From 7e437ed3a84504e2cad07c44f581b7957d11d16f Mon Sep 17 00:00:00 2001 From: Ross MacLeod Date: Tue, 30 Aug 2022 12:19:48 -0400 Subject: [PATCH] Add ATSAMDA1[EGJ] support --- hal/CHANGELOG.md | 1 + hal/Cargo.toml | 26 +- hal/README.md | 3 + hal/src/dmac/channel/mod.rs | 6 +- hal/src/dmac/channel/reg.rs | 4 +- hal/src/dmac/dma_controller.rs | 6 +- hal/src/dmac/mod.rs | 4 +- hal/src/gpio/dynpin.rs | 6 +- hal/src/gpio/pin.rs | 58 +- hal/src/gpio/reg.rs | 10 +- hal/src/lib.rs | 15 +- hal/src/rtc.rs | 21 +- hal/src/sercom/dma.rs | 12 +- hal/src/sercom/i2c.rs | 2 +- hal/src/sercom/i2c/pads_thumbv6m.rs | 2 +- hal/src/sercom/mod.rs | 12 +- hal/src/sercom/pad.rs | 2 +- hal/src/sercom/pad/impl_pad_thumbv6m.rs | 98 +- hal/src/sercom/spi.rs | 40 +- hal/src/sercom/spi/char_size.rs | 2 +- hal/src/sercom/spi/impl_ehal_thumbv6m.rs | 2 +- hal/src/sercom/spi/pads_thumbv6m.rs | 6 +- hal/src/sercom/spi/reg.rs | 14 +- hal/src/sercom/spi_future.rs | 8 +- hal/src/sercom/uart.rs | 4 +- hal/src/sercom/uart/config.rs | 2 +- hal/src/sercom/uart/pads_thumbv6m.rs | 4 +- hal/src/sercom/uart/reg.rs | 4 +- hal/src/thumbv6m/adc.rs | 6 +- hal/src/thumbv6m/calibration.rs | 5 + hal/src/thumbv6m/clock/v1.rs | 21 +- hal/src/thumbv6m/clock/v2/gclkio.rs | 24 +- hal/src/thumbv6m/clock/v2/osc32k.rs | 4 + hal/src/thumbv6m/clock/v2/pclk.rs | 6 +- hal/src/thumbv6m/clock/v2/types.rs | 4 +- hal/src/thumbv6m/clock/v2/xosc.rs | 4 + hal/src/thumbv6m/clock/v2/xosc32k.rs | 4 + hal/src/thumbv6m/eic/pin.rs | 86 +- hal/src/thumbv6m/mod.rs | 2 +- hal/src/thumbv6m/pwm.rs | 11 +- hal/src/thumbv6m/timer.rs | 8 +- hal/src/thumbv7em/clock/v1.rs | 4 + hal/src/thumbv7em/clock/v2.rs | 1 + pac/atsamda1e/Cargo.toml | 22 + pac/atsamda1e/README.md | 26 + pac/atsamda1e/build.rs | 16 + pac/atsamda1e/device.x | 29 + pac/atsamda1e/src/ac.rs | 80 + pac/atsamda1e/src/ac/compctrl.rs | 927 + pac/atsamda1e/src/ac/ctrla.rs | 254 + pac/atsamda1e/src/ac/ctrlb.rs | 99 + pac/atsamda1e/src/ac/evctrl.rs | 301 + pac/atsamda1e/src/ac/intenclr.rs | 207 + pac/atsamda1e/src/ac/intenset.rs | 207 + pac/atsamda1e/src/ac/intflag.rs | 207 + pac/atsamda1e/src/ac/scaler.rs | 104 + pac/atsamda1e/src/ac/statusa.rs | 135 + pac/atsamda1e/src/ac/statusb.rs | 93 + pac/atsamda1e/src/ac/statusc.rs | 135 + pac/atsamda1e/src/ac/winctrl.rs | 225 + pac/atsamda1e/src/adc.rs | 130 + pac/atsamda1e/src/adc/avgctrl.rs | 306 + pac/atsamda1e/src/adc/calib.rs | 140 + pac/atsamda1e/src/adc/ctrla.rs | 207 + pac/atsamda1e/src/adc/ctrlb.rs | 530 + pac/atsamda1e/src/adc/dbgctrl.rs | 113 + pac/atsamda1e/src/adc/evctrl.rs | 254 + pac/atsamda1e/src/adc/gaincorr.rs | 103 + pac/atsamda1e/src/adc/inputctrl.rs | 853 + pac/atsamda1e/src/adc/intenclr.rs | 254 + pac/atsamda1e/src/adc/intenset.rs | 254 + pac/atsamda1e/src/adc/intflag.rs | 254 + pac/atsamda1e/src/adc/offsetcorr.rs | 103 + pac/atsamda1e/src/adc/refctrl.rs | 238 + pac/atsamda1e/src/adc/result.rs | 53 + pac/atsamda1e/src/adc/sampctrl.rs | 103 + pac/atsamda1e/src/adc/status.rs | 53 + pac/atsamda1e/src/adc/swtrig.rs | 160 + pac/atsamda1e/src/adc/winctrl.rs | 191 + pac/atsamda1e/src/adc/winlt.rs | 103 + pac/atsamda1e/src/adc/winut.rs | 103 + pac/atsamda1e/src/dac.rs | 60 + pac/atsamda1e/src/dac/ctrla.rs | 207 + pac/atsamda1e/src/dac/ctrlb.rs | 400 + pac/atsamda1e/src/dac/data.rs | 103 + pac/atsamda1e/src/dac/databuf.rs | 103 + pac/atsamda1e/src/dac/evctrl.rs | 160 + pac/atsamda1e/src/dac/intenclr.rs | 207 + pac/atsamda1e/src/dac/intenset.rs | 207 + pac/atsamda1e/src/dac/intflag.rs | 207 + pac/atsamda1e/src/dac/status.rs | 53 + pac/atsamda1e/src/dmac.rs | 148 + pac/atsamda1e/src/dmac/active.rs | 173 + pac/atsamda1e/src/dmac/baseaddr.rs | 103 + pac/atsamda1e/src/dmac/busych.rs | 273 + pac/atsamda1e/src/dmac/chctrla.rs | 160 + pac/atsamda1e/src/dmac/chctrlb.rs | 1331 + pac/atsamda1e/src/dmac/chid.rs | 103 + pac/atsamda1e/src/dmac/chintenclr.rs | 207 + pac/atsamda1e/src/dmac/chintenset.rs | 207 + pac/atsamda1e/src/dmac/chintflag.rs | 207 + pac/atsamda1e/src/dmac/chstatus.rs | 93 + pac/atsamda1e/src/dmac/crcchksum.rs | 103 + pac/atsamda1e/src/dmac/crcctrl.rs | 337 + pac/atsamda1e/src/dmac/crcdatain.rs | 103 + pac/atsamda1e/src/dmac/crcstatus.rs | 160 + pac/atsamda1e/src/dmac/ctrl.rs | 395 + pac/atsamda1e/src/dmac/dbgctrl.rs | 113 + pac/atsamda1e/src/dmac/intpend.rs | 385 + pac/atsamda1e/src/dmac/intstatus.rs | 273 + pac/atsamda1e/src/dmac/pendch.rs | 273 + pac/atsamda1e/src/dmac/prictrl0.rs | 402 + pac/atsamda1e/src/dmac/qosctrl.rs | 402 + pac/atsamda1e/src/dmac/swtrigctrl.rs | 630 + pac/atsamda1e/src/dmac/wrbaddr.rs | 103 + pac/atsamda1e/src/dsu.rs | 134 + pac/atsamda1e/src/dsu/addr.rs | 103 + pac/atsamda1e/src/dsu/cid0.rs | 53 + pac/atsamda1e/src/dsu/cid1.rs | 73 + pac/atsamda1e/src/dsu/cid2.rs | 53 + pac/atsamda1e/src/dsu/cid3.rs | 53 + pac/atsamda1e/src/dsu/ctrl.rs | 153 + pac/atsamda1e/src/dsu/data.rs | 103 + pac/atsamda1e/src/dsu/dcc.rs | 104 + pac/atsamda1e/src/dsu/did.rs | 153 + pac/atsamda1e/src/dsu/end.rs | 53 + pac/atsamda1e/src/dsu/entry0.rs | 93 + pac/atsamda1e/src/dsu/entry1.rs | 31 + pac/atsamda1e/src/dsu/length.rs | 103 + pac/atsamda1e/src/dsu/memtype.rs | 53 + pac/atsamda1e/src/dsu/pid0.rs | 53 + pac/atsamda1e/src/dsu/pid1.rs | 73 + pac/atsamda1e/src/dsu/pid2.rs | 93 + pac/atsamda1e/src/dsu/pid3.rs | 73 + pac/atsamda1e/src/dsu/pid4.rs | 73 + pac/atsamda1e/src/dsu/statusa.rs | 301 + pac/atsamda1e/src/dsu/statusb.rs | 133 + pac/atsamda1e/src/eic.rs | 64 + pac/atsamda1e/src/eic/config.rs | 1547 ++ pac/atsamda1e/src/eic/ctrl.rs | 160 + pac/atsamda1e/src/eic/evctrl.rs | 818 + pac/atsamda1e/src/eic/intenclr.rs | 818 + pac/atsamda1e/src/eic/intenset.rs | 818 + pac/atsamda1e/src/eic/intflag.rs | 818 + pac/atsamda1e/src/eic/nmictrl.rs | 251 + pac/atsamda1e/src/eic/nmiflag.rs | 113 + pac/atsamda1e/src/eic/status.rs | 53 + pac/atsamda1e/src/eic/wakeup.rs | 818 + pac/atsamda1e/src/evsys.rs | 48 + pac/atsamda1e/src/evsys/channel.rs | 398 + pac/atsamda1e/src/evsys/chstatus.rs | 513 + pac/atsamda1e/src/evsys/ctrl.rs | 99 + pac/atsamda1e/src/evsys/intenclr.rs | 1194 + pac/atsamda1e/src/evsys/intenset.rs | 1194 + pac/atsamda1e/src/evsys/intflag.rs | 1194 + pac/atsamda1e/src/evsys/user.rs | 176 + pac/atsamda1e/src/gclk.rs | 34 + pac/atsamda1e/src/gclk/clkctrl.rs | 865 + pac/atsamda1e/src/gclk/ctrl.rs | 113 + pac/atsamda1e/src/gclk/genctrl.rs | 609 + pac/atsamda1e/src/gclk/gendiv.rs | 140 + pac/atsamda1e/src/gclk/status.rs | 53 + pac/atsamda1e/src/generic.rs | 260 + pac/atsamda1e/src/i2s.rs | 58 + pac/atsamda1e/src/i2s/clkctrl.rs | 1013 + pac/atsamda1e/src/i2s/ctrla.rs | 348 + pac/atsamda1e/src/i2s/data.rs | 104 + pac/atsamda1e/src/i2s/intenclr.rs | 442 + pac/atsamda1e/src/i2s/intenset.rs | 442 + pac/atsamda1e/src/i2s/intflag.rs | 442 + pac/atsamda1e/src/i2s/serctrl.rs | 1622 ++ pac/atsamda1e/src/i2s/syncbusy.rs | 193 + pac/atsamda1e/src/lib.rs | 1452 + pac/atsamda1e/src/mtb.rs | 158 + pac/atsamda1e/src/mtb/authstatus.rs | 31 + pac/atsamda1e/src/mtb/base.rs | 31 + pac/atsamda1e/src/mtb/cid0.rs | 31 + pac/atsamda1e/src/mtb/cid1.rs | 31 + pac/atsamda1e/src/mtb/cid2.rs | 31 + pac/atsamda1e/src/mtb/cid3.rs | 31 + pac/atsamda1e/src/mtb/claimclr.rs | 64 + pac/atsamda1e/src/mtb/claimset.rs | 64 + pac/atsamda1e/src/mtb/devarch.rs | 31 + pac/atsamda1e/src/mtb/devid.rs | 31 + pac/atsamda1e/src/mtb/devtype.rs | 31 + pac/atsamda1e/src/mtb/flow.rs | 197 + pac/atsamda1e/src/mtb/itctrl.rs | 64 + pac/atsamda1e/src/mtb/lockaccess.rs | 64 + pac/atsamda1e/src/mtb/lockstatus.rs | 31 + pac/atsamda1e/src/mtb/master.rs | 385 + pac/atsamda1e/src/mtb/pid0.rs | 31 + pac/atsamda1e/src/mtb/pid1.rs | 31 + pac/atsamda1e/src/mtb/pid2.rs | 31 + pac/atsamda1e/src/mtb/pid3.rs | 31 + pac/atsamda1e/src/mtb/pid4.rs | 31 + pac/atsamda1e/src/mtb/pid5.rs | 31 + pac/atsamda1e/src/mtb/pid6.rs | 31 + pac/atsamda1e/src/mtb/pid7.rs | 31 + pac/atsamda1e/src/mtb/position.rs | 150 + pac/atsamda1e/src/nvmctrl.rs | 63 + pac/atsamda1e/src/nvmctrl/addr.rs | 103 + pac/atsamda1e/src/nvmctrl/ctrla.rs | 394 + pac/atsamda1e/src/nvmctrl/ctrlb.rs | 457 + pac/atsamda1e/src/nvmctrl/intenclr.rs | 160 + pac/atsamda1e/src/nvmctrl/intenset.rs | 160 + pac/atsamda1e/src/nvmctrl/intflag.rs | 160 + pac/atsamda1e/src/nvmctrl/lock.rs | 103 + pac/atsamda1e/src/nvmctrl/param.rs | 304 + pac/atsamda1e/src/nvmctrl/status.rs | 348 + pac/atsamda1e/src/pac0.rs | 16 + pac/atsamda1e/src/pac0/wpclr.rs | 103 + pac/atsamda1e/src/pac0/wpset.rs | 103 + pac/atsamda1e/src/pm.rs | 98 + pac/atsamda1e/src/pm/ahbmask.rs | 395 + pac/atsamda1e/src/pm/apbamask.rs | 395 + pac/atsamda1e/src/pm/apbasel.rs | 230 + pac/atsamda1e/src/pm/apbbmask.rs | 395 + pac/atsamda1e/src/pm/apbbsel.rs | 230 + pac/atsamda1e/src/pm/apbcmask.rs | 1053 + pac/atsamda1e/src/pm/apbcsel.rs | 230 + pac/atsamda1e/src/pm/cpusel.rs | 230 + pac/atsamda1e/src/pm/ctrl.rs | 64 + pac/atsamda1e/src/pm/extctrl.rs | 113 + pac/atsamda1e/src/pm/intenclr.rs | 113 + pac/atsamda1e/src/pm/intenset.rs | 113 + pac/atsamda1e/src/pm/intflag.rs | 113 + pac/atsamda1e/src/pm/rcause.rs | 153 + pac/atsamda1e/src/pm/sleep.rs | 165 + pac/atsamda1e/src/port.rs | 40 + pac/atsamda1e/src/port/group.rs | 52 + pac/atsamda1e/src/port/group/ctrl.rs | 103 + pac/atsamda1e/src/port/group/dir.rs | 103 + pac/atsamda1e/src/port/group/dirclr.rs | 103 + pac/atsamda1e/src/port/group/dirset.rs | 103 + pac/atsamda1e/src/port/group/dirtgl.rs | 103 + pac/atsamda1e/src/port/group/in_.rs | 53 + pac/atsamda1e/src/port/group/out.rs | 103 + pac/atsamda1e/src/port/group/outclr.rs | 103 + pac/atsamda1e/src/port/group/outset.rs | 103 + pac/atsamda1e/src/port/group/outtgl.rs | 103 + pac/atsamda1e/src/port/group/pincfg.rs | 255 + pac/atsamda1e/src/port/group/pmux.rs | 395 + pac/atsamda1e/src/port/group/wrconfig.rs | 268 + pac/atsamda1e/src/rtc.rs | 123 + pac/atsamda1e/src/rtc/mode0.rs | 44 + pac/atsamda1e/src/rtc/mode0/comp.rs | 103 + pac/atsamda1e/src/rtc/mode0/count.rs | 103 + pac/atsamda1e/src/rtc/mode0/ctrl.rs | 509 + pac/atsamda1e/src/rtc/mode0/dbgctrl.rs | 113 + pac/atsamda1e/src/rtc/mode0/evctrl.rs | 536 + pac/atsamda1e/src/rtc/mode0/freqcorr.rs | 150 + pac/atsamda1e/src/rtc/mode0/intenclr.rs | 207 + pac/atsamda1e/src/rtc/mode0/intenset.rs | 207 + pac/atsamda1e/src/rtc/mode0/intflag.rs | 207 + pac/atsamda1e/src/rtc/mode0/readreq.rs | 197 + pac/atsamda1e/src/rtc/mode0/status.rs | 113 + pac/atsamda1e/src/rtc/mode1.rs | 48 + pac/atsamda1e/src/rtc/mode1/comp.rs | 104 + pac/atsamda1e/src/rtc/mode1/count.rs | 103 + pac/atsamda1e/src/rtc/mode1/ctrl.rs | 462 + pac/atsamda1e/src/rtc/mode1/dbgctrl.rs | 113 + pac/atsamda1e/src/rtc/mode1/evctrl.rs | 583 + pac/atsamda1e/src/rtc/mode1/freqcorr.rs | 150 + pac/atsamda1e/src/rtc/mode1/intenclr.rs | 254 + pac/atsamda1e/src/rtc/mode1/intenset.rs | 254 + pac/atsamda1e/src/rtc/mode1/intflag.rs | 254 + pac/atsamda1e/src/rtc/mode1/per.rs | 103 + pac/atsamda1e/src/rtc/mode1/readreq.rs | 197 + pac/atsamda1e/src/rtc/mode1/status.rs | 113 + pac/atsamda1e/src/rtc/mode2.rs | 48 + pac/atsamda1e/src/rtc/mode2/alarm.rs | 337 + pac/atsamda1e/src/rtc/mode2/clock.rs | 337 + pac/atsamda1e/src/rtc/mode2/ctrl.rs | 556 + pac/atsamda1e/src/rtc/mode2/dbgctrl.rs | 113 + pac/atsamda1e/src/rtc/mode2/evctrl.rs | 536 + pac/atsamda1e/src/rtc/mode2/freqcorr.rs | 150 + pac/atsamda1e/src/rtc/mode2/intenclr.rs | 207 + pac/atsamda1e/src/rtc/mode2/intenset.rs | 207 + pac/atsamda1e/src/rtc/mode2/intflag.rs | 207 + pac/atsamda1e/src/rtc/mode2/mask.rs | 217 + pac/atsamda1e/src/rtc/mode2/readreq.rs | 197 + pac/atsamda1e/src/rtc/mode2/status.rs | 113 + pac/atsamda1e/src/sbmatrix.rs | 25 + pac/atsamda1e/src/sbmatrix/prs.rs | 8 + pac/atsamda1e/src/sbmatrix/prs/pras.rs | 64 + pac/atsamda1e/src/sbmatrix/prs/prbs.rs | 64 + pac/atsamda1e/src/sbmatrix/sfr.rs | 104 + pac/atsamda1e/src/sercom0.rs | 325 + pac/atsamda1e/src/sercom0/i2cm.rs | 44 + pac/atsamda1e/src/sercom0/i2cm/addr.rs | 281 + pac/atsamda1e/src/sercom0/i2cm/baud.rs | 214 + pac/atsamda1e/src/sercom0/i2cm/ctrla.rs | 903 + pac/atsamda1e/src/sercom0/i2cm/ctrlb.rs | 244 + pac/atsamda1e/src/sercom0/i2cm/data.rs | 103 + pac/atsamda1e/src/sercom0/i2cm/dbgctrl.rs | 113 + pac/atsamda1e/src/sercom0/i2cm/intenclr.rs | 207 + pac/atsamda1e/src/sercom0/i2cm/intenset.rs | 207 + pac/atsamda1e/src/sercom0/i2cm/intflag.rs | 207 + pac/atsamda1e/src/sercom0/i2cm/status.rs | 479 + pac/atsamda1e/src/sercom0/i2cm/syncbusy.rs | 93 + pac/atsamda1e/src/sercom0/i2cs.rs | 36 + pac/atsamda1e/src/sercom0/i2cs/addr.rs | 234 + pac/atsamda1e/src/sercom0/i2cs/ctrla.rs | 744 + pac/atsamda1e/src/sercom0/i2cs/ctrlb.rs | 328 + pac/atsamda1e/src/sercom0/i2cs/data.rs | 103 + pac/atsamda1e/src/sercom0/i2cs/intenclr.rs | 254 + pac/atsamda1e/src/sercom0/i2cs/intenset.rs | 254 + pac/atsamda1e/src/sercom0/i2cs/intflag.rs | 254 + pac/atsamda1e/src/sercom0/i2cs/status.rs | 489 + pac/atsamda1e/src/sercom0/i2cs/syncbusy.rs | 73 + pac/atsamda1e/src/sercom0/spim.rs | 44 + pac/atsamda1e/src/sercom0/spim/addr.rs | 140 + pac/atsamda1e/src/sercom0/spim/baud.rs | 103 + pac/atsamda1e/src/sercom0/spim/ctrla.rs | 992 + pac/atsamda1e/src/sercom0/spim/ctrlb.rs | 439 + pac/atsamda1e/src/sercom0/spim/data.rs | 103 + pac/atsamda1e/src/sercom0/spim/dbgctrl.rs | 113 + pac/atsamda1e/src/sercom0/spim/intenclr.rs | 301 + pac/atsamda1e/src/sercom0/spim/intenset.rs | 301 + pac/atsamda1e/src/sercom0/spim/intflag.rs | 301 + pac/atsamda1e/src/sercom0/spim/status.rs | 113 + pac/atsamda1e/src/sercom0/spim/syncbusy.rs | 93 + pac/atsamda1e/src/sercom0/spis.rs | 44 + pac/atsamda1e/src/sercom0/spis/addr.rs | 140 + pac/atsamda1e/src/sercom0/spis/baud.rs | 103 + pac/atsamda1e/src/sercom0/spis/ctrla.rs | 992 + pac/atsamda1e/src/sercom0/spis/ctrlb.rs | 439 + pac/atsamda1e/src/sercom0/spis/data.rs | 103 + pac/atsamda1e/src/sercom0/spis/dbgctrl.rs | 113 + pac/atsamda1e/src/sercom0/spis/intenclr.rs | 301 + pac/atsamda1e/src/sercom0/spis/intenset.rs | 301 + pac/atsamda1e/src/sercom0/spis/intflag.rs | 301 + pac/atsamda1e/src/sercom0/spis/status.rs | 113 + pac/atsamda1e/src/sercom0/spis/syncbusy.rs | 93 + pac/atsamda1e/src/sercom0/usart_ext.rs | 56 + pac/atsamda1e/src/sercom0/usart_ext/baud.rs | 103 + .../src/sercom0/usart_ext/baud_frac_mode.rs | 140 + .../src/sercom0/usart_ext/baud_fracfp_mode.rs | 140 + .../sercom0/usart_ext/baud_usartfp_mode.rs | 103 + pac/atsamda1e/src/sercom0/usart_ext/ctrla.rs | 1256 + pac/atsamda1e/src/sercom0/usart_ext/ctrlb.rs | 614 + pac/atsamda1e/src/sercom0/usart_ext/data.rs | 103 + .../src/sercom0/usart_ext/dbgctrl.rs | 113 + .../src/sercom0/usart_ext/intenclr.rs | 395 + .../src/sercom0/usart_ext/intenset.rs | 395 + .../src/sercom0/usart_ext/intflag.rs | 395 + pac/atsamda1e/src/sercom0/usart_ext/rxpl.rs | 103 + pac/atsamda1e/src/sercom0/usart_ext/status.rs | 395 + .../src/sercom0/usart_ext/syncbusy.rs | 93 + pac/atsamda1e/src/sercom0/usart_int.rs | 56 + pac/atsamda1e/src/sercom0/usart_int/baud.rs | 103 + .../src/sercom0/usart_int/baud_frac_mode.rs | 140 + .../src/sercom0/usart_int/baud_fracfp_mode.rs | 140 + .../sercom0/usart_int/baud_usartfp_mode.rs | 103 + pac/atsamda1e/src/sercom0/usart_int/ctrla.rs | 1256 + pac/atsamda1e/src/sercom0/usart_int/ctrlb.rs | 614 + pac/atsamda1e/src/sercom0/usart_int/data.rs | 103 + .../src/sercom0/usart_int/dbgctrl.rs | 113 + .../src/sercom0/usart_int/intenclr.rs | 395 + .../src/sercom0/usart_int/intenset.rs | 395 + .../src/sercom0/usart_int/intflag.rs | 395 + pac/atsamda1e/src/sercom0/usart_int/rxpl.rs | 103 + pac/atsamda1e/src/sercom0/usart_int/status.rs | 395 + .../src/sercom0/usart_int/syncbusy.rs | 93 + pac/atsamda1e/src/sys_tick.rs | 28 + pac/atsamda1e/src/sys_tick/calib.rs | 157 + pac/atsamda1e/src/sys_tick/csr.rs | 395 + pac/atsamda1e/src/sys_tick/cvr.rs | 103 + pac/atsamda1e/src/sys_tick/rvr.rs | 103 + pac/atsamda1e/src/sysctrl.rs | 132 + pac/atsamda1e/src/sysctrl/bod33.rs | 705 + pac/atsamda1e/src/sysctrl/dfllctrl.rs | 583 + pac/atsamda1e/src/sysctrl/dfllmul.rs | 177 + pac/atsamda1e/src/sysctrl/dfllsync.rs | 113 + pac/atsamda1e/src/sysctrl/dfllval.rs | 177 + pac/atsamda1e/src/sysctrl/dpllctrla.rs | 207 + pac/atsamda1e/src/sysctrl/dpllctrlb.rs | 580 + pac/atsamda1e/src/sysctrl/dpllratio.rs | 140 + pac/atsamda1e/src/sysctrl/dpllstatus.rs | 113 + pac/atsamda1e/src/sysctrl/intenclr.rs | 771 + pac/atsamda1e/src/sysctrl/intenset.rs | 771 + pac/atsamda1e/src/sysctrl/intflag.rs | 771 + pac/atsamda1e/src/sysctrl/osc32k.rs | 549 + pac/atsamda1e/src/sysctrl/osc8m.rs | 468 + pac/atsamda1e/src/sysctrl/osculp32k.rs | 150 + pac/atsamda1e/src/sysctrl/pclksr.rs | 333 + pac/atsamda1e/src/sysctrl/vref.rs | 197 + pac/atsamda1e/src/sysctrl/vreg.rs | 160 + pac/atsamda1e/src/sysctrl/xosc.rs | 694 + pac/atsamda1e/src/sysctrl/xosc32k.rs | 606 + pac/atsamda1e/src/system_control.rs | 67 + pac/atsamda1e/src/system_control/aircr.rs | 338 + pac/atsamda1e/src/system_control/ccr.rs | 137 + pac/atsamda1e/src/system_control/cpuid.rs | 133 + pac/atsamda1e/src/system_control/dfsr.rs | 301 + pac/atsamda1e/src/system_control/icsr.rs | 704 + pac/atsamda1e/src/system_control/scr.rs | 348 + pac/atsamda1e/src/system_control/shcsr.rs | 113 + pac/atsamda1e/src/system_control/shpr2.rs | 103 + pac/atsamda1e/src/system_control/shpr3.rs | 140 + pac/atsamda1e/src/system_control/vtor.rs | 103 + pac/atsamda1e/src/tc3.rs | 133 + pac/atsamda1e/src/tc3/count16.rs | 52 + pac/atsamda1e/src/tc3/count16/cc.rs | 104 + pac/atsamda1e/src/tc3/count16/count.rs | 103 + pac/atsamda1e/src/tc3/count16/ctrla.rs | 681 + pac/atsamda1e/src/tc3/count16/ctrlbclr.rs | 259 + pac/atsamda1e/src/tc3/count16/ctrlbset.rs | 259 + pac/atsamda1e/src/tc3/count16/ctrlc.rs | 254 + pac/atsamda1e/src/tc3/count16/dbgctrl.rs | 113 + pac/atsamda1e/src/tc3/count16/evctrl.rs | 439 + pac/atsamda1e/src/tc3/count16/intenclr.rs | 301 + pac/atsamda1e/src/tc3/count16/intenset.rs | 301 + pac/atsamda1e/src/tc3/count16/intflag.rs | 301 + pac/atsamda1e/src/tc3/count16/readreq.rs | 197 + pac/atsamda1e/src/tc3/count16/status.rs | 93 + pac/atsamda1e/src/tc3/count32.rs | 52 + pac/atsamda1e/src/tc3/count32/cc.rs | 104 + pac/atsamda1e/src/tc3/count32/count.rs | 103 + pac/atsamda1e/src/tc3/count32/ctrla.rs | 681 + pac/atsamda1e/src/tc3/count32/ctrlbclr.rs | 259 + pac/atsamda1e/src/tc3/count32/ctrlbset.rs | 259 + pac/atsamda1e/src/tc3/count32/ctrlc.rs | 254 + pac/atsamda1e/src/tc3/count32/dbgctrl.rs | 113 + pac/atsamda1e/src/tc3/count32/evctrl.rs | 439 + pac/atsamda1e/src/tc3/count32/intenclr.rs | 301 + pac/atsamda1e/src/tc3/count32/intenset.rs | 301 + pac/atsamda1e/src/tc3/count32/intflag.rs | 301 + pac/atsamda1e/src/tc3/count32/readreq.rs | 197 + pac/atsamda1e/src/tc3/count32/status.rs | 93 + pac/atsamda1e/src/tc3/count8.rs | 56 + pac/atsamda1e/src/tc3/count8/cc.rs | 104 + pac/atsamda1e/src/tc3/count8/count.rs | 103 + pac/atsamda1e/src/tc3/count8/ctrla.rs | 681 + pac/atsamda1e/src/tc3/count8/ctrlbclr.rs | 259 + pac/atsamda1e/src/tc3/count8/ctrlbset.rs | 259 + pac/atsamda1e/src/tc3/count8/ctrlc.rs | 254 + pac/atsamda1e/src/tc3/count8/dbgctrl.rs | 113 + pac/atsamda1e/src/tc3/count8/evctrl.rs | 439 + pac/atsamda1e/src/tc3/count8/intenclr.rs | 301 + pac/atsamda1e/src/tc3/count8/intenset.rs | 301 + pac/atsamda1e/src/tc3/count8/intflag.rs | 301 + pac/atsamda1e/src/tc3/count8/per.rs | 103 + pac/atsamda1e/src/tc3/count8/readreq.rs | 197 + pac/atsamda1e/src/tc3/count8/status.rs | 93 + pac/atsamda1e/src/tcc0.rs | 365 + pac/atsamda1e/src/tcc0/cc.rs | 104 + pac/atsamda1e/src/tcc0/cc_dith4_mode.rs | 141 + pac/atsamda1e/src/tcc0/cc_dith5_mode.rs | 141 + pac/atsamda1e/src/tcc0/cc_dith6_mode.rs | 141 + pac/atsamda1e/src/tcc0/ccb.rs | 104 + pac/atsamda1e/src/tcc0/ccb_dith4_mode.rs | 141 + pac/atsamda1e/src/tcc0/ccb_dith5_mode.rs | 141 + pac/atsamda1e/src/tcc0/ccb_dith6_mode.rs | 141 + pac/atsamda1e/src/tcc0/count.rs | 103 + pac/atsamda1e/src/tcc0/count_dith4_mode.rs | 103 + pac/atsamda1e/src/tcc0/count_dith5_mode.rs | 103 + pac/atsamda1e/src/tcc0/count_dith6_mode.rs | 103 + pac/atsamda1e/src/tcc0/ctrla.rs | 817 + pac/atsamda1e/src/tcc0/ctrlbclr.rs | 444 + pac/atsamda1e/src/tcc0/ctrlbset.rs | 444 + pac/atsamda1e/src/tcc0/dbgctrl.rs | 160 + pac/atsamda1e/src/tcc0/drvctrl.rs | 1268 + pac/atsamda1e/src/tcc0/evctrl.rs | 1198 + pac/atsamda1e/src/tcc0/fctrla.rs | 880 + pac/atsamda1e/src/tcc0/fctrlb.rs | 880 + pac/atsamda1e/src/tcc0/intenclr.rs | 677 + pac/atsamda1e/src/tcc0/intenset.rs | 677 + pac/atsamda1e/src/tcc0/intflag.rs | 677 + pac/atsamda1e/src/tcc0/patt.rs | 818 + pac/atsamda1e/src/tcc0/pattb.rs | 818 + pac/atsamda1e/src/tcc0/per.rs | 103 + pac/atsamda1e/src/tcc0/per_dith4_mode.rs | 140 + pac/atsamda1e/src/tcc0/per_dith5_mode.rs | 140 + pac/atsamda1e/src/tcc0/per_dith6_mode.rs | 140 + pac/atsamda1e/src/tcc0/perb.rs | 103 + pac/atsamda1e/src/tcc0/perb_dith4_mode.rs | 140 + pac/atsamda1e/src/tcc0/perb_dith5_mode.rs | 140 + pac/atsamda1e/src/tcc0/perb_dith6_mode.rs | 140 + pac/atsamda1e/src/tcc0/status.rs | 1147 + pac/atsamda1e/src/tcc0/syncbusy.rs | 413 + pac/atsamda1e/src/tcc0/wave.rs | 927 + pac/atsamda1e/src/tcc0/waveb.rs | 927 + pac/atsamda1e/src/tcc0/wexctrl.rs | 365 + pac/atsamda1e/src/usb.rs | 155 + pac/atsamda1e/src/usb/device.rs | 78 + pac/atsamda1e/src/usb/device/ctrla.rs | 301 + pac/atsamda1e/src/usb/device/ctrlb.rs | 666 + pac/atsamda1e/src/usb/device/dadd.rs | 150 + pac/atsamda1e/src/usb/device/descadd.rs | 103 + .../src/usb/device/device_endpoint.rs | 28 + .../src/usb/device/device_endpoint/epcfg.rs | 187 + .../usb/device/device_endpoint/epintenclr.rs | 395 + .../usb/device/device_endpoint/epintenset.rs | 395 + .../usb/device/device_endpoint/epintflag.rs | 395 + .../usb/device/device_endpoint/epstatus.rs | 173 + .../usb/device/device_endpoint/epstatusclr.rs | 234 + .../usb/device/device_endpoint/epstatusset.rs | 234 + pac/atsamda1e/src/usb/device/epintsmry.rs | 193 + pac/atsamda1e/src/usb/device/fnum.rs | 93 + pac/atsamda1e/src/usb/device/fsmstatus.rs | 127 + pac/atsamda1e/src/usb/device/intenclr.rs | 536 + pac/atsamda1e/src/usb/device/intenset.rs | 536 + pac/atsamda1e/src/usb/device/intflag.rs | 536 + pac/atsamda1e/src/usb/device/padcal.rs | 177 + pac/atsamda1e/src/usb/device/qosctrl.rs | 290 + pac/atsamda1e/src/usb/device/status.rs | 157 + pac/atsamda1e/src/usb/device/syncbusy.rs | 73 + pac/atsamda1e/src/usb/host.rs | 84 + pac/atsamda1e/src/usb/host/ctrla.rs | 301 + pac/atsamda1e/src/usb/host/ctrlb.rs | 481 + pac/atsamda1e/src/usb/host/descadd.rs | 103 + pac/atsamda1e/src/usb/host/flenhigh.rs | 53 + pac/atsamda1e/src/usb/host/fnum.rs | 140 + pac/atsamda1e/src/usb/host/fsmstatus.rs | 127 + pac/atsamda1e/src/usb/host/host_pipe.rs | 32 + .../src/usb/host/host_pipe/binterval.rs | 103 + pac/atsamda1e/src/usb/host/host_pipe/pcfg.rs | 187 + .../src/usb/host/host_pipe/pintenclr.rs | 348 + .../src/usb/host/host_pipe/pintenset.rs | 348 + .../src/usb/host/host_pipe/pintflag.rs | 348 + .../src/usb/host/host_pipe/pstatus.rs | 133 + .../src/usb/host/host_pipe/pstatusclr.rs | 180 + .../src/usb/host/host_pipe/pstatusset.rs | 180 + pac/atsamda1e/src/usb/host/hsofc.rs | 150 + pac/atsamda1e/src/usb/host/intenclr.rs | 442 + pac/atsamda1e/src/usb/host/intenset.rs | 442 + pac/atsamda1e/src/usb/host/intflag.rs | 442 + pac/atsamda1e/src/usb/host/padcal.rs | 177 + pac/atsamda1e/src/usb/host/pintsmry.rs | 193 + pac/atsamda1e/src/usb/host/qosctrl.rs | 290 + pac/atsamda1e/src/usb/host/status.rs | 140 + pac/atsamda1e/src/usb/host/syncbusy.rs | 73 + pac/atsamda1e/src/wdt.rs | 53 + pac/atsamda1e/src/wdt/clear.rs | 85 + pac/atsamda1e/src/wdt/config.rs | 498 + pac/atsamda1e/src/wdt/ctrl.rs | 207 + pac/atsamda1e/src/wdt/ewctrl.rs | 282 + pac/atsamda1e/src/wdt/intenclr.rs | 113 + pac/atsamda1e/src/wdt/intenset.rs | 113 + pac/atsamda1e/src/wdt/intflag.rs | 113 + pac/atsamda1e/src/wdt/status.rs | 53 + pac/atsamda1g/Cargo.toml | 22 + pac/atsamda1g/README.md | 26 + pac/atsamda1g/build.rs | 16 + pac/atsamda1g/device.x | 29 + pac/atsamda1g/src/ac.rs | 80 + pac/atsamda1g/src/ac/compctrl.rs | 927 + pac/atsamda1g/src/ac/ctrla.rs | 254 + pac/atsamda1g/src/ac/ctrlb.rs | 99 + pac/atsamda1g/src/ac/evctrl.rs | 301 + pac/atsamda1g/src/ac/intenclr.rs | 207 + pac/atsamda1g/src/ac/intenset.rs | 207 + pac/atsamda1g/src/ac/intflag.rs | 207 + pac/atsamda1g/src/ac/scaler.rs | 104 + pac/atsamda1g/src/ac/statusa.rs | 135 + pac/atsamda1g/src/ac/statusb.rs | 93 + pac/atsamda1g/src/ac/statusc.rs | 135 + pac/atsamda1g/src/ac/winctrl.rs | 225 + pac/atsamda1g/src/adc.rs | 130 + pac/atsamda1g/src/adc/avgctrl.rs | 306 + pac/atsamda1g/src/adc/calib.rs | 140 + pac/atsamda1g/src/adc/ctrla.rs | 207 + pac/atsamda1g/src/adc/ctrlb.rs | 530 + pac/atsamda1g/src/adc/dbgctrl.rs | 113 + pac/atsamda1g/src/adc/evctrl.rs | 254 + pac/atsamda1g/src/adc/gaincorr.rs | 103 + pac/atsamda1g/src/adc/inputctrl.rs | 853 + pac/atsamda1g/src/adc/intenclr.rs | 254 + pac/atsamda1g/src/adc/intenset.rs | 254 + pac/atsamda1g/src/adc/intflag.rs | 254 + pac/atsamda1g/src/adc/offsetcorr.rs | 103 + pac/atsamda1g/src/adc/refctrl.rs | 238 + pac/atsamda1g/src/adc/result.rs | 53 + pac/atsamda1g/src/adc/sampctrl.rs | 103 + pac/atsamda1g/src/adc/status.rs | 53 + pac/atsamda1g/src/adc/swtrig.rs | 160 + pac/atsamda1g/src/adc/winctrl.rs | 191 + pac/atsamda1g/src/adc/winlt.rs | 103 + pac/atsamda1g/src/adc/winut.rs | 103 + pac/atsamda1g/src/dac.rs | 60 + pac/atsamda1g/src/dac/ctrla.rs | 207 + pac/atsamda1g/src/dac/ctrlb.rs | 400 + pac/atsamda1g/src/dac/data.rs | 103 + pac/atsamda1g/src/dac/databuf.rs | 103 + pac/atsamda1g/src/dac/evctrl.rs | 160 + pac/atsamda1g/src/dac/intenclr.rs | 207 + pac/atsamda1g/src/dac/intenset.rs | 207 + pac/atsamda1g/src/dac/intflag.rs | 207 + pac/atsamda1g/src/dac/status.rs | 53 + pac/atsamda1g/src/dmac.rs | 148 + pac/atsamda1g/src/dmac/active.rs | 173 + pac/atsamda1g/src/dmac/baseaddr.rs | 103 + pac/atsamda1g/src/dmac/busych.rs | 273 + pac/atsamda1g/src/dmac/chctrla.rs | 160 + pac/atsamda1g/src/dmac/chctrlb.rs | 1331 + pac/atsamda1g/src/dmac/chid.rs | 103 + pac/atsamda1g/src/dmac/chintenclr.rs | 207 + pac/atsamda1g/src/dmac/chintenset.rs | 207 + pac/atsamda1g/src/dmac/chintflag.rs | 207 + pac/atsamda1g/src/dmac/chstatus.rs | 93 + pac/atsamda1g/src/dmac/crcchksum.rs | 103 + pac/atsamda1g/src/dmac/crcctrl.rs | 337 + pac/atsamda1g/src/dmac/crcdatain.rs | 103 + pac/atsamda1g/src/dmac/crcstatus.rs | 160 + pac/atsamda1g/src/dmac/ctrl.rs | 395 + pac/atsamda1g/src/dmac/dbgctrl.rs | 113 + pac/atsamda1g/src/dmac/intpend.rs | 385 + pac/atsamda1g/src/dmac/intstatus.rs | 273 + pac/atsamda1g/src/dmac/pendch.rs | 273 + pac/atsamda1g/src/dmac/prictrl0.rs | 402 + pac/atsamda1g/src/dmac/qosctrl.rs | 402 + pac/atsamda1g/src/dmac/swtrigctrl.rs | 630 + pac/atsamda1g/src/dmac/wrbaddr.rs | 103 + pac/atsamda1g/src/dsu.rs | 134 + pac/atsamda1g/src/dsu/addr.rs | 103 + pac/atsamda1g/src/dsu/cid0.rs | 53 + pac/atsamda1g/src/dsu/cid1.rs | 73 + pac/atsamda1g/src/dsu/cid2.rs | 53 + pac/atsamda1g/src/dsu/cid3.rs | 53 + pac/atsamda1g/src/dsu/ctrl.rs | 153 + pac/atsamda1g/src/dsu/data.rs | 103 + pac/atsamda1g/src/dsu/dcc.rs | 104 + pac/atsamda1g/src/dsu/did.rs | 153 + pac/atsamda1g/src/dsu/end.rs | 53 + pac/atsamda1g/src/dsu/entry0.rs | 93 + pac/atsamda1g/src/dsu/entry1.rs | 31 + pac/atsamda1g/src/dsu/length.rs | 103 + pac/atsamda1g/src/dsu/memtype.rs | 53 + pac/atsamda1g/src/dsu/pid0.rs | 53 + pac/atsamda1g/src/dsu/pid1.rs | 73 + pac/atsamda1g/src/dsu/pid2.rs | 93 + pac/atsamda1g/src/dsu/pid3.rs | 73 + pac/atsamda1g/src/dsu/pid4.rs | 73 + pac/atsamda1g/src/dsu/statusa.rs | 301 + pac/atsamda1g/src/dsu/statusb.rs | 133 + pac/atsamda1g/src/eic.rs | 64 + pac/atsamda1g/src/eic/config.rs | 1547 ++ pac/atsamda1g/src/eic/ctrl.rs | 160 + pac/atsamda1g/src/eic/evctrl.rs | 818 + pac/atsamda1g/src/eic/intenclr.rs | 818 + pac/atsamda1g/src/eic/intenset.rs | 818 + pac/atsamda1g/src/eic/intflag.rs | 818 + pac/atsamda1g/src/eic/nmictrl.rs | 251 + pac/atsamda1g/src/eic/nmiflag.rs | 113 + pac/atsamda1g/src/eic/status.rs | 53 + pac/atsamda1g/src/eic/wakeup.rs | 818 + pac/atsamda1g/src/evsys.rs | 48 + pac/atsamda1g/src/evsys/channel.rs | 398 + pac/atsamda1g/src/evsys/chstatus.rs | 513 + pac/atsamda1g/src/evsys/ctrl.rs | 99 + pac/atsamda1g/src/evsys/intenclr.rs | 1194 + pac/atsamda1g/src/evsys/intenset.rs | 1194 + pac/atsamda1g/src/evsys/intflag.rs | 1194 + pac/atsamda1g/src/evsys/user.rs | 176 + pac/atsamda1g/src/gclk.rs | 34 + pac/atsamda1g/src/gclk/clkctrl.rs | 865 + pac/atsamda1g/src/gclk/ctrl.rs | 113 + pac/atsamda1g/src/gclk/genctrl.rs | 609 + pac/atsamda1g/src/gclk/gendiv.rs | 140 + pac/atsamda1g/src/gclk/status.rs | 53 + pac/atsamda1g/src/generic.rs | 260 + pac/atsamda1g/src/i2s.rs | 58 + pac/atsamda1g/src/i2s/clkctrl.rs | 1013 + pac/atsamda1g/src/i2s/ctrla.rs | 348 + pac/atsamda1g/src/i2s/data.rs | 104 + pac/atsamda1g/src/i2s/intenclr.rs | 442 + pac/atsamda1g/src/i2s/intenset.rs | 442 + pac/atsamda1g/src/i2s/intflag.rs | 442 + pac/atsamda1g/src/i2s/serctrl.rs | 1622 ++ pac/atsamda1g/src/i2s/syncbusy.rs | 193 + pac/atsamda1g/src/lib.rs | 1452 + pac/atsamda1g/src/mtb.rs | 158 + pac/atsamda1g/src/mtb/authstatus.rs | 31 + pac/atsamda1g/src/mtb/base.rs | 31 + pac/atsamda1g/src/mtb/cid0.rs | 31 + pac/atsamda1g/src/mtb/cid1.rs | 31 + pac/atsamda1g/src/mtb/cid2.rs | 31 + pac/atsamda1g/src/mtb/cid3.rs | 31 + pac/atsamda1g/src/mtb/claimclr.rs | 64 + pac/atsamda1g/src/mtb/claimset.rs | 64 + pac/atsamda1g/src/mtb/devarch.rs | 31 + pac/atsamda1g/src/mtb/devid.rs | 31 + pac/atsamda1g/src/mtb/devtype.rs | 31 + pac/atsamda1g/src/mtb/flow.rs | 197 + pac/atsamda1g/src/mtb/itctrl.rs | 64 + pac/atsamda1g/src/mtb/lockaccess.rs | 64 + pac/atsamda1g/src/mtb/lockstatus.rs | 31 + pac/atsamda1g/src/mtb/master.rs | 385 + pac/atsamda1g/src/mtb/pid0.rs | 31 + pac/atsamda1g/src/mtb/pid1.rs | 31 + pac/atsamda1g/src/mtb/pid2.rs | 31 + pac/atsamda1g/src/mtb/pid3.rs | 31 + pac/atsamda1g/src/mtb/pid4.rs | 31 + pac/atsamda1g/src/mtb/pid5.rs | 31 + pac/atsamda1g/src/mtb/pid6.rs | 31 + pac/atsamda1g/src/mtb/pid7.rs | 31 + pac/atsamda1g/src/mtb/position.rs | 150 + pac/atsamda1g/src/nvmctrl.rs | 63 + pac/atsamda1g/src/nvmctrl/addr.rs | 103 + pac/atsamda1g/src/nvmctrl/ctrla.rs | 394 + pac/atsamda1g/src/nvmctrl/ctrlb.rs | 457 + pac/atsamda1g/src/nvmctrl/intenclr.rs | 160 + pac/atsamda1g/src/nvmctrl/intenset.rs | 160 + pac/atsamda1g/src/nvmctrl/intflag.rs | 160 + pac/atsamda1g/src/nvmctrl/lock.rs | 103 + pac/atsamda1g/src/nvmctrl/param.rs | 304 + pac/atsamda1g/src/nvmctrl/status.rs | 348 + pac/atsamda1g/src/pac0.rs | 16 + pac/atsamda1g/src/pac0/wpclr.rs | 103 + pac/atsamda1g/src/pac0/wpset.rs | 103 + pac/atsamda1g/src/pm.rs | 98 + pac/atsamda1g/src/pm/ahbmask.rs | 395 + pac/atsamda1g/src/pm/apbamask.rs | 395 + pac/atsamda1g/src/pm/apbasel.rs | 230 + pac/atsamda1g/src/pm/apbbmask.rs | 395 + pac/atsamda1g/src/pm/apbbsel.rs | 230 + pac/atsamda1g/src/pm/apbcmask.rs | 1053 + pac/atsamda1g/src/pm/apbcsel.rs | 230 + pac/atsamda1g/src/pm/cpusel.rs | 230 + pac/atsamda1g/src/pm/ctrl.rs | 64 + pac/atsamda1g/src/pm/extctrl.rs | 113 + pac/atsamda1g/src/pm/intenclr.rs | 113 + pac/atsamda1g/src/pm/intenset.rs | 113 + pac/atsamda1g/src/pm/intflag.rs | 113 + pac/atsamda1g/src/pm/rcause.rs | 153 + pac/atsamda1g/src/pm/sleep.rs | 165 + pac/atsamda1g/src/port.rs | 43 + pac/atsamda1g/src/port/group.rs | 52 + pac/atsamda1g/src/port/group/ctrl.rs | 103 + pac/atsamda1g/src/port/group/dir.rs | 103 + pac/atsamda1g/src/port/group/dirclr.rs | 103 + pac/atsamda1g/src/port/group/dirset.rs | 103 + pac/atsamda1g/src/port/group/dirtgl.rs | 103 + pac/atsamda1g/src/port/group/in_.rs | 53 + pac/atsamda1g/src/port/group/out.rs | 103 + pac/atsamda1g/src/port/group/outclr.rs | 103 + pac/atsamda1g/src/port/group/outset.rs | 103 + pac/atsamda1g/src/port/group/outtgl.rs | 103 + pac/atsamda1g/src/port/group/pincfg.rs | 255 + pac/atsamda1g/src/port/group/pmux.rs | 395 + pac/atsamda1g/src/port/group/wrconfig.rs | 268 + pac/atsamda1g/src/rtc.rs | 123 + pac/atsamda1g/src/rtc/mode0.rs | 44 + pac/atsamda1g/src/rtc/mode0/comp.rs | 103 + pac/atsamda1g/src/rtc/mode0/count.rs | 103 + pac/atsamda1g/src/rtc/mode0/ctrl.rs | 509 + pac/atsamda1g/src/rtc/mode0/dbgctrl.rs | 113 + pac/atsamda1g/src/rtc/mode0/evctrl.rs | 536 + pac/atsamda1g/src/rtc/mode0/freqcorr.rs | 150 + pac/atsamda1g/src/rtc/mode0/intenclr.rs | 207 + pac/atsamda1g/src/rtc/mode0/intenset.rs | 207 + pac/atsamda1g/src/rtc/mode0/intflag.rs | 207 + pac/atsamda1g/src/rtc/mode0/readreq.rs | 197 + pac/atsamda1g/src/rtc/mode0/status.rs | 113 + pac/atsamda1g/src/rtc/mode1.rs | 48 + pac/atsamda1g/src/rtc/mode1/comp.rs | 104 + pac/atsamda1g/src/rtc/mode1/count.rs | 103 + pac/atsamda1g/src/rtc/mode1/ctrl.rs | 462 + pac/atsamda1g/src/rtc/mode1/dbgctrl.rs | 113 + pac/atsamda1g/src/rtc/mode1/evctrl.rs | 583 + pac/atsamda1g/src/rtc/mode1/freqcorr.rs | 150 + pac/atsamda1g/src/rtc/mode1/intenclr.rs | 254 + pac/atsamda1g/src/rtc/mode1/intenset.rs | 254 + pac/atsamda1g/src/rtc/mode1/intflag.rs | 254 + pac/atsamda1g/src/rtc/mode1/per.rs | 103 + pac/atsamda1g/src/rtc/mode1/readreq.rs | 197 + pac/atsamda1g/src/rtc/mode1/status.rs | 113 + pac/atsamda1g/src/rtc/mode2.rs | 48 + pac/atsamda1g/src/rtc/mode2/alarm.rs | 337 + pac/atsamda1g/src/rtc/mode2/clock.rs | 337 + pac/atsamda1g/src/rtc/mode2/ctrl.rs | 556 + pac/atsamda1g/src/rtc/mode2/dbgctrl.rs | 113 + pac/atsamda1g/src/rtc/mode2/evctrl.rs | 536 + pac/atsamda1g/src/rtc/mode2/freqcorr.rs | 150 + pac/atsamda1g/src/rtc/mode2/intenclr.rs | 207 + pac/atsamda1g/src/rtc/mode2/intenset.rs | 207 + pac/atsamda1g/src/rtc/mode2/intflag.rs | 207 + pac/atsamda1g/src/rtc/mode2/mask.rs | 217 + pac/atsamda1g/src/rtc/mode2/readreq.rs | 197 + pac/atsamda1g/src/rtc/mode2/status.rs | 113 + pac/atsamda1g/src/sbmatrix.rs | 25 + pac/atsamda1g/src/sbmatrix/prs.rs | 8 + pac/atsamda1g/src/sbmatrix/prs/pras.rs | 64 + pac/atsamda1g/src/sbmatrix/prs/prbs.rs | 64 + pac/atsamda1g/src/sbmatrix/sfr.rs | 104 + pac/atsamda1g/src/sercom0.rs | 325 + pac/atsamda1g/src/sercom0/i2cm.rs | 44 + pac/atsamda1g/src/sercom0/i2cm/addr.rs | 281 + pac/atsamda1g/src/sercom0/i2cm/baud.rs | 214 + pac/atsamda1g/src/sercom0/i2cm/ctrla.rs | 903 + pac/atsamda1g/src/sercom0/i2cm/ctrlb.rs | 244 + pac/atsamda1g/src/sercom0/i2cm/data.rs | 103 + pac/atsamda1g/src/sercom0/i2cm/dbgctrl.rs | 113 + pac/atsamda1g/src/sercom0/i2cm/intenclr.rs | 207 + pac/atsamda1g/src/sercom0/i2cm/intenset.rs | 207 + pac/atsamda1g/src/sercom0/i2cm/intflag.rs | 207 + pac/atsamda1g/src/sercom0/i2cm/status.rs | 479 + pac/atsamda1g/src/sercom0/i2cm/syncbusy.rs | 93 + pac/atsamda1g/src/sercom0/i2cs.rs | 36 + pac/atsamda1g/src/sercom0/i2cs/addr.rs | 234 + pac/atsamda1g/src/sercom0/i2cs/ctrla.rs | 744 + pac/atsamda1g/src/sercom0/i2cs/ctrlb.rs | 328 + pac/atsamda1g/src/sercom0/i2cs/data.rs | 103 + pac/atsamda1g/src/sercom0/i2cs/intenclr.rs | 254 + pac/atsamda1g/src/sercom0/i2cs/intenset.rs | 254 + pac/atsamda1g/src/sercom0/i2cs/intflag.rs | 254 + pac/atsamda1g/src/sercom0/i2cs/status.rs | 489 + pac/atsamda1g/src/sercom0/i2cs/syncbusy.rs | 73 + pac/atsamda1g/src/sercom0/spim.rs | 44 + pac/atsamda1g/src/sercom0/spim/addr.rs | 140 + pac/atsamda1g/src/sercom0/spim/baud.rs | 103 + pac/atsamda1g/src/sercom0/spim/ctrla.rs | 992 + pac/atsamda1g/src/sercom0/spim/ctrlb.rs | 439 + pac/atsamda1g/src/sercom0/spim/data.rs | 103 + pac/atsamda1g/src/sercom0/spim/dbgctrl.rs | 113 + pac/atsamda1g/src/sercom0/spim/intenclr.rs | 301 + pac/atsamda1g/src/sercom0/spim/intenset.rs | 301 + pac/atsamda1g/src/sercom0/spim/intflag.rs | 301 + pac/atsamda1g/src/sercom0/spim/status.rs | 113 + pac/atsamda1g/src/sercom0/spim/syncbusy.rs | 93 + pac/atsamda1g/src/sercom0/spis.rs | 44 + pac/atsamda1g/src/sercom0/spis/addr.rs | 140 + pac/atsamda1g/src/sercom0/spis/baud.rs | 103 + pac/atsamda1g/src/sercom0/spis/ctrla.rs | 992 + pac/atsamda1g/src/sercom0/spis/ctrlb.rs | 439 + pac/atsamda1g/src/sercom0/spis/data.rs | 103 + pac/atsamda1g/src/sercom0/spis/dbgctrl.rs | 113 + pac/atsamda1g/src/sercom0/spis/intenclr.rs | 301 + pac/atsamda1g/src/sercom0/spis/intenset.rs | 301 + pac/atsamda1g/src/sercom0/spis/intflag.rs | 301 + pac/atsamda1g/src/sercom0/spis/status.rs | 113 + pac/atsamda1g/src/sercom0/spis/syncbusy.rs | 93 + pac/atsamda1g/src/sercom0/usart_ext.rs | 56 + pac/atsamda1g/src/sercom0/usart_ext/baud.rs | 103 + .../src/sercom0/usart_ext/baud_frac_mode.rs | 140 + .../src/sercom0/usart_ext/baud_fracfp_mode.rs | 140 + .../sercom0/usart_ext/baud_usartfp_mode.rs | 103 + pac/atsamda1g/src/sercom0/usart_ext/ctrla.rs | 1256 + pac/atsamda1g/src/sercom0/usart_ext/ctrlb.rs | 614 + pac/atsamda1g/src/sercom0/usart_ext/data.rs | 103 + .../src/sercom0/usart_ext/dbgctrl.rs | 113 + .../src/sercom0/usart_ext/intenclr.rs | 395 + .../src/sercom0/usart_ext/intenset.rs | 395 + .../src/sercom0/usart_ext/intflag.rs | 395 + pac/atsamda1g/src/sercom0/usart_ext/rxpl.rs | 103 + pac/atsamda1g/src/sercom0/usart_ext/status.rs | 395 + .../src/sercom0/usart_ext/syncbusy.rs | 93 + pac/atsamda1g/src/sercom0/usart_int.rs | 56 + pac/atsamda1g/src/sercom0/usart_int/baud.rs | 103 + .../src/sercom0/usart_int/baud_frac_mode.rs | 140 + .../src/sercom0/usart_int/baud_fracfp_mode.rs | 140 + .../sercom0/usart_int/baud_usartfp_mode.rs | 103 + pac/atsamda1g/src/sercom0/usart_int/ctrla.rs | 1256 + pac/atsamda1g/src/sercom0/usart_int/ctrlb.rs | 614 + pac/atsamda1g/src/sercom0/usart_int/data.rs | 103 + .../src/sercom0/usart_int/dbgctrl.rs | 113 + .../src/sercom0/usart_int/intenclr.rs | 395 + .../src/sercom0/usart_int/intenset.rs | 395 + .../src/sercom0/usart_int/intflag.rs | 395 + pac/atsamda1g/src/sercom0/usart_int/rxpl.rs | 103 + pac/atsamda1g/src/sercom0/usart_int/status.rs | 395 + .../src/sercom0/usart_int/syncbusy.rs | 93 + pac/atsamda1g/src/sys_tick.rs | 28 + pac/atsamda1g/src/sys_tick/calib.rs | 157 + pac/atsamda1g/src/sys_tick/csr.rs | 395 + pac/atsamda1g/src/sys_tick/cvr.rs | 103 + pac/atsamda1g/src/sys_tick/rvr.rs | 103 + pac/atsamda1g/src/sysctrl.rs | 132 + pac/atsamda1g/src/sysctrl/bod33.rs | 705 + pac/atsamda1g/src/sysctrl/dfllctrl.rs | 583 + pac/atsamda1g/src/sysctrl/dfllmul.rs | 177 + pac/atsamda1g/src/sysctrl/dfllsync.rs | 113 + pac/atsamda1g/src/sysctrl/dfllval.rs | 177 + pac/atsamda1g/src/sysctrl/dpllctrla.rs | 207 + pac/atsamda1g/src/sysctrl/dpllctrlb.rs | 580 + pac/atsamda1g/src/sysctrl/dpllratio.rs | 140 + pac/atsamda1g/src/sysctrl/dpllstatus.rs | 113 + pac/atsamda1g/src/sysctrl/intenclr.rs | 771 + pac/atsamda1g/src/sysctrl/intenset.rs | 771 + pac/atsamda1g/src/sysctrl/intflag.rs | 771 + pac/atsamda1g/src/sysctrl/osc32k.rs | 549 + pac/atsamda1g/src/sysctrl/osc8m.rs | 468 + pac/atsamda1g/src/sysctrl/osculp32k.rs | 150 + pac/atsamda1g/src/sysctrl/pclksr.rs | 333 + pac/atsamda1g/src/sysctrl/vref.rs | 197 + pac/atsamda1g/src/sysctrl/vreg.rs | 160 + pac/atsamda1g/src/sysctrl/xosc.rs | 694 + pac/atsamda1g/src/sysctrl/xosc32k.rs | 606 + pac/atsamda1g/src/system_control.rs | 67 + pac/atsamda1g/src/system_control/aircr.rs | 338 + pac/atsamda1g/src/system_control/ccr.rs | 137 + pac/atsamda1g/src/system_control/cpuid.rs | 133 + pac/atsamda1g/src/system_control/dfsr.rs | 301 + pac/atsamda1g/src/system_control/icsr.rs | 704 + pac/atsamda1g/src/system_control/scr.rs | 348 + pac/atsamda1g/src/system_control/shcsr.rs | 113 + pac/atsamda1g/src/system_control/shpr2.rs | 103 + pac/atsamda1g/src/system_control/shpr3.rs | 140 + pac/atsamda1g/src/system_control/vtor.rs | 103 + pac/atsamda1g/src/tc3.rs | 133 + pac/atsamda1g/src/tc3/count16.rs | 52 + pac/atsamda1g/src/tc3/count16/cc.rs | 104 + pac/atsamda1g/src/tc3/count16/count.rs | 103 + pac/atsamda1g/src/tc3/count16/ctrla.rs | 681 + pac/atsamda1g/src/tc3/count16/ctrlbclr.rs | 259 + pac/atsamda1g/src/tc3/count16/ctrlbset.rs | 259 + pac/atsamda1g/src/tc3/count16/ctrlc.rs | 254 + pac/atsamda1g/src/tc3/count16/dbgctrl.rs | 113 + pac/atsamda1g/src/tc3/count16/evctrl.rs | 439 + pac/atsamda1g/src/tc3/count16/intenclr.rs | 301 + pac/atsamda1g/src/tc3/count16/intenset.rs | 301 + pac/atsamda1g/src/tc3/count16/intflag.rs | 301 + pac/atsamda1g/src/tc3/count16/readreq.rs | 197 + pac/atsamda1g/src/tc3/count16/status.rs | 93 + pac/atsamda1g/src/tc3/count32.rs | 52 + pac/atsamda1g/src/tc3/count32/cc.rs | 104 + pac/atsamda1g/src/tc3/count32/count.rs | 103 + pac/atsamda1g/src/tc3/count32/ctrla.rs | 681 + pac/atsamda1g/src/tc3/count32/ctrlbclr.rs | 259 + pac/atsamda1g/src/tc3/count32/ctrlbset.rs | 259 + pac/atsamda1g/src/tc3/count32/ctrlc.rs | 254 + pac/atsamda1g/src/tc3/count32/dbgctrl.rs | 113 + pac/atsamda1g/src/tc3/count32/evctrl.rs | 439 + pac/atsamda1g/src/tc3/count32/intenclr.rs | 301 + pac/atsamda1g/src/tc3/count32/intenset.rs | 301 + pac/atsamda1g/src/tc3/count32/intflag.rs | 301 + pac/atsamda1g/src/tc3/count32/readreq.rs | 197 + pac/atsamda1g/src/tc3/count32/status.rs | 93 + pac/atsamda1g/src/tc3/count8.rs | 56 + pac/atsamda1g/src/tc3/count8/cc.rs | 104 + pac/atsamda1g/src/tc3/count8/count.rs | 103 + pac/atsamda1g/src/tc3/count8/ctrla.rs | 681 + pac/atsamda1g/src/tc3/count8/ctrlbclr.rs | 259 + pac/atsamda1g/src/tc3/count8/ctrlbset.rs | 259 + pac/atsamda1g/src/tc3/count8/ctrlc.rs | 254 + pac/atsamda1g/src/tc3/count8/dbgctrl.rs | 113 + pac/atsamda1g/src/tc3/count8/evctrl.rs | 439 + pac/atsamda1g/src/tc3/count8/intenclr.rs | 301 + pac/atsamda1g/src/tc3/count8/intenset.rs | 301 + pac/atsamda1g/src/tc3/count8/intflag.rs | 301 + pac/atsamda1g/src/tc3/count8/per.rs | 103 + pac/atsamda1g/src/tc3/count8/readreq.rs | 197 + pac/atsamda1g/src/tc3/count8/status.rs | 93 + pac/atsamda1g/src/tcc0.rs | 365 + pac/atsamda1g/src/tcc0/cc.rs | 104 + pac/atsamda1g/src/tcc0/cc_dith4_mode.rs | 141 + pac/atsamda1g/src/tcc0/cc_dith5_mode.rs | 141 + pac/atsamda1g/src/tcc0/cc_dith6_mode.rs | 141 + pac/atsamda1g/src/tcc0/ccb.rs | 104 + pac/atsamda1g/src/tcc0/ccb_dith4_mode.rs | 141 + pac/atsamda1g/src/tcc0/ccb_dith5_mode.rs | 141 + pac/atsamda1g/src/tcc0/ccb_dith6_mode.rs | 141 + pac/atsamda1g/src/tcc0/count.rs | 103 + pac/atsamda1g/src/tcc0/count_dith4_mode.rs | 103 + pac/atsamda1g/src/tcc0/count_dith5_mode.rs | 103 + pac/atsamda1g/src/tcc0/count_dith6_mode.rs | 103 + pac/atsamda1g/src/tcc0/ctrla.rs | 817 + pac/atsamda1g/src/tcc0/ctrlbclr.rs | 444 + pac/atsamda1g/src/tcc0/ctrlbset.rs | 444 + pac/atsamda1g/src/tcc0/dbgctrl.rs | 160 + pac/atsamda1g/src/tcc0/drvctrl.rs | 1268 + pac/atsamda1g/src/tcc0/evctrl.rs | 1198 + pac/atsamda1g/src/tcc0/fctrla.rs | 880 + pac/atsamda1g/src/tcc0/fctrlb.rs | 880 + pac/atsamda1g/src/tcc0/intenclr.rs | 677 + pac/atsamda1g/src/tcc0/intenset.rs | 677 + pac/atsamda1g/src/tcc0/intflag.rs | 677 + pac/atsamda1g/src/tcc0/patt.rs | 818 + pac/atsamda1g/src/tcc0/pattb.rs | 818 + pac/atsamda1g/src/tcc0/per.rs | 103 + pac/atsamda1g/src/tcc0/per_dith4_mode.rs | 140 + pac/atsamda1g/src/tcc0/per_dith5_mode.rs | 140 + pac/atsamda1g/src/tcc0/per_dith6_mode.rs | 140 + pac/atsamda1g/src/tcc0/perb.rs | 103 + pac/atsamda1g/src/tcc0/perb_dith4_mode.rs | 140 + pac/atsamda1g/src/tcc0/perb_dith5_mode.rs | 140 + pac/atsamda1g/src/tcc0/perb_dith6_mode.rs | 140 + pac/atsamda1g/src/tcc0/status.rs | 1147 + pac/atsamda1g/src/tcc0/syncbusy.rs | 413 + pac/atsamda1g/src/tcc0/wave.rs | 927 + pac/atsamda1g/src/tcc0/waveb.rs | 927 + pac/atsamda1g/src/tcc0/wexctrl.rs | 365 + pac/atsamda1g/src/usb.rs | 155 + pac/atsamda1g/src/usb/device.rs | 78 + pac/atsamda1g/src/usb/device/ctrla.rs | 301 + pac/atsamda1g/src/usb/device/ctrlb.rs | 666 + pac/atsamda1g/src/usb/device/dadd.rs | 150 + pac/atsamda1g/src/usb/device/descadd.rs | 103 + .../src/usb/device/device_endpoint.rs | 28 + .../src/usb/device/device_endpoint/epcfg.rs | 187 + .../usb/device/device_endpoint/epintenclr.rs | 395 + .../usb/device/device_endpoint/epintenset.rs | 395 + .../usb/device/device_endpoint/epintflag.rs | 395 + .../usb/device/device_endpoint/epstatus.rs | 173 + .../usb/device/device_endpoint/epstatusclr.rs | 234 + .../usb/device/device_endpoint/epstatusset.rs | 234 + pac/atsamda1g/src/usb/device/epintsmry.rs | 193 + pac/atsamda1g/src/usb/device/fnum.rs | 93 + pac/atsamda1g/src/usb/device/fsmstatus.rs | 127 + pac/atsamda1g/src/usb/device/intenclr.rs | 536 + pac/atsamda1g/src/usb/device/intenset.rs | 536 + pac/atsamda1g/src/usb/device/intflag.rs | 536 + pac/atsamda1g/src/usb/device/padcal.rs | 177 + pac/atsamda1g/src/usb/device/qosctrl.rs | 290 + pac/atsamda1g/src/usb/device/status.rs | 157 + pac/atsamda1g/src/usb/device/syncbusy.rs | 73 + pac/atsamda1g/src/usb/host.rs | 84 + pac/atsamda1g/src/usb/host/ctrla.rs | 301 + pac/atsamda1g/src/usb/host/ctrlb.rs | 481 + pac/atsamda1g/src/usb/host/descadd.rs | 103 + pac/atsamda1g/src/usb/host/flenhigh.rs | 53 + pac/atsamda1g/src/usb/host/fnum.rs | 140 + pac/atsamda1g/src/usb/host/fsmstatus.rs | 127 + pac/atsamda1g/src/usb/host/host_pipe.rs | 32 + .../src/usb/host/host_pipe/binterval.rs | 103 + pac/atsamda1g/src/usb/host/host_pipe/pcfg.rs | 187 + .../src/usb/host/host_pipe/pintenclr.rs | 348 + .../src/usb/host/host_pipe/pintenset.rs | 348 + .../src/usb/host/host_pipe/pintflag.rs | 348 + .../src/usb/host/host_pipe/pstatus.rs | 133 + .../src/usb/host/host_pipe/pstatusclr.rs | 180 + .../src/usb/host/host_pipe/pstatusset.rs | 180 + pac/atsamda1g/src/usb/host/hsofc.rs | 150 + pac/atsamda1g/src/usb/host/intenclr.rs | 442 + pac/atsamda1g/src/usb/host/intenset.rs | 442 + pac/atsamda1g/src/usb/host/intflag.rs | 442 + pac/atsamda1g/src/usb/host/padcal.rs | 177 + pac/atsamda1g/src/usb/host/pintsmry.rs | 193 + pac/atsamda1g/src/usb/host/qosctrl.rs | 290 + pac/atsamda1g/src/usb/host/status.rs | 140 + pac/atsamda1g/src/usb/host/syncbusy.rs | 73 + pac/atsamda1g/src/wdt.rs | 53 + pac/atsamda1g/src/wdt/clear.rs | 85 + pac/atsamda1g/src/wdt/config.rs | 498 + pac/atsamda1g/src/wdt/ctrl.rs | 207 + pac/atsamda1g/src/wdt/ewctrl.rs | 282 + pac/atsamda1g/src/wdt/intenclr.rs | 113 + pac/atsamda1g/src/wdt/intenset.rs | 113 + pac/atsamda1g/src/wdt/intflag.rs | 113 + pac/atsamda1g/src/wdt/status.rs | 53 + pac/atsamda1j/Cargo.toml | 22 + pac/atsamda1j/README.md | 26 + pac/atsamda1j/build.rs | 16 + pac/atsamda1j/device.x | 29 + pac/atsamda1j/src/ac.rs | 80 + pac/atsamda1j/src/ac/compctrl.rs | 927 + pac/atsamda1j/src/ac/ctrla.rs | 254 + pac/atsamda1j/src/ac/ctrlb.rs | 99 + pac/atsamda1j/src/ac/evctrl.rs | 301 + pac/atsamda1j/src/ac/intenclr.rs | 207 + pac/atsamda1j/src/ac/intenset.rs | 207 + pac/atsamda1j/src/ac/intflag.rs | 207 + pac/atsamda1j/src/ac/scaler.rs | 104 + pac/atsamda1j/src/ac/statusa.rs | 135 + pac/atsamda1j/src/ac/statusb.rs | 93 + pac/atsamda1j/src/ac/statusc.rs | 135 + pac/atsamda1j/src/ac/winctrl.rs | 225 + pac/atsamda1j/src/adc.rs | 130 + pac/atsamda1j/src/adc/avgctrl.rs | 306 + pac/atsamda1j/src/adc/calib.rs | 140 + pac/atsamda1j/src/adc/ctrla.rs | 207 + pac/atsamda1j/src/adc/ctrlb.rs | 530 + pac/atsamda1j/src/adc/dbgctrl.rs | 113 + pac/atsamda1j/src/adc/evctrl.rs | 254 + pac/atsamda1j/src/adc/gaincorr.rs | 103 + pac/atsamda1j/src/adc/inputctrl.rs | 853 + pac/atsamda1j/src/adc/intenclr.rs | 254 + pac/atsamda1j/src/adc/intenset.rs | 254 + pac/atsamda1j/src/adc/intflag.rs | 254 + pac/atsamda1j/src/adc/offsetcorr.rs | 103 + pac/atsamda1j/src/adc/refctrl.rs | 238 + pac/atsamda1j/src/adc/result.rs | 53 + pac/atsamda1j/src/adc/sampctrl.rs | 103 + pac/atsamda1j/src/adc/status.rs | 53 + pac/atsamda1j/src/adc/swtrig.rs | 160 + pac/atsamda1j/src/adc/winctrl.rs | 191 + pac/atsamda1j/src/adc/winlt.rs | 103 + pac/atsamda1j/src/adc/winut.rs | 103 + pac/atsamda1j/src/dac.rs | 60 + pac/atsamda1j/src/dac/ctrla.rs | 207 + pac/atsamda1j/src/dac/ctrlb.rs | 400 + pac/atsamda1j/src/dac/data.rs | 103 + pac/atsamda1j/src/dac/databuf.rs | 103 + pac/atsamda1j/src/dac/evctrl.rs | 160 + pac/atsamda1j/src/dac/intenclr.rs | 207 + pac/atsamda1j/src/dac/intenset.rs | 207 + pac/atsamda1j/src/dac/intflag.rs | 207 + pac/atsamda1j/src/dac/status.rs | 53 + pac/atsamda1j/src/dmac.rs | 148 + pac/atsamda1j/src/dmac/active.rs | 173 + pac/atsamda1j/src/dmac/baseaddr.rs | 103 + pac/atsamda1j/src/dmac/busych.rs | 273 + pac/atsamda1j/src/dmac/chctrla.rs | 160 + pac/atsamda1j/src/dmac/chctrlb.rs | 1331 + pac/atsamda1j/src/dmac/chid.rs | 103 + pac/atsamda1j/src/dmac/chintenclr.rs | 207 + pac/atsamda1j/src/dmac/chintenset.rs | 207 + pac/atsamda1j/src/dmac/chintflag.rs | 207 + pac/atsamda1j/src/dmac/chstatus.rs | 93 + pac/atsamda1j/src/dmac/crcchksum.rs | 103 + pac/atsamda1j/src/dmac/crcctrl.rs | 337 + pac/atsamda1j/src/dmac/crcdatain.rs | 103 + pac/atsamda1j/src/dmac/crcstatus.rs | 160 + pac/atsamda1j/src/dmac/ctrl.rs | 395 + pac/atsamda1j/src/dmac/dbgctrl.rs | 113 + pac/atsamda1j/src/dmac/intpend.rs | 385 + pac/atsamda1j/src/dmac/intstatus.rs | 273 + pac/atsamda1j/src/dmac/pendch.rs | 273 + pac/atsamda1j/src/dmac/prictrl0.rs | 402 + pac/atsamda1j/src/dmac/qosctrl.rs | 402 + pac/atsamda1j/src/dmac/swtrigctrl.rs | 630 + pac/atsamda1j/src/dmac/wrbaddr.rs | 103 + pac/atsamda1j/src/dsu.rs | 134 + pac/atsamda1j/src/dsu/addr.rs | 103 + pac/atsamda1j/src/dsu/cid0.rs | 53 + pac/atsamda1j/src/dsu/cid1.rs | 73 + pac/atsamda1j/src/dsu/cid2.rs | 53 + pac/atsamda1j/src/dsu/cid3.rs | 53 + pac/atsamda1j/src/dsu/ctrl.rs | 153 + pac/atsamda1j/src/dsu/data.rs | 103 + pac/atsamda1j/src/dsu/dcc.rs | 104 + pac/atsamda1j/src/dsu/did.rs | 153 + pac/atsamda1j/src/dsu/end.rs | 53 + pac/atsamda1j/src/dsu/entry0.rs | 93 + pac/atsamda1j/src/dsu/entry1.rs | 31 + pac/atsamda1j/src/dsu/length.rs | 103 + pac/atsamda1j/src/dsu/memtype.rs | 53 + pac/atsamda1j/src/dsu/pid0.rs | 53 + pac/atsamda1j/src/dsu/pid1.rs | 73 + pac/atsamda1j/src/dsu/pid2.rs | 93 + pac/atsamda1j/src/dsu/pid3.rs | 73 + pac/atsamda1j/src/dsu/pid4.rs | 73 + pac/atsamda1j/src/dsu/statusa.rs | 301 + pac/atsamda1j/src/dsu/statusb.rs | 133 + pac/atsamda1j/src/eic.rs | 64 + pac/atsamda1j/src/eic/config.rs | 1547 ++ pac/atsamda1j/src/eic/ctrl.rs | 160 + pac/atsamda1j/src/eic/evctrl.rs | 818 + pac/atsamda1j/src/eic/intenclr.rs | 818 + pac/atsamda1j/src/eic/intenset.rs | 818 + pac/atsamda1j/src/eic/intflag.rs | 818 + pac/atsamda1j/src/eic/nmictrl.rs | 251 + pac/atsamda1j/src/eic/nmiflag.rs | 113 + pac/atsamda1j/src/eic/status.rs | 53 + pac/atsamda1j/src/eic/wakeup.rs | 818 + pac/atsamda1j/src/evsys.rs | 48 + pac/atsamda1j/src/evsys/channel.rs | 398 + pac/atsamda1j/src/evsys/chstatus.rs | 513 + pac/atsamda1j/src/evsys/ctrl.rs | 99 + pac/atsamda1j/src/evsys/intenclr.rs | 1194 + pac/atsamda1j/src/evsys/intenset.rs | 1194 + pac/atsamda1j/src/evsys/intflag.rs | 1194 + pac/atsamda1j/src/evsys/user.rs | 176 + pac/atsamda1j/src/gclk.rs | 34 + pac/atsamda1j/src/gclk/clkctrl.rs | 865 + pac/atsamda1j/src/gclk/ctrl.rs | 113 + pac/atsamda1j/src/gclk/genctrl.rs | 609 + pac/atsamda1j/src/gclk/gendiv.rs | 140 + pac/atsamda1j/src/gclk/status.rs | 53 + pac/atsamda1j/src/generic.rs | 260 + pac/atsamda1j/src/i2s.rs | 58 + pac/atsamda1j/src/i2s/clkctrl.rs | 1013 + pac/atsamda1j/src/i2s/ctrla.rs | 348 + pac/atsamda1j/src/i2s/data.rs | 104 + pac/atsamda1j/src/i2s/intenclr.rs | 442 + pac/atsamda1j/src/i2s/intenset.rs | 442 + pac/atsamda1j/src/i2s/intflag.rs | 442 + pac/atsamda1j/src/i2s/serctrl.rs | 1622 ++ pac/atsamda1j/src/i2s/syncbusy.rs | 193 + pac/atsamda1j/src/lib.rs | 1452 + pac/atsamda1j/src/mtb.rs | 158 + pac/atsamda1j/src/mtb/authstatus.rs | 31 + pac/atsamda1j/src/mtb/base.rs | 31 + pac/atsamda1j/src/mtb/cid0.rs | 31 + pac/atsamda1j/src/mtb/cid1.rs | 31 + pac/atsamda1j/src/mtb/cid2.rs | 31 + pac/atsamda1j/src/mtb/cid3.rs | 31 + pac/atsamda1j/src/mtb/claimclr.rs | 64 + pac/atsamda1j/src/mtb/claimset.rs | 64 + pac/atsamda1j/src/mtb/devarch.rs | 31 + pac/atsamda1j/src/mtb/devid.rs | 31 + pac/atsamda1j/src/mtb/devtype.rs | 31 + pac/atsamda1j/src/mtb/flow.rs | 197 + pac/atsamda1j/src/mtb/itctrl.rs | 64 + pac/atsamda1j/src/mtb/lockaccess.rs | 64 + pac/atsamda1j/src/mtb/lockstatus.rs | 31 + pac/atsamda1j/src/mtb/master.rs | 385 + pac/atsamda1j/src/mtb/pid0.rs | 31 + pac/atsamda1j/src/mtb/pid1.rs | 31 + pac/atsamda1j/src/mtb/pid2.rs | 31 + pac/atsamda1j/src/mtb/pid3.rs | 31 + pac/atsamda1j/src/mtb/pid4.rs | 31 + pac/atsamda1j/src/mtb/pid5.rs | 31 + pac/atsamda1j/src/mtb/pid6.rs | 31 + pac/atsamda1j/src/mtb/pid7.rs | 31 + pac/atsamda1j/src/mtb/position.rs | 150 + pac/atsamda1j/src/nvmctrl.rs | 63 + pac/atsamda1j/src/nvmctrl/addr.rs | 103 + pac/atsamda1j/src/nvmctrl/ctrla.rs | 394 + pac/atsamda1j/src/nvmctrl/ctrlb.rs | 457 + pac/atsamda1j/src/nvmctrl/intenclr.rs | 160 + pac/atsamda1j/src/nvmctrl/intenset.rs | 160 + pac/atsamda1j/src/nvmctrl/intflag.rs | 160 + pac/atsamda1j/src/nvmctrl/lock.rs | 103 + pac/atsamda1j/src/nvmctrl/param.rs | 304 + pac/atsamda1j/src/nvmctrl/status.rs | 348 + pac/atsamda1j/src/pac0.rs | 16 + pac/atsamda1j/src/pac0/wpclr.rs | 103 + pac/atsamda1j/src/pac0/wpset.rs | 103 + pac/atsamda1j/src/pm.rs | 98 + pac/atsamda1j/src/pm/ahbmask.rs | 395 + pac/atsamda1j/src/pm/apbamask.rs | 395 + pac/atsamda1j/src/pm/apbasel.rs | 230 + pac/atsamda1j/src/pm/apbbmask.rs | 395 + pac/atsamda1j/src/pm/apbbsel.rs | 230 + pac/atsamda1j/src/pm/apbcmask.rs | 1053 + pac/atsamda1j/src/pm/apbcsel.rs | 230 + pac/atsamda1j/src/pm/cpusel.rs | 230 + pac/atsamda1j/src/pm/ctrl.rs | 64 + pac/atsamda1j/src/pm/extctrl.rs | 113 + pac/atsamda1j/src/pm/intenclr.rs | 113 + pac/atsamda1j/src/pm/intenset.rs | 113 + pac/atsamda1j/src/pm/intflag.rs | 113 + pac/atsamda1j/src/pm/rcause.rs | 153 + pac/atsamda1j/src/pm/sleep.rs | 165 + pac/atsamda1j/src/port.rs | 43 + pac/atsamda1j/src/port/group.rs | 52 + pac/atsamda1j/src/port/group/ctrl.rs | 103 + pac/atsamda1j/src/port/group/dir.rs | 103 + pac/atsamda1j/src/port/group/dirclr.rs | 103 + pac/atsamda1j/src/port/group/dirset.rs | 103 + pac/atsamda1j/src/port/group/dirtgl.rs | 103 + pac/atsamda1j/src/port/group/in_.rs | 53 + pac/atsamda1j/src/port/group/out.rs | 103 + pac/atsamda1j/src/port/group/outclr.rs | 103 + pac/atsamda1j/src/port/group/outset.rs | 103 + pac/atsamda1j/src/port/group/outtgl.rs | 103 + pac/atsamda1j/src/port/group/pincfg.rs | 255 + pac/atsamda1j/src/port/group/pmux.rs | 395 + pac/atsamda1j/src/port/group/wrconfig.rs | 268 + pac/atsamda1j/src/rtc.rs | 123 + pac/atsamda1j/src/rtc/mode0.rs | 44 + pac/atsamda1j/src/rtc/mode0/comp.rs | 103 + pac/atsamda1j/src/rtc/mode0/count.rs | 103 + pac/atsamda1j/src/rtc/mode0/ctrl.rs | 509 + pac/atsamda1j/src/rtc/mode0/dbgctrl.rs | 113 + pac/atsamda1j/src/rtc/mode0/evctrl.rs | 536 + pac/atsamda1j/src/rtc/mode0/freqcorr.rs | 150 + pac/atsamda1j/src/rtc/mode0/intenclr.rs | 207 + pac/atsamda1j/src/rtc/mode0/intenset.rs | 207 + pac/atsamda1j/src/rtc/mode0/intflag.rs | 207 + pac/atsamda1j/src/rtc/mode0/readreq.rs | 197 + pac/atsamda1j/src/rtc/mode0/status.rs | 113 + pac/atsamda1j/src/rtc/mode1.rs | 48 + pac/atsamda1j/src/rtc/mode1/comp.rs | 104 + pac/atsamda1j/src/rtc/mode1/count.rs | 103 + pac/atsamda1j/src/rtc/mode1/ctrl.rs | 462 + pac/atsamda1j/src/rtc/mode1/dbgctrl.rs | 113 + pac/atsamda1j/src/rtc/mode1/evctrl.rs | 583 + pac/atsamda1j/src/rtc/mode1/freqcorr.rs | 150 + pac/atsamda1j/src/rtc/mode1/intenclr.rs | 254 + pac/atsamda1j/src/rtc/mode1/intenset.rs | 254 + pac/atsamda1j/src/rtc/mode1/intflag.rs | 254 + pac/atsamda1j/src/rtc/mode1/per.rs | 103 + pac/atsamda1j/src/rtc/mode1/readreq.rs | 197 + pac/atsamda1j/src/rtc/mode1/status.rs | 113 + pac/atsamda1j/src/rtc/mode2.rs | 48 + pac/atsamda1j/src/rtc/mode2/alarm.rs | 337 + pac/atsamda1j/src/rtc/mode2/clock.rs | 337 + pac/atsamda1j/src/rtc/mode2/ctrl.rs | 556 + pac/atsamda1j/src/rtc/mode2/dbgctrl.rs | 113 + pac/atsamda1j/src/rtc/mode2/evctrl.rs | 536 + pac/atsamda1j/src/rtc/mode2/freqcorr.rs | 150 + pac/atsamda1j/src/rtc/mode2/intenclr.rs | 207 + pac/atsamda1j/src/rtc/mode2/intenset.rs | 207 + pac/atsamda1j/src/rtc/mode2/intflag.rs | 207 + pac/atsamda1j/src/rtc/mode2/mask.rs | 217 + pac/atsamda1j/src/rtc/mode2/readreq.rs | 197 + pac/atsamda1j/src/rtc/mode2/status.rs | 113 + pac/atsamda1j/src/sbmatrix.rs | 25 + pac/atsamda1j/src/sbmatrix/prs.rs | 8 + pac/atsamda1j/src/sbmatrix/prs/pras.rs | 64 + pac/atsamda1j/src/sbmatrix/prs/prbs.rs | 64 + pac/atsamda1j/src/sbmatrix/sfr.rs | 104 + pac/atsamda1j/src/sercom0.rs | 325 + pac/atsamda1j/src/sercom0/i2cm.rs | 44 + pac/atsamda1j/src/sercom0/i2cm/addr.rs | 281 + pac/atsamda1j/src/sercom0/i2cm/baud.rs | 214 + pac/atsamda1j/src/sercom0/i2cm/ctrla.rs | 903 + pac/atsamda1j/src/sercom0/i2cm/ctrlb.rs | 244 + pac/atsamda1j/src/sercom0/i2cm/data.rs | 103 + pac/atsamda1j/src/sercom0/i2cm/dbgctrl.rs | 113 + pac/atsamda1j/src/sercom0/i2cm/intenclr.rs | 207 + pac/atsamda1j/src/sercom0/i2cm/intenset.rs | 207 + pac/atsamda1j/src/sercom0/i2cm/intflag.rs | 207 + pac/atsamda1j/src/sercom0/i2cm/status.rs | 479 + pac/atsamda1j/src/sercom0/i2cm/syncbusy.rs | 93 + pac/atsamda1j/src/sercom0/i2cs.rs | 36 + pac/atsamda1j/src/sercom0/i2cs/addr.rs | 234 + pac/atsamda1j/src/sercom0/i2cs/ctrla.rs | 744 + pac/atsamda1j/src/sercom0/i2cs/ctrlb.rs | 328 + pac/atsamda1j/src/sercom0/i2cs/data.rs | 103 + pac/atsamda1j/src/sercom0/i2cs/intenclr.rs | 254 + pac/atsamda1j/src/sercom0/i2cs/intenset.rs | 254 + pac/atsamda1j/src/sercom0/i2cs/intflag.rs | 254 + pac/atsamda1j/src/sercom0/i2cs/status.rs | 489 + pac/atsamda1j/src/sercom0/i2cs/syncbusy.rs | 73 + pac/atsamda1j/src/sercom0/spim.rs | 44 + pac/atsamda1j/src/sercom0/spim/addr.rs | 140 + pac/atsamda1j/src/sercom0/spim/baud.rs | 103 + pac/atsamda1j/src/sercom0/spim/ctrla.rs | 992 + pac/atsamda1j/src/sercom0/spim/ctrlb.rs | 439 + pac/atsamda1j/src/sercom0/spim/data.rs | 103 + pac/atsamda1j/src/sercom0/spim/dbgctrl.rs | 113 + pac/atsamda1j/src/sercom0/spim/intenclr.rs | 301 + pac/atsamda1j/src/sercom0/spim/intenset.rs | 301 + pac/atsamda1j/src/sercom0/spim/intflag.rs | 301 + pac/atsamda1j/src/sercom0/spim/status.rs | 113 + pac/atsamda1j/src/sercom0/spim/syncbusy.rs | 93 + pac/atsamda1j/src/sercom0/spis.rs | 44 + pac/atsamda1j/src/sercom0/spis/addr.rs | 140 + pac/atsamda1j/src/sercom0/spis/baud.rs | 103 + pac/atsamda1j/src/sercom0/spis/ctrla.rs | 992 + pac/atsamda1j/src/sercom0/spis/ctrlb.rs | 439 + pac/atsamda1j/src/sercom0/spis/data.rs | 103 + pac/atsamda1j/src/sercom0/spis/dbgctrl.rs | 113 + pac/atsamda1j/src/sercom0/spis/intenclr.rs | 301 + pac/atsamda1j/src/sercom0/spis/intenset.rs | 301 + pac/atsamda1j/src/sercom0/spis/intflag.rs | 301 + pac/atsamda1j/src/sercom0/spis/status.rs | 113 + pac/atsamda1j/src/sercom0/spis/syncbusy.rs | 93 + pac/atsamda1j/src/sercom0/usart_ext.rs | 56 + pac/atsamda1j/src/sercom0/usart_ext/baud.rs | 103 + .../src/sercom0/usart_ext/baud_frac_mode.rs | 140 + .../src/sercom0/usart_ext/baud_fracfp_mode.rs | 140 + .../sercom0/usart_ext/baud_usartfp_mode.rs | 103 + pac/atsamda1j/src/sercom0/usart_ext/ctrla.rs | 1256 + pac/atsamda1j/src/sercom0/usart_ext/ctrlb.rs | 614 + pac/atsamda1j/src/sercom0/usart_ext/data.rs | 103 + .../src/sercom0/usart_ext/dbgctrl.rs | 113 + .../src/sercom0/usart_ext/intenclr.rs | 395 + .../src/sercom0/usart_ext/intenset.rs | 395 + .../src/sercom0/usart_ext/intflag.rs | 395 + pac/atsamda1j/src/sercom0/usart_ext/rxpl.rs | 103 + pac/atsamda1j/src/sercom0/usart_ext/status.rs | 395 + .../src/sercom0/usart_ext/syncbusy.rs | 93 + pac/atsamda1j/src/sercom0/usart_int.rs | 56 + pac/atsamda1j/src/sercom0/usart_int/baud.rs | 103 + .../src/sercom0/usart_int/baud_frac_mode.rs | 140 + .../src/sercom0/usart_int/baud_fracfp_mode.rs | 140 + .../sercom0/usart_int/baud_usartfp_mode.rs | 103 + pac/atsamda1j/src/sercom0/usart_int/ctrla.rs | 1256 + pac/atsamda1j/src/sercom0/usart_int/ctrlb.rs | 614 + pac/atsamda1j/src/sercom0/usart_int/data.rs | 103 + .../src/sercom0/usart_int/dbgctrl.rs | 113 + .../src/sercom0/usart_int/intenclr.rs | 395 + .../src/sercom0/usart_int/intenset.rs | 395 + .../src/sercom0/usart_int/intflag.rs | 395 + pac/atsamda1j/src/sercom0/usart_int/rxpl.rs | 103 + pac/atsamda1j/src/sercom0/usart_int/status.rs | 395 + .../src/sercom0/usart_int/syncbusy.rs | 93 + pac/atsamda1j/src/sys_tick.rs | 28 + pac/atsamda1j/src/sys_tick/calib.rs | 157 + pac/atsamda1j/src/sys_tick/csr.rs | 395 + pac/atsamda1j/src/sys_tick/cvr.rs | 103 + pac/atsamda1j/src/sys_tick/rvr.rs | 103 + pac/atsamda1j/src/sysctrl.rs | 132 + pac/atsamda1j/src/sysctrl/bod33.rs | 705 + pac/atsamda1j/src/sysctrl/dfllctrl.rs | 583 + pac/atsamda1j/src/sysctrl/dfllmul.rs | 177 + pac/atsamda1j/src/sysctrl/dfllsync.rs | 113 + pac/atsamda1j/src/sysctrl/dfllval.rs | 177 + pac/atsamda1j/src/sysctrl/dpllctrla.rs | 207 + pac/atsamda1j/src/sysctrl/dpllctrlb.rs | 580 + pac/atsamda1j/src/sysctrl/dpllratio.rs | 140 + pac/atsamda1j/src/sysctrl/dpllstatus.rs | 113 + pac/atsamda1j/src/sysctrl/intenclr.rs | 771 + pac/atsamda1j/src/sysctrl/intenset.rs | 771 + pac/atsamda1j/src/sysctrl/intflag.rs | 771 + pac/atsamda1j/src/sysctrl/osc32k.rs | 549 + pac/atsamda1j/src/sysctrl/osc8m.rs | 468 + pac/atsamda1j/src/sysctrl/osculp32k.rs | 150 + pac/atsamda1j/src/sysctrl/pclksr.rs | 333 + pac/atsamda1j/src/sysctrl/vref.rs | 197 + pac/atsamda1j/src/sysctrl/vreg.rs | 160 + pac/atsamda1j/src/sysctrl/xosc.rs | 694 + pac/atsamda1j/src/sysctrl/xosc32k.rs | 606 + pac/atsamda1j/src/system_control.rs | 67 + pac/atsamda1j/src/system_control/aircr.rs | 338 + pac/atsamda1j/src/system_control/ccr.rs | 137 + pac/atsamda1j/src/system_control/cpuid.rs | 133 + pac/atsamda1j/src/system_control/dfsr.rs | 301 + pac/atsamda1j/src/system_control/icsr.rs | 704 + pac/atsamda1j/src/system_control/scr.rs | 348 + pac/atsamda1j/src/system_control/shcsr.rs | 113 + pac/atsamda1j/src/system_control/shpr2.rs | 103 + pac/atsamda1j/src/system_control/shpr3.rs | 140 + pac/atsamda1j/src/system_control/vtor.rs | 103 + pac/atsamda1j/src/tc3.rs | 133 + pac/atsamda1j/src/tc3/count16.rs | 52 + pac/atsamda1j/src/tc3/count16/cc.rs | 104 + pac/atsamda1j/src/tc3/count16/count.rs | 103 + pac/atsamda1j/src/tc3/count16/ctrla.rs | 681 + pac/atsamda1j/src/tc3/count16/ctrlbclr.rs | 259 + pac/atsamda1j/src/tc3/count16/ctrlbset.rs | 259 + pac/atsamda1j/src/tc3/count16/ctrlc.rs | 254 + pac/atsamda1j/src/tc3/count16/dbgctrl.rs | 113 + pac/atsamda1j/src/tc3/count16/evctrl.rs | 439 + pac/atsamda1j/src/tc3/count16/intenclr.rs | 301 + pac/atsamda1j/src/tc3/count16/intenset.rs | 301 + pac/atsamda1j/src/tc3/count16/intflag.rs | 301 + pac/atsamda1j/src/tc3/count16/readreq.rs | 197 + pac/atsamda1j/src/tc3/count16/status.rs | 93 + pac/atsamda1j/src/tc3/count32.rs | 52 + pac/atsamda1j/src/tc3/count32/cc.rs | 104 + pac/atsamda1j/src/tc3/count32/count.rs | 103 + pac/atsamda1j/src/tc3/count32/ctrla.rs | 681 + pac/atsamda1j/src/tc3/count32/ctrlbclr.rs | 259 + pac/atsamda1j/src/tc3/count32/ctrlbset.rs | 259 + pac/atsamda1j/src/tc3/count32/ctrlc.rs | 254 + pac/atsamda1j/src/tc3/count32/dbgctrl.rs | 113 + pac/atsamda1j/src/tc3/count32/evctrl.rs | 439 + pac/atsamda1j/src/tc3/count32/intenclr.rs | 301 + pac/atsamda1j/src/tc3/count32/intenset.rs | 301 + pac/atsamda1j/src/tc3/count32/intflag.rs | 301 + pac/atsamda1j/src/tc3/count32/readreq.rs | 197 + pac/atsamda1j/src/tc3/count32/status.rs | 93 + pac/atsamda1j/src/tc3/count8.rs | 56 + pac/atsamda1j/src/tc3/count8/cc.rs | 104 + pac/atsamda1j/src/tc3/count8/count.rs | 103 + pac/atsamda1j/src/tc3/count8/ctrla.rs | 681 + pac/atsamda1j/src/tc3/count8/ctrlbclr.rs | 259 + pac/atsamda1j/src/tc3/count8/ctrlbset.rs | 259 + pac/atsamda1j/src/tc3/count8/ctrlc.rs | 254 + pac/atsamda1j/src/tc3/count8/dbgctrl.rs | 113 + pac/atsamda1j/src/tc3/count8/evctrl.rs | 439 + pac/atsamda1j/src/tc3/count8/intenclr.rs | 301 + pac/atsamda1j/src/tc3/count8/intenset.rs | 301 + pac/atsamda1j/src/tc3/count8/intflag.rs | 301 + pac/atsamda1j/src/tc3/count8/per.rs | 103 + pac/atsamda1j/src/tc3/count8/readreq.rs | 197 + pac/atsamda1j/src/tc3/count8/status.rs | 93 + pac/atsamda1j/src/tcc0.rs | 365 + pac/atsamda1j/src/tcc0/cc.rs | 104 + pac/atsamda1j/src/tcc0/cc_dith4_mode.rs | 141 + pac/atsamda1j/src/tcc0/cc_dith5_mode.rs | 141 + pac/atsamda1j/src/tcc0/cc_dith6_mode.rs | 141 + pac/atsamda1j/src/tcc0/ccb.rs | 104 + pac/atsamda1j/src/tcc0/ccb_dith4_mode.rs | 141 + pac/atsamda1j/src/tcc0/ccb_dith5_mode.rs | 141 + pac/atsamda1j/src/tcc0/ccb_dith6_mode.rs | 141 + pac/atsamda1j/src/tcc0/count.rs | 103 + pac/atsamda1j/src/tcc0/count_dith4_mode.rs | 103 + pac/atsamda1j/src/tcc0/count_dith5_mode.rs | 103 + pac/atsamda1j/src/tcc0/count_dith6_mode.rs | 103 + pac/atsamda1j/src/tcc0/ctrla.rs | 817 + pac/atsamda1j/src/tcc0/ctrlbclr.rs | 444 + pac/atsamda1j/src/tcc0/ctrlbset.rs | 444 + pac/atsamda1j/src/tcc0/dbgctrl.rs | 160 + pac/atsamda1j/src/tcc0/drvctrl.rs | 1268 + pac/atsamda1j/src/tcc0/evctrl.rs | 1198 + pac/atsamda1j/src/tcc0/fctrla.rs | 880 + pac/atsamda1j/src/tcc0/fctrlb.rs | 880 + pac/atsamda1j/src/tcc0/intenclr.rs | 677 + pac/atsamda1j/src/tcc0/intenset.rs | 677 + pac/atsamda1j/src/tcc0/intflag.rs | 677 + pac/atsamda1j/src/tcc0/patt.rs | 818 + pac/atsamda1j/src/tcc0/pattb.rs | 818 + pac/atsamda1j/src/tcc0/per.rs | 103 + pac/atsamda1j/src/tcc0/per_dith4_mode.rs | 140 + pac/atsamda1j/src/tcc0/per_dith5_mode.rs | 140 + pac/atsamda1j/src/tcc0/per_dith6_mode.rs | 140 + pac/atsamda1j/src/tcc0/perb.rs | 103 + pac/atsamda1j/src/tcc0/perb_dith4_mode.rs | 140 + pac/atsamda1j/src/tcc0/perb_dith5_mode.rs | 140 + pac/atsamda1j/src/tcc0/perb_dith6_mode.rs | 140 + pac/atsamda1j/src/tcc0/status.rs | 1147 + pac/atsamda1j/src/tcc0/syncbusy.rs | 413 + pac/atsamda1j/src/tcc0/wave.rs | 927 + pac/atsamda1j/src/tcc0/waveb.rs | 927 + pac/atsamda1j/src/tcc0/wexctrl.rs | 365 + pac/atsamda1j/src/usb.rs | 155 + pac/atsamda1j/src/usb/device.rs | 78 + pac/atsamda1j/src/usb/device/ctrla.rs | 301 + pac/atsamda1j/src/usb/device/ctrlb.rs | 666 + pac/atsamda1j/src/usb/device/dadd.rs | 150 + pac/atsamda1j/src/usb/device/descadd.rs | 103 + .../src/usb/device/device_endpoint.rs | 28 + .../src/usb/device/device_endpoint/epcfg.rs | 187 + .../usb/device/device_endpoint/epintenclr.rs | 395 + .../usb/device/device_endpoint/epintenset.rs | 395 + .../usb/device/device_endpoint/epintflag.rs | 395 + .../usb/device/device_endpoint/epstatus.rs | 173 + .../usb/device/device_endpoint/epstatusclr.rs | 234 + .../usb/device/device_endpoint/epstatusset.rs | 234 + pac/atsamda1j/src/usb/device/epintsmry.rs | 193 + pac/atsamda1j/src/usb/device/fnum.rs | 93 + pac/atsamda1j/src/usb/device/fsmstatus.rs | 127 + pac/atsamda1j/src/usb/device/intenclr.rs | 536 + pac/atsamda1j/src/usb/device/intenset.rs | 536 + pac/atsamda1j/src/usb/device/intflag.rs | 536 + pac/atsamda1j/src/usb/device/padcal.rs | 177 + pac/atsamda1j/src/usb/device/qosctrl.rs | 290 + pac/atsamda1j/src/usb/device/status.rs | 157 + pac/atsamda1j/src/usb/device/syncbusy.rs | 73 + pac/atsamda1j/src/usb/host.rs | 84 + pac/atsamda1j/src/usb/host/ctrla.rs | 301 + pac/atsamda1j/src/usb/host/ctrlb.rs | 481 + pac/atsamda1j/src/usb/host/descadd.rs | 103 + pac/atsamda1j/src/usb/host/flenhigh.rs | 53 + pac/atsamda1j/src/usb/host/fnum.rs | 140 + pac/atsamda1j/src/usb/host/fsmstatus.rs | 127 + pac/atsamda1j/src/usb/host/host_pipe.rs | 32 + .../src/usb/host/host_pipe/binterval.rs | 103 + pac/atsamda1j/src/usb/host/host_pipe/pcfg.rs | 187 + .../src/usb/host/host_pipe/pintenclr.rs | 348 + .../src/usb/host/host_pipe/pintenset.rs | 348 + .../src/usb/host/host_pipe/pintflag.rs | 348 + .../src/usb/host/host_pipe/pstatus.rs | 133 + .../src/usb/host/host_pipe/pstatusclr.rs | 180 + .../src/usb/host/host_pipe/pstatusset.rs | 180 + pac/atsamda1j/src/usb/host/hsofc.rs | 150 + pac/atsamda1j/src/usb/host/intenclr.rs | 442 + pac/atsamda1j/src/usb/host/intenset.rs | 442 + pac/atsamda1j/src/usb/host/intflag.rs | 442 + pac/atsamda1j/src/usb/host/padcal.rs | 177 + pac/atsamda1j/src/usb/host/pintsmry.rs | 193 + pac/atsamda1j/src/usb/host/qosctrl.rs | 290 + pac/atsamda1j/src/usb/host/status.rs | 140 + pac/atsamda1j/src/usb/host/syncbusy.rs | 73 + pac/atsamda1j/src/wdt.rs | 53 + pac/atsamda1j/src/wdt/clear.rs | 85 + pac/atsamda1j/src/wdt/config.rs | 498 + pac/atsamda1j/src/wdt/ctrl.rs | 207 + pac/atsamda1j/src/wdt/ewctrl.rs | 282 + pac/atsamda1j/src/wdt/intenclr.rs | 113 + pac/atsamda1j/src/wdt/intenset.rs | 113 + pac/atsamda1j/src/wdt/intflag.rs | 113 + pac/atsamda1j/src/wdt/status.rs | 53 + svd/ATSAMDA1E14B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1E15B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1E16B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1G14B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1G15B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1G16B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1J14B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1J15B.svd | 22165 ++++++++++++++++ svd/ATSAMDA1J16B.svd | 22165 ++++++++++++++++ svd/devices/atsamda1e14b.xsl | 5 + svd/devices/atsamda1e15b.xsl | 5 + svd/devices/atsamda1e16b.xsl | 5 + svd/devices/atsamda1g14b.xsl | 5 + svd/devices/atsamda1g15b.xsl | 5 + svd/devices/atsamda1g16b.xsl | 5 + svd/devices/atsamda1j14b.xsl | 5 + svd/devices/atsamda1j15b.xsl | 5 + svd/devices/atsamda1j16b.xsl | 5 + svd/devices/include/atsamda1.xsl | 256 + 1559 files changed, 588500 insertions(+), 245 deletions(-) create mode 100644 pac/atsamda1e/Cargo.toml create mode 100644 pac/atsamda1e/README.md create mode 100644 pac/atsamda1e/build.rs create mode 100644 pac/atsamda1e/device.x create mode 100644 pac/atsamda1e/src/ac.rs create mode 100644 pac/atsamda1e/src/ac/compctrl.rs create mode 100644 pac/atsamda1e/src/ac/ctrla.rs create mode 100644 pac/atsamda1e/src/ac/ctrlb.rs create mode 100644 pac/atsamda1e/src/ac/evctrl.rs create mode 100644 pac/atsamda1e/src/ac/intenclr.rs create mode 100644 pac/atsamda1e/src/ac/intenset.rs create mode 100644 pac/atsamda1e/src/ac/intflag.rs create mode 100644 pac/atsamda1e/src/ac/scaler.rs create mode 100644 pac/atsamda1e/src/ac/statusa.rs create mode 100644 pac/atsamda1e/src/ac/statusb.rs create mode 100644 pac/atsamda1e/src/ac/statusc.rs create mode 100644 pac/atsamda1e/src/ac/winctrl.rs create mode 100644 pac/atsamda1e/src/adc.rs create mode 100644 pac/atsamda1e/src/adc/avgctrl.rs create mode 100644 pac/atsamda1e/src/adc/calib.rs create mode 100644 pac/atsamda1e/src/adc/ctrla.rs create mode 100644 pac/atsamda1e/src/adc/ctrlb.rs create mode 100644 pac/atsamda1e/src/adc/dbgctrl.rs create mode 100644 pac/atsamda1e/src/adc/evctrl.rs create mode 100644 pac/atsamda1e/src/adc/gaincorr.rs create mode 100644 pac/atsamda1e/src/adc/inputctrl.rs create mode 100644 pac/atsamda1e/src/adc/intenclr.rs create mode 100644 pac/atsamda1e/src/adc/intenset.rs create mode 100644 pac/atsamda1e/src/adc/intflag.rs create mode 100644 pac/atsamda1e/src/adc/offsetcorr.rs create mode 100644 pac/atsamda1e/src/adc/refctrl.rs create mode 100644 pac/atsamda1e/src/adc/result.rs create mode 100644 pac/atsamda1e/src/adc/sampctrl.rs create mode 100644 pac/atsamda1e/src/adc/status.rs create mode 100644 pac/atsamda1e/src/adc/swtrig.rs create mode 100644 pac/atsamda1e/src/adc/winctrl.rs create mode 100644 pac/atsamda1e/src/adc/winlt.rs create mode 100644 pac/atsamda1e/src/adc/winut.rs create mode 100644 pac/atsamda1e/src/dac.rs create mode 100644 pac/atsamda1e/src/dac/ctrla.rs create mode 100644 pac/atsamda1e/src/dac/ctrlb.rs create mode 100644 pac/atsamda1e/src/dac/data.rs create mode 100644 pac/atsamda1e/src/dac/databuf.rs create mode 100644 pac/atsamda1e/src/dac/evctrl.rs create mode 100644 pac/atsamda1e/src/dac/intenclr.rs create mode 100644 pac/atsamda1e/src/dac/intenset.rs create mode 100644 pac/atsamda1e/src/dac/intflag.rs create mode 100644 pac/atsamda1e/src/dac/status.rs create mode 100644 pac/atsamda1e/src/dmac.rs create mode 100644 pac/atsamda1e/src/dmac/active.rs create mode 100644 pac/atsamda1e/src/dmac/baseaddr.rs create mode 100644 pac/atsamda1e/src/dmac/busych.rs create mode 100644 pac/atsamda1e/src/dmac/chctrla.rs create mode 100644 pac/atsamda1e/src/dmac/chctrlb.rs create mode 100644 pac/atsamda1e/src/dmac/chid.rs create mode 100644 pac/atsamda1e/src/dmac/chintenclr.rs create mode 100644 pac/atsamda1e/src/dmac/chintenset.rs create mode 100644 pac/atsamda1e/src/dmac/chintflag.rs create mode 100644 pac/atsamda1e/src/dmac/chstatus.rs create mode 100644 pac/atsamda1e/src/dmac/crcchksum.rs create mode 100644 pac/atsamda1e/src/dmac/crcctrl.rs create mode 100644 pac/atsamda1e/src/dmac/crcdatain.rs create mode 100644 pac/atsamda1e/src/dmac/crcstatus.rs create mode 100644 pac/atsamda1e/src/dmac/ctrl.rs create mode 100644 pac/atsamda1e/src/dmac/dbgctrl.rs create mode 100644 pac/atsamda1e/src/dmac/intpend.rs create mode 100644 pac/atsamda1e/src/dmac/intstatus.rs create mode 100644 pac/atsamda1e/src/dmac/pendch.rs create mode 100644 pac/atsamda1e/src/dmac/prictrl0.rs create mode 100644 pac/atsamda1e/src/dmac/qosctrl.rs create mode 100644 pac/atsamda1e/src/dmac/swtrigctrl.rs create mode 100644 pac/atsamda1e/src/dmac/wrbaddr.rs create mode 100644 pac/atsamda1e/src/dsu.rs create mode 100644 pac/atsamda1e/src/dsu/addr.rs create mode 100644 pac/atsamda1e/src/dsu/cid0.rs create mode 100644 pac/atsamda1e/src/dsu/cid1.rs create mode 100644 pac/atsamda1e/src/dsu/cid2.rs create mode 100644 pac/atsamda1e/src/dsu/cid3.rs create mode 100644 pac/atsamda1e/src/dsu/ctrl.rs create mode 100644 pac/atsamda1e/src/dsu/data.rs create mode 100644 pac/atsamda1e/src/dsu/dcc.rs create mode 100644 pac/atsamda1e/src/dsu/did.rs create mode 100644 pac/atsamda1e/src/dsu/end.rs create mode 100644 pac/atsamda1e/src/dsu/entry0.rs create mode 100644 pac/atsamda1e/src/dsu/entry1.rs create mode 100644 pac/atsamda1e/src/dsu/length.rs create mode 100644 pac/atsamda1e/src/dsu/memtype.rs create mode 100644 pac/atsamda1e/src/dsu/pid0.rs create mode 100644 pac/atsamda1e/src/dsu/pid1.rs create mode 100644 pac/atsamda1e/src/dsu/pid2.rs create mode 100644 pac/atsamda1e/src/dsu/pid3.rs create mode 100644 pac/atsamda1e/src/dsu/pid4.rs create mode 100644 pac/atsamda1e/src/dsu/statusa.rs create mode 100644 pac/atsamda1e/src/dsu/statusb.rs create mode 100644 pac/atsamda1e/src/eic.rs create mode 100644 pac/atsamda1e/src/eic/config.rs create mode 100644 pac/atsamda1e/src/eic/ctrl.rs create mode 100644 pac/atsamda1e/src/eic/evctrl.rs create mode 100644 pac/atsamda1e/src/eic/intenclr.rs create mode 100644 pac/atsamda1e/src/eic/intenset.rs create mode 100644 pac/atsamda1e/src/eic/intflag.rs create mode 100644 pac/atsamda1e/src/eic/nmictrl.rs create mode 100644 pac/atsamda1e/src/eic/nmiflag.rs create mode 100644 pac/atsamda1e/src/eic/status.rs create mode 100644 pac/atsamda1e/src/eic/wakeup.rs create mode 100644 pac/atsamda1e/src/evsys.rs create mode 100644 pac/atsamda1e/src/evsys/channel.rs create mode 100644 pac/atsamda1e/src/evsys/chstatus.rs create mode 100644 pac/atsamda1e/src/evsys/ctrl.rs create mode 100644 pac/atsamda1e/src/evsys/intenclr.rs create mode 100644 pac/atsamda1e/src/evsys/intenset.rs create mode 100644 pac/atsamda1e/src/evsys/intflag.rs create mode 100644 pac/atsamda1e/src/evsys/user.rs create mode 100644 pac/atsamda1e/src/gclk.rs create mode 100644 pac/atsamda1e/src/gclk/clkctrl.rs create mode 100644 pac/atsamda1e/src/gclk/ctrl.rs create mode 100644 pac/atsamda1e/src/gclk/genctrl.rs create mode 100644 pac/atsamda1e/src/gclk/gendiv.rs create mode 100644 pac/atsamda1e/src/gclk/status.rs create mode 100644 pac/atsamda1e/src/generic.rs create mode 100644 pac/atsamda1e/src/i2s.rs create mode 100644 pac/atsamda1e/src/i2s/clkctrl.rs create mode 100644 pac/atsamda1e/src/i2s/ctrla.rs create mode 100644 pac/atsamda1e/src/i2s/data.rs create mode 100644 pac/atsamda1e/src/i2s/intenclr.rs create mode 100644 pac/atsamda1e/src/i2s/intenset.rs create mode 100644 pac/atsamda1e/src/i2s/intflag.rs create mode 100644 pac/atsamda1e/src/i2s/serctrl.rs create mode 100644 pac/atsamda1e/src/i2s/syncbusy.rs create mode 100644 pac/atsamda1e/src/lib.rs create mode 100644 pac/atsamda1e/src/mtb.rs create mode 100644 pac/atsamda1e/src/mtb/authstatus.rs create mode 100644 pac/atsamda1e/src/mtb/base.rs create mode 100644 pac/atsamda1e/src/mtb/cid0.rs create mode 100644 pac/atsamda1e/src/mtb/cid1.rs create mode 100644 pac/atsamda1e/src/mtb/cid2.rs create mode 100644 pac/atsamda1e/src/mtb/cid3.rs create mode 100644 pac/atsamda1e/src/mtb/claimclr.rs create mode 100644 pac/atsamda1e/src/mtb/claimset.rs create mode 100644 pac/atsamda1e/src/mtb/devarch.rs create mode 100644 pac/atsamda1e/src/mtb/devid.rs create mode 100644 pac/atsamda1e/src/mtb/devtype.rs create mode 100644 pac/atsamda1e/src/mtb/flow.rs create mode 100644 pac/atsamda1e/src/mtb/itctrl.rs create mode 100644 pac/atsamda1e/src/mtb/lockaccess.rs create mode 100644 pac/atsamda1e/src/mtb/lockstatus.rs create mode 100644 pac/atsamda1e/src/mtb/master.rs create mode 100644 pac/atsamda1e/src/mtb/pid0.rs create mode 100644 pac/atsamda1e/src/mtb/pid1.rs create mode 100644 pac/atsamda1e/src/mtb/pid2.rs create mode 100644 pac/atsamda1e/src/mtb/pid3.rs create mode 100644 pac/atsamda1e/src/mtb/pid4.rs create mode 100644 pac/atsamda1e/src/mtb/pid5.rs create mode 100644 pac/atsamda1e/src/mtb/pid6.rs create mode 100644 pac/atsamda1e/src/mtb/pid7.rs create mode 100644 pac/atsamda1e/src/mtb/position.rs create mode 100644 pac/atsamda1e/src/nvmctrl.rs create mode 100644 pac/atsamda1e/src/nvmctrl/addr.rs create mode 100644 pac/atsamda1e/src/nvmctrl/ctrla.rs create mode 100644 pac/atsamda1e/src/nvmctrl/ctrlb.rs create mode 100644 pac/atsamda1e/src/nvmctrl/intenclr.rs create mode 100644 pac/atsamda1e/src/nvmctrl/intenset.rs create mode 100644 pac/atsamda1e/src/nvmctrl/intflag.rs create mode 100644 pac/atsamda1e/src/nvmctrl/lock.rs create mode 100644 pac/atsamda1e/src/nvmctrl/param.rs create mode 100644 pac/atsamda1e/src/nvmctrl/status.rs create mode 100644 pac/atsamda1e/src/pac0.rs create mode 100644 pac/atsamda1e/src/pac0/wpclr.rs create mode 100644 pac/atsamda1e/src/pac0/wpset.rs create mode 100644 pac/atsamda1e/src/pm.rs create mode 100644 pac/atsamda1e/src/pm/ahbmask.rs create mode 100644 pac/atsamda1e/src/pm/apbamask.rs create mode 100644 pac/atsamda1e/src/pm/apbasel.rs create mode 100644 pac/atsamda1e/src/pm/apbbmask.rs create mode 100644 pac/atsamda1e/src/pm/apbbsel.rs create mode 100644 pac/atsamda1e/src/pm/apbcmask.rs create mode 100644 pac/atsamda1e/src/pm/apbcsel.rs create mode 100644 pac/atsamda1e/src/pm/cpusel.rs create mode 100644 pac/atsamda1e/src/pm/ctrl.rs create mode 100644 pac/atsamda1e/src/pm/extctrl.rs create mode 100644 pac/atsamda1e/src/pm/intenclr.rs create mode 100644 pac/atsamda1e/src/pm/intenset.rs create mode 100644 pac/atsamda1e/src/pm/intflag.rs create mode 100644 pac/atsamda1e/src/pm/rcause.rs create mode 100644 pac/atsamda1e/src/pm/sleep.rs create mode 100644 pac/atsamda1e/src/port.rs create mode 100644 pac/atsamda1e/src/port/group.rs create mode 100644 pac/atsamda1e/src/port/group/ctrl.rs create mode 100644 pac/atsamda1e/src/port/group/dir.rs create mode 100644 pac/atsamda1e/src/port/group/dirclr.rs create mode 100644 pac/atsamda1e/src/port/group/dirset.rs create mode 100644 pac/atsamda1e/src/port/group/dirtgl.rs create mode 100644 pac/atsamda1e/src/port/group/in_.rs create mode 100644 pac/atsamda1e/src/port/group/out.rs create mode 100644 pac/atsamda1e/src/port/group/outclr.rs create mode 100644 pac/atsamda1e/src/port/group/outset.rs create mode 100644 pac/atsamda1e/src/port/group/outtgl.rs create mode 100644 pac/atsamda1e/src/port/group/pincfg.rs create mode 100644 pac/atsamda1e/src/port/group/pmux.rs create mode 100644 pac/atsamda1e/src/port/group/wrconfig.rs create mode 100644 pac/atsamda1e/src/rtc.rs create mode 100644 pac/atsamda1e/src/rtc/mode0.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/comp.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/count.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/ctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/dbgctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/evctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/freqcorr.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/intenclr.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/intenset.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/intflag.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/readreq.rs create mode 100644 pac/atsamda1e/src/rtc/mode0/status.rs create mode 100644 pac/atsamda1e/src/rtc/mode1.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/comp.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/count.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/ctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/dbgctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/evctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/freqcorr.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/intenclr.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/intenset.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/intflag.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/per.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/readreq.rs create mode 100644 pac/atsamda1e/src/rtc/mode1/status.rs create mode 100644 pac/atsamda1e/src/rtc/mode2.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/alarm.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/clock.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/ctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/dbgctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/evctrl.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/freqcorr.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/intenclr.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/intenset.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/intflag.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/mask.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/readreq.rs create mode 100644 pac/atsamda1e/src/rtc/mode2/status.rs create mode 100644 pac/atsamda1e/src/sbmatrix.rs create mode 100644 pac/atsamda1e/src/sbmatrix/prs.rs create mode 100644 pac/atsamda1e/src/sbmatrix/prs/pras.rs create mode 100644 pac/atsamda1e/src/sbmatrix/prs/prbs.rs create mode 100644 pac/atsamda1e/src/sbmatrix/sfr.rs create mode 100644 pac/atsamda1e/src/sercom0.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/addr.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/baud.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/ctrla.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/ctrlb.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/data.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/dbgctrl.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/intenclr.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/intenset.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/intflag.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/status.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cm/syncbusy.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/addr.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/ctrla.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/ctrlb.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/data.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/intenclr.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/intenset.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/intflag.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/status.rs create mode 100644 pac/atsamda1e/src/sercom0/i2cs/syncbusy.rs create mode 100644 pac/atsamda1e/src/sercom0/spim.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/addr.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/baud.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/ctrla.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/ctrlb.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/data.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/dbgctrl.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/intenclr.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/intenset.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/intflag.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/status.rs create mode 100644 pac/atsamda1e/src/sercom0/spim/syncbusy.rs create mode 100644 pac/atsamda1e/src/sercom0/spis.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/addr.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/baud.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/ctrla.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/ctrlb.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/data.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/dbgctrl.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/intenclr.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/intenset.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/intflag.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/status.rs create mode 100644 pac/atsamda1e/src/sercom0/spis/syncbusy.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/baud.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/baud_frac_mode.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/baud_fracfp_mode.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/baud_usartfp_mode.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/ctrla.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/ctrlb.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/data.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/dbgctrl.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/intenclr.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/intenset.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/intflag.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/rxpl.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/status.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_ext/syncbusy.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/baud.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/baud_frac_mode.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/baud_fracfp_mode.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/baud_usartfp_mode.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/ctrla.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/ctrlb.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/data.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/dbgctrl.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/intenclr.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/intenset.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/intflag.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/rxpl.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/status.rs create mode 100644 pac/atsamda1e/src/sercom0/usart_int/syncbusy.rs create mode 100644 pac/atsamda1e/src/sys_tick.rs create mode 100644 pac/atsamda1e/src/sys_tick/calib.rs create mode 100644 pac/atsamda1e/src/sys_tick/csr.rs create mode 100644 pac/atsamda1e/src/sys_tick/cvr.rs create mode 100644 pac/atsamda1e/src/sys_tick/rvr.rs create mode 100644 pac/atsamda1e/src/sysctrl.rs create mode 100644 pac/atsamda1e/src/sysctrl/bod33.rs create mode 100644 pac/atsamda1e/src/sysctrl/dfllctrl.rs create mode 100644 pac/atsamda1e/src/sysctrl/dfllmul.rs create mode 100644 pac/atsamda1e/src/sysctrl/dfllsync.rs create mode 100644 pac/atsamda1e/src/sysctrl/dfllval.rs create mode 100644 pac/atsamda1e/src/sysctrl/dpllctrla.rs create mode 100644 pac/atsamda1e/src/sysctrl/dpllctrlb.rs create mode 100644 pac/atsamda1e/src/sysctrl/dpllratio.rs create mode 100644 pac/atsamda1e/src/sysctrl/dpllstatus.rs create mode 100644 pac/atsamda1e/src/sysctrl/intenclr.rs create mode 100644 pac/atsamda1e/src/sysctrl/intenset.rs create mode 100644 pac/atsamda1e/src/sysctrl/intflag.rs create mode 100644 pac/atsamda1e/src/sysctrl/osc32k.rs create mode 100644 pac/atsamda1e/src/sysctrl/osc8m.rs create mode 100644 pac/atsamda1e/src/sysctrl/osculp32k.rs create mode 100644 pac/atsamda1e/src/sysctrl/pclksr.rs create mode 100644 pac/atsamda1e/src/sysctrl/vref.rs create mode 100644 pac/atsamda1e/src/sysctrl/vreg.rs create mode 100644 pac/atsamda1e/src/sysctrl/xosc.rs create mode 100644 pac/atsamda1e/src/sysctrl/xosc32k.rs create mode 100644 pac/atsamda1e/src/system_control.rs create mode 100644 pac/atsamda1e/src/system_control/aircr.rs create mode 100644 pac/atsamda1e/src/system_control/ccr.rs create mode 100644 pac/atsamda1e/src/system_control/cpuid.rs create mode 100644 pac/atsamda1e/src/system_control/dfsr.rs create mode 100644 pac/atsamda1e/src/system_control/icsr.rs create mode 100644 pac/atsamda1e/src/system_control/scr.rs create mode 100644 pac/atsamda1e/src/system_control/shcsr.rs create mode 100644 pac/atsamda1e/src/system_control/shpr2.rs create mode 100644 pac/atsamda1e/src/system_control/shpr3.rs create mode 100644 pac/atsamda1e/src/system_control/vtor.rs create mode 100644 pac/atsamda1e/src/tc3.rs create mode 100644 pac/atsamda1e/src/tc3/count16.rs create mode 100644 pac/atsamda1e/src/tc3/count16/cc.rs create mode 100644 pac/atsamda1e/src/tc3/count16/count.rs create mode 100644 pac/atsamda1e/src/tc3/count16/ctrla.rs create mode 100644 pac/atsamda1e/src/tc3/count16/ctrlbclr.rs create mode 100644 pac/atsamda1e/src/tc3/count16/ctrlbset.rs create mode 100644 pac/atsamda1e/src/tc3/count16/ctrlc.rs create mode 100644 pac/atsamda1e/src/tc3/count16/dbgctrl.rs create mode 100644 pac/atsamda1e/src/tc3/count16/evctrl.rs create mode 100644 pac/atsamda1e/src/tc3/count16/intenclr.rs create mode 100644 pac/atsamda1e/src/tc3/count16/intenset.rs create mode 100644 pac/atsamda1e/src/tc3/count16/intflag.rs create mode 100644 pac/atsamda1e/src/tc3/count16/readreq.rs create mode 100644 pac/atsamda1e/src/tc3/count16/status.rs create mode 100644 pac/atsamda1e/src/tc3/count32.rs create mode 100644 pac/atsamda1e/src/tc3/count32/cc.rs create mode 100644 pac/atsamda1e/src/tc3/count32/count.rs create mode 100644 pac/atsamda1e/src/tc3/count32/ctrla.rs create mode 100644 pac/atsamda1e/src/tc3/count32/ctrlbclr.rs create mode 100644 pac/atsamda1e/src/tc3/count32/ctrlbset.rs create mode 100644 pac/atsamda1e/src/tc3/count32/ctrlc.rs create mode 100644 pac/atsamda1e/src/tc3/count32/dbgctrl.rs create mode 100644 pac/atsamda1e/src/tc3/count32/evctrl.rs create mode 100644 pac/atsamda1e/src/tc3/count32/intenclr.rs create mode 100644 pac/atsamda1e/src/tc3/count32/intenset.rs create mode 100644 pac/atsamda1e/src/tc3/count32/intflag.rs create mode 100644 pac/atsamda1e/src/tc3/count32/readreq.rs create mode 100644 pac/atsamda1e/src/tc3/count32/status.rs create mode 100644 pac/atsamda1e/src/tc3/count8.rs create mode 100644 pac/atsamda1e/src/tc3/count8/cc.rs create mode 100644 pac/atsamda1e/src/tc3/count8/count.rs create mode 100644 pac/atsamda1e/src/tc3/count8/ctrla.rs create mode 100644 pac/atsamda1e/src/tc3/count8/ctrlbclr.rs create mode 100644 pac/atsamda1e/src/tc3/count8/ctrlbset.rs create mode 100644 pac/atsamda1e/src/tc3/count8/ctrlc.rs create mode 100644 pac/atsamda1e/src/tc3/count8/dbgctrl.rs create mode 100644 pac/atsamda1e/src/tc3/count8/evctrl.rs create mode 100644 pac/atsamda1e/src/tc3/count8/intenclr.rs create mode 100644 pac/atsamda1e/src/tc3/count8/intenset.rs create mode 100644 pac/atsamda1e/src/tc3/count8/intflag.rs create mode 100644 pac/atsamda1e/src/tc3/count8/per.rs create mode 100644 pac/atsamda1e/src/tc3/count8/readreq.rs create mode 100644 pac/atsamda1e/src/tc3/count8/status.rs create mode 100644 pac/atsamda1e/src/tcc0.rs create mode 100644 pac/atsamda1e/src/tcc0/cc.rs create mode 100644 pac/atsamda1e/src/tcc0/cc_dith4_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/cc_dith5_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/cc_dith6_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/ccb.rs create mode 100644 pac/atsamda1e/src/tcc0/ccb_dith4_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/ccb_dith5_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/ccb_dith6_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/count.rs create mode 100644 pac/atsamda1e/src/tcc0/count_dith4_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/count_dith5_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/count_dith6_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/ctrla.rs create mode 100644 pac/atsamda1e/src/tcc0/ctrlbclr.rs create mode 100644 pac/atsamda1e/src/tcc0/ctrlbset.rs create mode 100644 pac/atsamda1e/src/tcc0/dbgctrl.rs create mode 100644 pac/atsamda1e/src/tcc0/drvctrl.rs create mode 100644 pac/atsamda1e/src/tcc0/evctrl.rs create mode 100644 pac/atsamda1e/src/tcc0/fctrla.rs create mode 100644 pac/atsamda1e/src/tcc0/fctrlb.rs create mode 100644 pac/atsamda1e/src/tcc0/intenclr.rs create mode 100644 pac/atsamda1e/src/tcc0/intenset.rs create mode 100644 pac/atsamda1e/src/tcc0/intflag.rs create mode 100644 pac/atsamda1e/src/tcc0/patt.rs create mode 100644 pac/atsamda1e/src/tcc0/pattb.rs create mode 100644 pac/atsamda1e/src/tcc0/per.rs create mode 100644 pac/atsamda1e/src/tcc0/per_dith4_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/per_dith5_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/per_dith6_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/perb.rs create mode 100644 pac/atsamda1e/src/tcc0/perb_dith4_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/perb_dith5_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/perb_dith6_mode.rs create mode 100644 pac/atsamda1e/src/tcc0/status.rs create mode 100644 pac/atsamda1e/src/tcc0/syncbusy.rs create mode 100644 pac/atsamda1e/src/tcc0/wave.rs create mode 100644 pac/atsamda1e/src/tcc0/waveb.rs create mode 100644 pac/atsamda1e/src/tcc0/wexctrl.rs create mode 100644 pac/atsamda1e/src/usb.rs create mode 100644 pac/atsamda1e/src/usb/device.rs create mode 100644 pac/atsamda1e/src/usb/device/ctrla.rs create mode 100644 pac/atsamda1e/src/usb/device/ctrlb.rs create mode 100644 pac/atsamda1e/src/usb/device/dadd.rs create mode 100644 pac/atsamda1e/src/usb/device/descadd.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint/epcfg.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint/epintenclr.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint/epintenset.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint/epintflag.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint/epstatus.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint/epstatusclr.rs create mode 100644 pac/atsamda1e/src/usb/device/device_endpoint/epstatusset.rs create mode 100644 pac/atsamda1e/src/usb/device/epintsmry.rs create mode 100644 pac/atsamda1e/src/usb/device/fnum.rs create mode 100644 pac/atsamda1e/src/usb/device/fsmstatus.rs create mode 100644 pac/atsamda1e/src/usb/device/intenclr.rs create mode 100644 pac/atsamda1e/src/usb/device/intenset.rs create mode 100644 pac/atsamda1e/src/usb/device/intflag.rs create mode 100644 pac/atsamda1e/src/usb/device/padcal.rs create mode 100644 pac/atsamda1e/src/usb/device/qosctrl.rs create mode 100644 pac/atsamda1e/src/usb/device/status.rs create mode 100644 pac/atsamda1e/src/usb/device/syncbusy.rs create mode 100644 pac/atsamda1e/src/usb/host.rs create mode 100644 pac/atsamda1e/src/usb/host/ctrla.rs create mode 100644 pac/atsamda1e/src/usb/host/ctrlb.rs create mode 100644 pac/atsamda1e/src/usb/host/descadd.rs create mode 100644 pac/atsamda1e/src/usb/host/flenhigh.rs create mode 100644 pac/atsamda1e/src/usb/host/fnum.rs create mode 100644 pac/atsamda1e/src/usb/host/fsmstatus.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/binterval.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/pcfg.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/pintenclr.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/pintenset.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/pintflag.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/pstatus.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/pstatusclr.rs create mode 100644 pac/atsamda1e/src/usb/host/host_pipe/pstatusset.rs create mode 100644 pac/atsamda1e/src/usb/host/hsofc.rs create mode 100644 pac/atsamda1e/src/usb/host/intenclr.rs create mode 100644 pac/atsamda1e/src/usb/host/intenset.rs create mode 100644 pac/atsamda1e/src/usb/host/intflag.rs create mode 100644 pac/atsamda1e/src/usb/host/padcal.rs create mode 100644 pac/atsamda1e/src/usb/host/pintsmry.rs create mode 100644 pac/atsamda1e/src/usb/host/qosctrl.rs create mode 100644 pac/atsamda1e/src/usb/host/status.rs create mode 100644 pac/atsamda1e/src/usb/host/syncbusy.rs create mode 100644 pac/atsamda1e/src/wdt.rs create mode 100644 pac/atsamda1e/src/wdt/clear.rs create mode 100644 pac/atsamda1e/src/wdt/config.rs create mode 100644 pac/atsamda1e/src/wdt/ctrl.rs create mode 100644 pac/atsamda1e/src/wdt/ewctrl.rs create mode 100644 pac/atsamda1e/src/wdt/intenclr.rs create mode 100644 pac/atsamda1e/src/wdt/intenset.rs create mode 100644 pac/atsamda1e/src/wdt/intflag.rs create mode 100644 pac/atsamda1e/src/wdt/status.rs create mode 100644 pac/atsamda1g/Cargo.toml create mode 100644 pac/atsamda1g/README.md create mode 100644 pac/atsamda1g/build.rs create mode 100644 pac/atsamda1g/device.x create mode 100644 pac/atsamda1g/src/ac.rs create mode 100644 pac/atsamda1g/src/ac/compctrl.rs create mode 100644 pac/atsamda1g/src/ac/ctrla.rs create mode 100644 pac/atsamda1g/src/ac/ctrlb.rs create mode 100644 pac/atsamda1g/src/ac/evctrl.rs create mode 100644 pac/atsamda1g/src/ac/intenclr.rs create mode 100644 pac/atsamda1g/src/ac/intenset.rs create mode 100644 pac/atsamda1g/src/ac/intflag.rs create mode 100644 pac/atsamda1g/src/ac/scaler.rs create mode 100644 pac/atsamda1g/src/ac/statusa.rs create mode 100644 pac/atsamda1g/src/ac/statusb.rs create mode 100644 pac/atsamda1g/src/ac/statusc.rs create mode 100644 pac/atsamda1g/src/ac/winctrl.rs create mode 100644 pac/atsamda1g/src/adc.rs create mode 100644 pac/atsamda1g/src/adc/avgctrl.rs create mode 100644 pac/atsamda1g/src/adc/calib.rs create mode 100644 pac/atsamda1g/src/adc/ctrla.rs create mode 100644 pac/atsamda1g/src/adc/ctrlb.rs create mode 100644 pac/atsamda1g/src/adc/dbgctrl.rs create mode 100644 pac/atsamda1g/src/adc/evctrl.rs create mode 100644 pac/atsamda1g/src/adc/gaincorr.rs create mode 100644 pac/atsamda1g/src/adc/inputctrl.rs create mode 100644 pac/atsamda1g/src/adc/intenclr.rs create mode 100644 pac/atsamda1g/src/adc/intenset.rs create mode 100644 pac/atsamda1g/src/adc/intflag.rs create mode 100644 pac/atsamda1g/src/adc/offsetcorr.rs create mode 100644 pac/atsamda1g/src/adc/refctrl.rs create mode 100644 pac/atsamda1g/src/adc/result.rs create mode 100644 pac/atsamda1g/src/adc/sampctrl.rs create mode 100644 pac/atsamda1g/src/adc/status.rs create mode 100644 pac/atsamda1g/src/adc/swtrig.rs create mode 100644 pac/atsamda1g/src/adc/winctrl.rs create mode 100644 pac/atsamda1g/src/adc/winlt.rs create mode 100644 pac/atsamda1g/src/adc/winut.rs create mode 100644 pac/atsamda1g/src/dac.rs create mode 100644 pac/atsamda1g/src/dac/ctrla.rs create mode 100644 pac/atsamda1g/src/dac/ctrlb.rs create mode 100644 pac/atsamda1g/src/dac/data.rs create mode 100644 pac/atsamda1g/src/dac/databuf.rs create mode 100644 pac/atsamda1g/src/dac/evctrl.rs create mode 100644 pac/atsamda1g/src/dac/intenclr.rs create mode 100644 pac/atsamda1g/src/dac/intenset.rs create mode 100644 pac/atsamda1g/src/dac/intflag.rs create mode 100644 pac/atsamda1g/src/dac/status.rs create mode 100644 pac/atsamda1g/src/dmac.rs create mode 100644 pac/atsamda1g/src/dmac/active.rs create mode 100644 pac/atsamda1g/src/dmac/baseaddr.rs create mode 100644 pac/atsamda1g/src/dmac/busych.rs create mode 100644 pac/atsamda1g/src/dmac/chctrla.rs create mode 100644 pac/atsamda1g/src/dmac/chctrlb.rs create mode 100644 pac/atsamda1g/src/dmac/chid.rs create mode 100644 pac/atsamda1g/src/dmac/chintenclr.rs create mode 100644 pac/atsamda1g/src/dmac/chintenset.rs create mode 100644 pac/atsamda1g/src/dmac/chintflag.rs create mode 100644 pac/atsamda1g/src/dmac/chstatus.rs create mode 100644 pac/atsamda1g/src/dmac/crcchksum.rs create mode 100644 pac/atsamda1g/src/dmac/crcctrl.rs create mode 100644 pac/atsamda1g/src/dmac/crcdatain.rs create mode 100644 pac/atsamda1g/src/dmac/crcstatus.rs create mode 100644 pac/atsamda1g/src/dmac/ctrl.rs create mode 100644 pac/atsamda1g/src/dmac/dbgctrl.rs create mode 100644 pac/atsamda1g/src/dmac/intpend.rs create mode 100644 pac/atsamda1g/src/dmac/intstatus.rs create mode 100644 pac/atsamda1g/src/dmac/pendch.rs create mode 100644 pac/atsamda1g/src/dmac/prictrl0.rs create mode 100644 pac/atsamda1g/src/dmac/qosctrl.rs create mode 100644 pac/atsamda1g/src/dmac/swtrigctrl.rs create mode 100644 pac/atsamda1g/src/dmac/wrbaddr.rs create mode 100644 pac/atsamda1g/src/dsu.rs create mode 100644 pac/atsamda1g/src/dsu/addr.rs create mode 100644 pac/atsamda1g/src/dsu/cid0.rs create mode 100644 pac/atsamda1g/src/dsu/cid1.rs create mode 100644 pac/atsamda1g/src/dsu/cid2.rs create mode 100644 pac/atsamda1g/src/dsu/cid3.rs create mode 100644 pac/atsamda1g/src/dsu/ctrl.rs create mode 100644 pac/atsamda1g/src/dsu/data.rs create mode 100644 pac/atsamda1g/src/dsu/dcc.rs create mode 100644 pac/atsamda1g/src/dsu/did.rs create mode 100644 pac/atsamda1g/src/dsu/end.rs create mode 100644 pac/atsamda1g/src/dsu/entry0.rs create mode 100644 pac/atsamda1g/src/dsu/entry1.rs create mode 100644 pac/atsamda1g/src/dsu/length.rs create mode 100644 pac/atsamda1g/src/dsu/memtype.rs create mode 100644 pac/atsamda1g/src/dsu/pid0.rs create mode 100644 pac/atsamda1g/src/dsu/pid1.rs create mode 100644 pac/atsamda1g/src/dsu/pid2.rs create mode 100644 pac/atsamda1g/src/dsu/pid3.rs create mode 100644 pac/atsamda1g/src/dsu/pid4.rs create mode 100644 pac/atsamda1g/src/dsu/statusa.rs create mode 100644 pac/atsamda1g/src/dsu/statusb.rs create mode 100644 pac/atsamda1g/src/eic.rs create mode 100644 pac/atsamda1g/src/eic/config.rs create mode 100644 pac/atsamda1g/src/eic/ctrl.rs create mode 100644 pac/atsamda1g/src/eic/evctrl.rs create mode 100644 pac/atsamda1g/src/eic/intenclr.rs create mode 100644 pac/atsamda1g/src/eic/intenset.rs create mode 100644 pac/atsamda1g/src/eic/intflag.rs create mode 100644 pac/atsamda1g/src/eic/nmictrl.rs create mode 100644 pac/atsamda1g/src/eic/nmiflag.rs create mode 100644 pac/atsamda1g/src/eic/status.rs create mode 100644 pac/atsamda1g/src/eic/wakeup.rs create mode 100644 pac/atsamda1g/src/evsys.rs create mode 100644 pac/atsamda1g/src/evsys/channel.rs create mode 100644 pac/atsamda1g/src/evsys/chstatus.rs create mode 100644 pac/atsamda1g/src/evsys/ctrl.rs create mode 100644 pac/atsamda1g/src/evsys/intenclr.rs create mode 100644 pac/atsamda1g/src/evsys/intenset.rs create mode 100644 pac/atsamda1g/src/evsys/intflag.rs create mode 100644 pac/atsamda1g/src/evsys/user.rs create mode 100644 pac/atsamda1g/src/gclk.rs create mode 100644 pac/atsamda1g/src/gclk/clkctrl.rs create mode 100644 pac/atsamda1g/src/gclk/ctrl.rs create mode 100644 pac/atsamda1g/src/gclk/genctrl.rs create mode 100644 pac/atsamda1g/src/gclk/gendiv.rs create mode 100644 pac/atsamda1g/src/gclk/status.rs create mode 100644 pac/atsamda1g/src/generic.rs create mode 100644 pac/atsamda1g/src/i2s.rs create mode 100644 pac/atsamda1g/src/i2s/clkctrl.rs create mode 100644 pac/atsamda1g/src/i2s/ctrla.rs create mode 100644 pac/atsamda1g/src/i2s/data.rs create mode 100644 pac/atsamda1g/src/i2s/intenclr.rs create mode 100644 pac/atsamda1g/src/i2s/intenset.rs create mode 100644 pac/atsamda1g/src/i2s/intflag.rs create mode 100644 pac/atsamda1g/src/i2s/serctrl.rs create mode 100644 pac/atsamda1g/src/i2s/syncbusy.rs create mode 100644 pac/atsamda1g/src/lib.rs create mode 100644 pac/atsamda1g/src/mtb.rs create mode 100644 pac/atsamda1g/src/mtb/authstatus.rs create mode 100644 pac/atsamda1g/src/mtb/base.rs create mode 100644 pac/atsamda1g/src/mtb/cid0.rs create mode 100644 pac/atsamda1g/src/mtb/cid1.rs create mode 100644 pac/atsamda1g/src/mtb/cid2.rs create mode 100644 pac/atsamda1g/src/mtb/cid3.rs create mode 100644 pac/atsamda1g/src/mtb/claimclr.rs create mode 100644 pac/atsamda1g/src/mtb/claimset.rs create mode 100644 pac/atsamda1g/src/mtb/devarch.rs create mode 100644 pac/atsamda1g/src/mtb/devid.rs create mode 100644 pac/atsamda1g/src/mtb/devtype.rs create mode 100644 pac/atsamda1g/src/mtb/flow.rs create mode 100644 pac/atsamda1g/src/mtb/itctrl.rs create mode 100644 pac/atsamda1g/src/mtb/lockaccess.rs create mode 100644 pac/atsamda1g/src/mtb/lockstatus.rs create mode 100644 pac/atsamda1g/src/mtb/master.rs create mode 100644 pac/atsamda1g/src/mtb/pid0.rs create mode 100644 pac/atsamda1g/src/mtb/pid1.rs create mode 100644 pac/atsamda1g/src/mtb/pid2.rs create mode 100644 pac/atsamda1g/src/mtb/pid3.rs create mode 100644 pac/atsamda1g/src/mtb/pid4.rs create mode 100644 pac/atsamda1g/src/mtb/pid5.rs create mode 100644 pac/atsamda1g/src/mtb/pid6.rs create mode 100644 pac/atsamda1g/src/mtb/pid7.rs create mode 100644 pac/atsamda1g/src/mtb/position.rs create mode 100644 pac/atsamda1g/src/nvmctrl.rs create mode 100644 pac/atsamda1g/src/nvmctrl/addr.rs create mode 100644 pac/atsamda1g/src/nvmctrl/ctrla.rs create mode 100644 pac/atsamda1g/src/nvmctrl/ctrlb.rs create mode 100644 pac/atsamda1g/src/nvmctrl/intenclr.rs create mode 100644 pac/atsamda1g/src/nvmctrl/intenset.rs create mode 100644 pac/atsamda1g/src/nvmctrl/intflag.rs create mode 100644 pac/atsamda1g/src/nvmctrl/lock.rs create mode 100644 pac/atsamda1g/src/nvmctrl/param.rs create mode 100644 pac/atsamda1g/src/nvmctrl/status.rs create mode 100644 pac/atsamda1g/src/pac0.rs create mode 100644 pac/atsamda1g/src/pac0/wpclr.rs create mode 100644 pac/atsamda1g/src/pac0/wpset.rs create mode 100644 pac/atsamda1g/src/pm.rs create mode 100644 pac/atsamda1g/src/pm/ahbmask.rs create mode 100644 pac/atsamda1g/src/pm/apbamask.rs create mode 100644 pac/atsamda1g/src/pm/apbasel.rs create mode 100644 pac/atsamda1g/src/pm/apbbmask.rs create mode 100644 pac/atsamda1g/src/pm/apbbsel.rs create mode 100644 pac/atsamda1g/src/pm/apbcmask.rs create mode 100644 pac/atsamda1g/src/pm/apbcsel.rs create mode 100644 pac/atsamda1g/src/pm/cpusel.rs create mode 100644 pac/atsamda1g/src/pm/ctrl.rs create mode 100644 pac/atsamda1g/src/pm/extctrl.rs create mode 100644 pac/atsamda1g/src/pm/intenclr.rs create mode 100644 pac/atsamda1g/src/pm/intenset.rs create mode 100644 pac/atsamda1g/src/pm/intflag.rs create mode 100644 pac/atsamda1g/src/pm/rcause.rs create mode 100644 pac/atsamda1g/src/pm/sleep.rs create mode 100644 pac/atsamda1g/src/port.rs create mode 100644 pac/atsamda1g/src/port/group.rs create mode 100644 pac/atsamda1g/src/port/group/ctrl.rs create mode 100644 pac/atsamda1g/src/port/group/dir.rs create mode 100644 pac/atsamda1g/src/port/group/dirclr.rs create mode 100644 pac/atsamda1g/src/port/group/dirset.rs create mode 100644 pac/atsamda1g/src/port/group/dirtgl.rs create mode 100644 pac/atsamda1g/src/port/group/in_.rs create mode 100644 pac/atsamda1g/src/port/group/out.rs create mode 100644 pac/atsamda1g/src/port/group/outclr.rs create mode 100644 pac/atsamda1g/src/port/group/outset.rs create mode 100644 pac/atsamda1g/src/port/group/outtgl.rs create mode 100644 pac/atsamda1g/src/port/group/pincfg.rs create mode 100644 pac/atsamda1g/src/port/group/pmux.rs create mode 100644 pac/atsamda1g/src/port/group/wrconfig.rs create mode 100644 pac/atsamda1g/src/rtc.rs create mode 100644 pac/atsamda1g/src/rtc/mode0.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/comp.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/count.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/ctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/dbgctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/evctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/freqcorr.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/intenclr.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/intenset.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/intflag.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/readreq.rs create mode 100644 pac/atsamda1g/src/rtc/mode0/status.rs create mode 100644 pac/atsamda1g/src/rtc/mode1.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/comp.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/count.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/ctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/dbgctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/evctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/freqcorr.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/intenclr.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/intenset.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/intflag.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/per.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/readreq.rs create mode 100644 pac/atsamda1g/src/rtc/mode1/status.rs create mode 100644 pac/atsamda1g/src/rtc/mode2.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/alarm.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/clock.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/ctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/dbgctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/evctrl.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/freqcorr.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/intenclr.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/intenset.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/intflag.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/mask.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/readreq.rs create mode 100644 pac/atsamda1g/src/rtc/mode2/status.rs create mode 100644 pac/atsamda1g/src/sbmatrix.rs create mode 100644 pac/atsamda1g/src/sbmatrix/prs.rs create mode 100644 pac/atsamda1g/src/sbmatrix/prs/pras.rs create mode 100644 pac/atsamda1g/src/sbmatrix/prs/prbs.rs create mode 100644 pac/atsamda1g/src/sbmatrix/sfr.rs create mode 100644 pac/atsamda1g/src/sercom0.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/addr.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/baud.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/ctrla.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/ctrlb.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/data.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/dbgctrl.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/intenclr.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/intenset.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/intflag.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/status.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cm/syncbusy.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/addr.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/ctrla.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/ctrlb.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/data.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/intenclr.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/intenset.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/intflag.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/status.rs create mode 100644 pac/atsamda1g/src/sercom0/i2cs/syncbusy.rs create mode 100644 pac/atsamda1g/src/sercom0/spim.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/addr.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/baud.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/ctrla.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/ctrlb.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/data.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/dbgctrl.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/intenclr.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/intenset.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/intflag.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/status.rs create mode 100644 pac/atsamda1g/src/sercom0/spim/syncbusy.rs create mode 100644 pac/atsamda1g/src/sercom0/spis.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/addr.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/baud.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/ctrla.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/ctrlb.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/data.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/dbgctrl.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/intenclr.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/intenset.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/intflag.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/status.rs create mode 100644 pac/atsamda1g/src/sercom0/spis/syncbusy.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/baud.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/baud_frac_mode.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/baud_fracfp_mode.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/baud_usartfp_mode.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/ctrla.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/ctrlb.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/data.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/dbgctrl.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/intenclr.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/intenset.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/intflag.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/rxpl.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/status.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_ext/syncbusy.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/baud.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/baud_frac_mode.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/baud_fracfp_mode.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/baud_usartfp_mode.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/ctrla.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/ctrlb.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/data.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/dbgctrl.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/intenclr.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/intenset.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/intflag.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/rxpl.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/status.rs create mode 100644 pac/atsamda1g/src/sercom0/usart_int/syncbusy.rs create mode 100644 pac/atsamda1g/src/sys_tick.rs create mode 100644 pac/atsamda1g/src/sys_tick/calib.rs create mode 100644 pac/atsamda1g/src/sys_tick/csr.rs create mode 100644 pac/atsamda1g/src/sys_tick/cvr.rs create mode 100644 pac/atsamda1g/src/sys_tick/rvr.rs create mode 100644 pac/atsamda1g/src/sysctrl.rs create mode 100644 pac/atsamda1g/src/sysctrl/bod33.rs create mode 100644 pac/atsamda1g/src/sysctrl/dfllctrl.rs create mode 100644 pac/atsamda1g/src/sysctrl/dfllmul.rs create mode 100644 pac/atsamda1g/src/sysctrl/dfllsync.rs create mode 100644 pac/atsamda1g/src/sysctrl/dfllval.rs create mode 100644 pac/atsamda1g/src/sysctrl/dpllctrla.rs create mode 100644 pac/atsamda1g/src/sysctrl/dpllctrlb.rs create mode 100644 pac/atsamda1g/src/sysctrl/dpllratio.rs create mode 100644 pac/atsamda1g/src/sysctrl/dpllstatus.rs create mode 100644 pac/atsamda1g/src/sysctrl/intenclr.rs create mode 100644 pac/atsamda1g/src/sysctrl/intenset.rs create mode 100644 pac/atsamda1g/src/sysctrl/intflag.rs create mode 100644 pac/atsamda1g/src/sysctrl/osc32k.rs create mode 100644 pac/atsamda1g/src/sysctrl/osc8m.rs create mode 100644 pac/atsamda1g/src/sysctrl/osculp32k.rs create mode 100644 pac/atsamda1g/src/sysctrl/pclksr.rs create mode 100644 pac/atsamda1g/src/sysctrl/vref.rs create mode 100644 pac/atsamda1g/src/sysctrl/vreg.rs create mode 100644 pac/atsamda1g/src/sysctrl/xosc.rs create mode 100644 pac/atsamda1g/src/sysctrl/xosc32k.rs create mode 100644 pac/atsamda1g/src/system_control.rs create mode 100644 pac/atsamda1g/src/system_control/aircr.rs create mode 100644 pac/atsamda1g/src/system_control/ccr.rs create mode 100644 pac/atsamda1g/src/system_control/cpuid.rs create mode 100644 pac/atsamda1g/src/system_control/dfsr.rs create mode 100644 pac/atsamda1g/src/system_control/icsr.rs create mode 100644 pac/atsamda1g/src/system_control/scr.rs create mode 100644 pac/atsamda1g/src/system_control/shcsr.rs create mode 100644 pac/atsamda1g/src/system_control/shpr2.rs create mode 100644 pac/atsamda1g/src/system_control/shpr3.rs create mode 100644 pac/atsamda1g/src/system_control/vtor.rs create mode 100644 pac/atsamda1g/src/tc3.rs create mode 100644 pac/atsamda1g/src/tc3/count16.rs create mode 100644 pac/atsamda1g/src/tc3/count16/cc.rs create mode 100644 pac/atsamda1g/src/tc3/count16/count.rs create mode 100644 pac/atsamda1g/src/tc3/count16/ctrla.rs create mode 100644 pac/atsamda1g/src/tc3/count16/ctrlbclr.rs create mode 100644 pac/atsamda1g/src/tc3/count16/ctrlbset.rs create mode 100644 pac/atsamda1g/src/tc3/count16/ctrlc.rs create mode 100644 pac/atsamda1g/src/tc3/count16/dbgctrl.rs create mode 100644 pac/atsamda1g/src/tc3/count16/evctrl.rs create mode 100644 pac/atsamda1g/src/tc3/count16/intenclr.rs create mode 100644 pac/atsamda1g/src/tc3/count16/intenset.rs create mode 100644 pac/atsamda1g/src/tc3/count16/intflag.rs create mode 100644 pac/atsamda1g/src/tc3/count16/readreq.rs create mode 100644 pac/atsamda1g/src/tc3/count16/status.rs create mode 100644 pac/atsamda1g/src/tc3/count32.rs create mode 100644 pac/atsamda1g/src/tc3/count32/cc.rs create mode 100644 pac/atsamda1g/src/tc3/count32/count.rs create mode 100644 pac/atsamda1g/src/tc3/count32/ctrla.rs create mode 100644 pac/atsamda1g/src/tc3/count32/ctrlbclr.rs create mode 100644 pac/atsamda1g/src/tc3/count32/ctrlbset.rs create mode 100644 pac/atsamda1g/src/tc3/count32/ctrlc.rs create mode 100644 pac/atsamda1g/src/tc3/count32/dbgctrl.rs create mode 100644 pac/atsamda1g/src/tc3/count32/evctrl.rs create mode 100644 pac/atsamda1g/src/tc3/count32/intenclr.rs create mode 100644 pac/atsamda1g/src/tc3/count32/intenset.rs create mode 100644 pac/atsamda1g/src/tc3/count32/intflag.rs create mode 100644 pac/atsamda1g/src/tc3/count32/readreq.rs create mode 100644 pac/atsamda1g/src/tc3/count32/status.rs create mode 100644 pac/atsamda1g/src/tc3/count8.rs create mode 100644 pac/atsamda1g/src/tc3/count8/cc.rs create mode 100644 pac/atsamda1g/src/tc3/count8/count.rs create mode 100644 pac/atsamda1g/src/tc3/count8/ctrla.rs create mode 100644 pac/atsamda1g/src/tc3/count8/ctrlbclr.rs create mode 100644 pac/atsamda1g/src/tc3/count8/ctrlbset.rs create mode 100644 pac/atsamda1g/src/tc3/count8/ctrlc.rs create mode 100644 pac/atsamda1g/src/tc3/count8/dbgctrl.rs create mode 100644 pac/atsamda1g/src/tc3/count8/evctrl.rs create mode 100644 pac/atsamda1g/src/tc3/count8/intenclr.rs create mode 100644 pac/atsamda1g/src/tc3/count8/intenset.rs create mode 100644 pac/atsamda1g/src/tc3/count8/intflag.rs create mode 100644 pac/atsamda1g/src/tc3/count8/per.rs create mode 100644 pac/atsamda1g/src/tc3/count8/readreq.rs create mode 100644 pac/atsamda1g/src/tc3/count8/status.rs create mode 100644 pac/atsamda1g/src/tcc0.rs create mode 100644 pac/atsamda1g/src/tcc0/cc.rs create mode 100644 pac/atsamda1g/src/tcc0/cc_dith4_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/cc_dith5_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/cc_dith6_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/ccb.rs create mode 100644 pac/atsamda1g/src/tcc0/ccb_dith4_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/ccb_dith5_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/ccb_dith6_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/count.rs create mode 100644 pac/atsamda1g/src/tcc0/count_dith4_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/count_dith5_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/count_dith6_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/ctrla.rs create mode 100644 pac/atsamda1g/src/tcc0/ctrlbclr.rs create mode 100644 pac/atsamda1g/src/tcc0/ctrlbset.rs create mode 100644 pac/atsamda1g/src/tcc0/dbgctrl.rs create mode 100644 pac/atsamda1g/src/tcc0/drvctrl.rs create mode 100644 pac/atsamda1g/src/tcc0/evctrl.rs create mode 100644 pac/atsamda1g/src/tcc0/fctrla.rs create mode 100644 pac/atsamda1g/src/tcc0/fctrlb.rs create mode 100644 pac/atsamda1g/src/tcc0/intenclr.rs create mode 100644 pac/atsamda1g/src/tcc0/intenset.rs create mode 100644 pac/atsamda1g/src/tcc0/intflag.rs create mode 100644 pac/atsamda1g/src/tcc0/patt.rs create mode 100644 pac/atsamda1g/src/tcc0/pattb.rs create mode 100644 pac/atsamda1g/src/tcc0/per.rs create mode 100644 pac/atsamda1g/src/tcc0/per_dith4_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/per_dith5_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/per_dith6_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/perb.rs create mode 100644 pac/atsamda1g/src/tcc0/perb_dith4_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/perb_dith5_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/perb_dith6_mode.rs create mode 100644 pac/atsamda1g/src/tcc0/status.rs create mode 100644 pac/atsamda1g/src/tcc0/syncbusy.rs create mode 100644 pac/atsamda1g/src/tcc0/wave.rs create mode 100644 pac/atsamda1g/src/tcc0/waveb.rs create mode 100644 pac/atsamda1g/src/tcc0/wexctrl.rs create mode 100644 pac/atsamda1g/src/usb.rs create mode 100644 pac/atsamda1g/src/usb/device.rs create mode 100644 pac/atsamda1g/src/usb/device/ctrla.rs create mode 100644 pac/atsamda1g/src/usb/device/ctrlb.rs create mode 100644 pac/atsamda1g/src/usb/device/dadd.rs create mode 100644 pac/atsamda1g/src/usb/device/descadd.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint/epcfg.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint/epintenclr.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint/epintenset.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint/epintflag.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint/epstatus.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint/epstatusclr.rs create mode 100644 pac/atsamda1g/src/usb/device/device_endpoint/epstatusset.rs create mode 100644 pac/atsamda1g/src/usb/device/epintsmry.rs create mode 100644 pac/atsamda1g/src/usb/device/fnum.rs create mode 100644 pac/atsamda1g/src/usb/device/fsmstatus.rs create mode 100644 pac/atsamda1g/src/usb/device/intenclr.rs create mode 100644 pac/atsamda1g/src/usb/device/intenset.rs create mode 100644 pac/atsamda1g/src/usb/device/intflag.rs create mode 100644 pac/atsamda1g/src/usb/device/padcal.rs create mode 100644 pac/atsamda1g/src/usb/device/qosctrl.rs create mode 100644 pac/atsamda1g/src/usb/device/status.rs create mode 100644 pac/atsamda1g/src/usb/device/syncbusy.rs create mode 100644 pac/atsamda1g/src/usb/host.rs create mode 100644 pac/atsamda1g/src/usb/host/ctrla.rs create mode 100644 pac/atsamda1g/src/usb/host/ctrlb.rs create mode 100644 pac/atsamda1g/src/usb/host/descadd.rs create mode 100644 pac/atsamda1g/src/usb/host/flenhigh.rs create mode 100644 pac/atsamda1g/src/usb/host/fnum.rs create mode 100644 pac/atsamda1g/src/usb/host/fsmstatus.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/binterval.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/pcfg.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/pintenclr.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/pintenset.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/pintflag.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/pstatus.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/pstatusclr.rs create mode 100644 pac/atsamda1g/src/usb/host/host_pipe/pstatusset.rs create mode 100644 pac/atsamda1g/src/usb/host/hsofc.rs create mode 100644 pac/atsamda1g/src/usb/host/intenclr.rs create mode 100644 pac/atsamda1g/src/usb/host/intenset.rs create mode 100644 pac/atsamda1g/src/usb/host/intflag.rs create mode 100644 pac/atsamda1g/src/usb/host/padcal.rs create mode 100644 pac/atsamda1g/src/usb/host/pintsmry.rs create mode 100644 pac/atsamda1g/src/usb/host/qosctrl.rs create mode 100644 pac/atsamda1g/src/usb/host/status.rs create mode 100644 pac/atsamda1g/src/usb/host/syncbusy.rs create mode 100644 pac/atsamda1g/src/wdt.rs create mode 100644 pac/atsamda1g/src/wdt/clear.rs create mode 100644 pac/atsamda1g/src/wdt/config.rs create mode 100644 pac/atsamda1g/src/wdt/ctrl.rs create mode 100644 pac/atsamda1g/src/wdt/ewctrl.rs create mode 100644 pac/atsamda1g/src/wdt/intenclr.rs create mode 100644 pac/atsamda1g/src/wdt/intenset.rs create mode 100644 pac/atsamda1g/src/wdt/intflag.rs create mode 100644 pac/atsamda1g/src/wdt/status.rs create mode 100644 pac/atsamda1j/Cargo.toml create mode 100644 pac/atsamda1j/README.md create mode 100644 pac/atsamda1j/build.rs create mode 100644 pac/atsamda1j/device.x create mode 100644 pac/atsamda1j/src/ac.rs create mode 100644 pac/atsamda1j/src/ac/compctrl.rs create mode 100644 pac/atsamda1j/src/ac/ctrla.rs create mode 100644 pac/atsamda1j/src/ac/ctrlb.rs create mode 100644 pac/atsamda1j/src/ac/evctrl.rs create mode 100644 pac/atsamda1j/src/ac/intenclr.rs create mode 100644 pac/atsamda1j/src/ac/intenset.rs create mode 100644 pac/atsamda1j/src/ac/intflag.rs create mode 100644 pac/atsamda1j/src/ac/scaler.rs create mode 100644 pac/atsamda1j/src/ac/statusa.rs create mode 100644 pac/atsamda1j/src/ac/statusb.rs create mode 100644 pac/atsamda1j/src/ac/statusc.rs create mode 100644 pac/atsamda1j/src/ac/winctrl.rs create mode 100644 pac/atsamda1j/src/adc.rs create mode 100644 pac/atsamda1j/src/adc/avgctrl.rs create mode 100644 pac/atsamda1j/src/adc/calib.rs create mode 100644 pac/atsamda1j/src/adc/ctrla.rs create mode 100644 pac/atsamda1j/src/adc/ctrlb.rs create mode 100644 pac/atsamda1j/src/adc/dbgctrl.rs create mode 100644 pac/atsamda1j/src/adc/evctrl.rs create mode 100644 pac/atsamda1j/src/adc/gaincorr.rs create mode 100644 pac/atsamda1j/src/adc/inputctrl.rs create mode 100644 pac/atsamda1j/src/adc/intenclr.rs create mode 100644 pac/atsamda1j/src/adc/intenset.rs create mode 100644 pac/atsamda1j/src/adc/intflag.rs create mode 100644 pac/atsamda1j/src/adc/offsetcorr.rs create mode 100644 pac/atsamda1j/src/adc/refctrl.rs create mode 100644 pac/atsamda1j/src/adc/result.rs create mode 100644 pac/atsamda1j/src/adc/sampctrl.rs create mode 100644 pac/atsamda1j/src/adc/status.rs create mode 100644 pac/atsamda1j/src/adc/swtrig.rs create mode 100644 pac/atsamda1j/src/adc/winctrl.rs create mode 100644 pac/atsamda1j/src/adc/winlt.rs create mode 100644 pac/atsamda1j/src/adc/winut.rs create mode 100644 pac/atsamda1j/src/dac.rs create mode 100644 pac/atsamda1j/src/dac/ctrla.rs create mode 100644 pac/atsamda1j/src/dac/ctrlb.rs create mode 100644 pac/atsamda1j/src/dac/data.rs create mode 100644 pac/atsamda1j/src/dac/databuf.rs create mode 100644 pac/atsamda1j/src/dac/evctrl.rs create mode 100644 pac/atsamda1j/src/dac/intenclr.rs create mode 100644 pac/atsamda1j/src/dac/intenset.rs create mode 100644 pac/atsamda1j/src/dac/intflag.rs create mode 100644 pac/atsamda1j/src/dac/status.rs create mode 100644 pac/atsamda1j/src/dmac.rs create mode 100644 pac/atsamda1j/src/dmac/active.rs create mode 100644 pac/atsamda1j/src/dmac/baseaddr.rs create mode 100644 pac/atsamda1j/src/dmac/busych.rs create mode 100644 pac/atsamda1j/src/dmac/chctrla.rs create mode 100644 pac/atsamda1j/src/dmac/chctrlb.rs create mode 100644 pac/atsamda1j/src/dmac/chid.rs create mode 100644 pac/atsamda1j/src/dmac/chintenclr.rs create mode 100644 pac/atsamda1j/src/dmac/chintenset.rs create mode 100644 pac/atsamda1j/src/dmac/chintflag.rs create mode 100644 pac/atsamda1j/src/dmac/chstatus.rs create mode 100644 pac/atsamda1j/src/dmac/crcchksum.rs create mode 100644 pac/atsamda1j/src/dmac/crcctrl.rs create mode 100644 pac/atsamda1j/src/dmac/crcdatain.rs create mode 100644 pac/atsamda1j/src/dmac/crcstatus.rs create mode 100644 pac/atsamda1j/src/dmac/ctrl.rs create mode 100644 pac/atsamda1j/src/dmac/dbgctrl.rs create mode 100644 pac/atsamda1j/src/dmac/intpend.rs create mode 100644 pac/atsamda1j/src/dmac/intstatus.rs create mode 100644 pac/atsamda1j/src/dmac/pendch.rs create mode 100644 pac/atsamda1j/src/dmac/prictrl0.rs create mode 100644 pac/atsamda1j/src/dmac/qosctrl.rs create mode 100644 pac/atsamda1j/src/dmac/swtrigctrl.rs create mode 100644 pac/atsamda1j/src/dmac/wrbaddr.rs create mode 100644 pac/atsamda1j/src/dsu.rs create mode 100644 pac/atsamda1j/src/dsu/addr.rs create mode 100644 pac/atsamda1j/src/dsu/cid0.rs create mode 100644 pac/atsamda1j/src/dsu/cid1.rs create mode 100644 pac/atsamda1j/src/dsu/cid2.rs create mode 100644 pac/atsamda1j/src/dsu/cid3.rs create mode 100644 pac/atsamda1j/src/dsu/ctrl.rs create mode 100644 pac/atsamda1j/src/dsu/data.rs create mode 100644 pac/atsamda1j/src/dsu/dcc.rs create mode 100644 pac/atsamda1j/src/dsu/did.rs create mode 100644 pac/atsamda1j/src/dsu/end.rs create mode 100644 pac/atsamda1j/src/dsu/entry0.rs create mode 100644 pac/atsamda1j/src/dsu/entry1.rs create mode 100644 pac/atsamda1j/src/dsu/length.rs create mode 100644 pac/atsamda1j/src/dsu/memtype.rs create mode 100644 pac/atsamda1j/src/dsu/pid0.rs create mode 100644 pac/atsamda1j/src/dsu/pid1.rs create mode 100644 pac/atsamda1j/src/dsu/pid2.rs create mode 100644 pac/atsamda1j/src/dsu/pid3.rs create mode 100644 pac/atsamda1j/src/dsu/pid4.rs create mode 100644 pac/atsamda1j/src/dsu/statusa.rs create mode 100644 pac/atsamda1j/src/dsu/statusb.rs create mode 100644 pac/atsamda1j/src/eic.rs create mode 100644 pac/atsamda1j/src/eic/config.rs create mode 100644 pac/atsamda1j/src/eic/ctrl.rs create mode 100644 pac/atsamda1j/src/eic/evctrl.rs create mode 100644 pac/atsamda1j/src/eic/intenclr.rs create mode 100644 pac/atsamda1j/src/eic/intenset.rs create mode 100644 pac/atsamda1j/src/eic/intflag.rs create mode 100644 pac/atsamda1j/src/eic/nmictrl.rs create mode 100644 pac/atsamda1j/src/eic/nmiflag.rs create mode 100644 pac/atsamda1j/src/eic/status.rs create mode 100644 pac/atsamda1j/src/eic/wakeup.rs create mode 100644 pac/atsamda1j/src/evsys.rs create mode 100644 pac/atsamda1j/src/evsys/channel.rs create mode 100644 pac/atsamda1j/src/evsys/chstatus.rs create mode 100644 pac/atsamda1j/src/evsys/ctrl.rs create mode 100644 pac/atsamda1j/src/evsys/intenclr.rs create mode 100644 pac/atsamda1j/src/evsys/intenset.rs create mode 100644 pac/atsamda1j/src/evsys/intflag.rs create mode 100644 pac/atsamda1j/src/evsys/user.rs create mode 100644 pac/atsamda1j/src/gclk.rs create mode 100644 pac/atsamda1j/src/gclk/clkctrl.rs create mode 100644 pac/atsamda1j/src/gclk/ctrl.rs create mode 100644 pac/atsamda1j/src/gclk/genctrl.rs create mode 100644 pac/atsamda1j/src/gclk/gendiv.rs create mode 100644 pac/atsamda1j/src/gclk/status.rs create mode 100644 pac/atsamda1j/src/generic.rs create mode 100644 pac/atsamda1j/src/i2s.rs create mode 100644 pac/atsamda1j/src/i2s/clkctrl.rs create mode 100644 pac/atsamda1j/src/i2s/ctrla.rs create mode 100644 pac/atsamda1j/src/i2s/data.rs create mode 100644 pac/atsamda1j/src/i2s/intenclr.rs create mode 100644 pac/atsamda1j/src/i2s/intenset.rs create mode 100644 pac/atsamda1j/src/i2s/intflag.rs create mode 100644 pac/atsamda1j/src/i2s/serctrl.rs create mode 100644 pac/atsamda1j/src/i2s/syncbusy.rs create mode 100644 pac/atsamda1j/src/lib.rs create mode 100644 pac/atsamda1j/src/mtb.rs create mode 100644 pac/atsamda1j/src/mtb/authstatus.rs create mode 100644 pac/atsamda1j/src/mtb/base.rs create mode 100644 pac/atsamda1j/src/mtb/cid0.rs create mode 100644 pac/atsamda1j/src/mtb/cid1.rs create mode 100644 pac/atsamda1j/src/mtb/cid2.rs create mode 100644 pac/atsamda1j/src/mtb/cid3.rs create mode 100644 pac/atsamda1j/src/mtb/claimclr.rs create mode 100644 pac/atsamda1j/src/mtb/claimset.rs create mode 100644 pac/atsamda1j/src/mtb/devarch.rs create mode 100644 pac/atsamda1j/src/mtb/devid.rs create mode 100644 pac/atsamda1j/src/mtb/devtype.rs create mode 100644 pac/atsamda1j/src/mtb/flow.rs create mode 100644 pac/atsamda1j/src/mtb/itctrl.rs create mode 100644 pac/atsamda1j/src/mtb/lockaccess.rs create mode 100644 pac/atsamda1j/src/mtb/lockstatus.rs create mode 100644 pac/atsamda1j/src/mtb/master.rs create mode 100644 pac/atsamda1j/src/mtb/pid0.rs create mode 100644 pac/atsamda1j/src/mtb/pid1.rs create mode 100644 pac/atsamda1j/src/mtb/pid2.rs create mode 100644 pac/atsamda1j/src/mtb/pid3.rs create mode 100644 pac/atsamda1j/src/mtb/pid4.rs create mode 100644 pac/atsamda1j/src/mtb/pid5.rs create mode 100644 pac/atsamda1j/src/mtb/pid6.rs create mode 100644 pac/atsamda1j/src/mtb/pid7.rs create mode 100644 pac/atsamda1j/src/mtb/position.rs create mode 100644 pac/atsamda1j/src/nvmctrl.rs create mode 100644 pac/atsamda1j/src/nvmctrl/addr.rs create mode 100644 pac/atsamda1j/src/nvmctrl/ctrla.rs create mode 100644 pac/atsamda1j/src/nvmctrl/ctrlb.rs create mode 100644 pac/atsamda1j/src/nvmctrl/intenclr.rs create mode 100644 pac/atsamda1j/src/nvmctrl/intenset.rs create mode 100644 pac/atsamda1j/src/nvmctrl/intflag.rs create mode 100644 pac/atsamda1j/src/nvmctrl/lock.rs create mode 100644 pac/atsamda1j/src/nvmctrl/param.rs create mode 100644 pac/atsamda1j/src/nvmctrl/status.rs create mode 100644 pac/atsamda1j/src/pac0.rs create mode 100644 pac/atsamda1j/src/pac0/wpclr.rs create mode 100644 pac/atsamda1j/src/pac0/wpset.rs create mode 100644 pac/atsamda1j/src/pm.rs create mode 100644 pac/atsamda1j/src/pm/ahbmask.rs create mode 100644 pac/atsamda1j/src/pm/apbamask.rs create mode 100644 pac/atsamda1j/src/pm/apbasel.rs create mode 100644 pac/atsamda1j/src/pm/apbbmask.rs create mode 100644 pac/atsamda1j/src/pm/apbbsel.rs create mode 100644 pac/atsamda1j/src/pm/apbcmask.rs create mode 100644 pac/atsamda1j/src/pm/apbcsel.rs create mode 100644 pac/atsamda1j/src/pm/cpusel.rs create mode 100644 pac/atsamda1j/src/pm/ctrl.rs create mode 100644 pac/atsamda1j/src/pm/extctrl.rs create mode 100644 pac/atsamda1j/src/pm/intenclr.rs create mode 100644 pac/atsamda1j/src/pm/intenset.rs create mode 100644 pac/atsamda1j/src/pm/intflag.rs create mode 100644 pac/atsamda1j/src/pm/rcause.rs create mode 100644 pac/atsamda1j/src/pm/sleep.rs create mode 100644 pac/atsamda1j/src/port.rs create mode 100644 pac/atsamda1j/src/port/group.rs create mode 100644 pac/atsamda1j/src/port/group/ctrl.rs create mode 100644 pac/atsamda1j/src/port/group/dir.rs create mode 100644 pac/atsamda1j/src/port/group/dirclr.rs create mode 100644 pac/atsamda1j/src/port/group/dirset.rs create mode 100644 pac/atsamda1j/src/port/group/dirtgl.rs create mode 100644 pac/atsamda1j/src/port/group/in_.rs create mode 100644 pac/atsamda1j/src/port/group/out.rs create mode 100644 pac/atsamda1j/src/port/group/outclr.rs create mode 100644 pac/atsamda1j/src/port/group/outset.rs create mode 100644 pac/atsamda1j/src/port/group/outtgl.rs create mode 100644 pac/atsamda1j/src/port/group/pincfg.rs create mode 100644 pac/atsamda1j/src/port/group/pmux.rs create mode 100644 pac/atsamda1j/src/port/group/wrconfig.rs create mode 100644 pac/atsamda1j/src/rtc.rs create mode 100644 pac/atsamda1j/src/rtc/mode0.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/comp.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/count.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/ctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/dbgctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/evctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/freqcorr.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/intenclr.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/intenset.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/intflag.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/readreq.rs create mode 100644 pac/atsamda1j/src/rtc/mode0/status.rs create mode 100644 pac/atsamda1j/src/rtc/mode1.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/comp.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/count.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/ctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/dbgctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/evctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/freqcorr.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/intenclr.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/intenset.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/intflag.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/per.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/readreq.rs create mode 100644 pac/atsamda1j/src/rtc/mode1/status.rs create mode 100644 pac/atsamda1j/src/rtc/mode2.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/alarm.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/clock.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/ctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/dbgctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/evctrl.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/freqcorr.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/intenclr.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/intenset.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/intflag.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/mask.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/readreq.rs create mode 100644 pac/atsamda1j/src/rtc/mode2/status.rs create mode 100644 pac/atsamda1j/src/sbmatrix.rs create mode 100644 pac/atsamda1j/src/sbmatrix/prs.rs create mode 100644 pac/atsamda1j/src/sbmatrix/prs/pras.rs create mode 100644 pac/atsamda1j/src/sbmatrix/prs/prbs.rs create mode 100644 pac/atsamda1j/src/sbmatrix/sfr.rs create mode 100644 pac/atsamda1j/src/sercom0.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/addr.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/baud.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/ctrla.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/ctrlb.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/data.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/dbgctrl.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/intenclr.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/intenset.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/intflag.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/status.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cm/syncbusy.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/addr.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/ctrla.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/ctrlb.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/data.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/intenclr.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/intenset.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/intflag.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/status.rs create mode 100644 pac/atsamda1j/src/sercom0/i2cs/syncbusy.rs create mode 100644 pac/atsamda1j/src/sercom0/spim.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/addr.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/baud.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/ctrla.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/ctrlb.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/data.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/dbgctrl.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/intenclr.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/intenset.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/intflag.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/status.rs create mode 100644 pac/atsamda1j/src/sercom0/spim/syncbusy.rs create mode 100644 pac/atsamda1j/src/sercom0/spis.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/addr.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/baud.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/ctrla.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/ctrlb.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/data.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/dbgctrl.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/intenclr.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/intenset.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/intflag.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/status.rs create mode 100644 pac/atsamda1j/src/sercom0/spis/syncbusy.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/baud.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/baud_frac_mode.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/baud_fracfp_mode.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/baud_usartfp_mode.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/ctrla.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/ctrlb.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/data.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/dbgctrl.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/intenclr.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/intenset.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/intflag.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/rxpl.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/status.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_ext/syncbusy.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/baud.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/baud_frac_mode.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/baud_fracfp_mode.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/baud_usartfp_mode.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/ctrla.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/ctrlb.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/data.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/dbgctrl.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/intenclr.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/intenset.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/intflag.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/rxpl.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/status.rs create mode 100644 pac/atsamda1j/src/sercom0/usart_int/syncbusy.rs create mode 100644 pac/atsamda1j/src/sys_tick.rs create mode 100644 pac/atsamda1j/src/sys_tick/calib.rs create mode 100644 pac/atsamda1j/src/sys_tick/csr.rs create mode 100644 pac/atsamda1j/src/sys_tick/cvr.rs create mode 100644 pac/atsamda1j/src/sys_tick/rvr.rs create mode 100644 pac/atsamda1j/src/sysctrl.rs create mode 100644 pac/atsamda1j/src/sysctrl/bod33.rs create mode 100644 pac/atsamda1j/src/sysctrl/dfllctrl.rs create mode 100644 pac/atsamda1j/src/sysctrl/dfllmul.rs create mode 100644 pac/atsamda1j/src/sysctrl/dfllsync.rs create mode 100644 pac/atsamda1j/src/sysctrl/dfllval.rs create mode 100644 pac/atsamda1j/src/sysctrl/dpllctrla.rs create mode 100644 pac/atsamda1j/src/sysctrl/dpllctrlb.rs create mode 100644 pac/atsamda1j/src/sysctrl/dpllratio.rs create mode 100644 pac/atsamda1j/src/sysctrl/dpllstatus.rs create mode 100644 pac/atsamda1j/src/sysctrl/intenclr.rs create mode 100644 pac/atsamda1j/src/sysctrl/intenset.rs create mode 100644 pac/atsamda1j/src/sysctrl/intflag.rs create mode 100644 pac/atsamda1j/src/sysctrl/osc32k.rs create mode 100644 pac/atsamda1j/src/sysctrl/osc8m.rs create mode 100644 pac/atsamda1j/src/sysctrl/osculp32k.rs create mode 100644 pac/atsamda1j/src/sysctrl/pclksr.rs create mode 100644 pac/atsamda1j/src/sysctrl/vref.rs create mode 100644 pac/atsamda1j/src/sysctrl/vreg.rs create mode 100644 pac/atsamda1j/src/sysctrl/xosc.rs create mode 100644 pac/atsamda1j/src/sysctrl/xosc32k.rs create mode 100644 pac/atsamda1j/src/system_control.rs create mode 100644 pac/atsamda1j/src/system_control/aircr.rs create mode 100644 pac/atsamda1j/src/system_control/ccr.rs create mode 100644 pac/atsamda1j/src/system_control/cpuid.rs create mode 100644 pac/atsamda1j/src/system_control/dfsr.rs create mode 100644 pac/atsamda1j/src/system_control/icsr.rs create mode 100644 pac/atsamda1j/src/system_control/scr.rs create mode 100644 pac/atsamda1j/src/system_control/shcsr.rs create mode 100644 pac/atsamda1j/src/system_control/shpr2.rs create mode 100644 pac/atsamda1j/src/system_control/shpr3.rs create mode 100644 pac/atsamda1j/src/system_control/vtor.rs create mode 100644 pac/atsamda1j/src/tc3.rs create mode 100644 pac/atsamda1j/src/tc3/count16.rs create mode 100644 pac/atsamda1j/src/tc3/count16/cc.rs create mode 100644 pac/atsamda1j/src/tc3/count16/count.rs create mode 100644 pac/atsamda1j/src/tc3/count16/ctrla.rs create mode 100644 pac/atsamda1j/src/tc3/count16/ctrlbclr.rs create mode 100644 pac/atsamda1j/src/tc3/count16/ctrlbset.rs create mode 100644 pac/atsamda1j/src/tc3/count16/ctrlc.rs create mode 100644 pac/atsamda1j/src/tc3/count16/dbgctrl.rs create mode 100644 pac/atsamda1j/src/tc3/count16/evctrl.rs create mode 100644 pac/atsamda1j/src/tc3/count16/intenclr.rs create mode 100644 pac/atsamda1j/src/tc3/count16/intenset.rs create mode 100644 pac/atsamda1j/src/tc3/count16/intflag.rs create mode 100644 pac/atsamda1j/src/tc3/count16/readreq.rs create mode 100644 pac/atsamda1j/src/tc3/count16/status.rs create mode 100644 pac/atsamda1j/src/tc3/count32.rs create mode 100644 pac/atsamda1j/src/tc3/count32/cc.rs create mode 100644 pac/atsamda1j/src/tc3/count32/count.rs create mode 100644 pac/atsamda1j/src/tc3/count32/ctrla.rs create mode 100644 pac/atsamda1j/src/tc3/count32/ctrlbclr.rs create mode 100644 pac/atsamda1j/src/tc3/count32/ctrlbset.rs create mode 100644 pac/atsamda1j/src/tc3/count32/ctrlc.rs create mode 100644 pac/atsamda1j/src/tc3/count32/dbgctrl.rs create mode 100644 pac/atsamda1j/src/tc3/count32/evctrl.rs create mode 100644 pac/atsamda1j/src/tc3/count32/intenclr.rs create mode 100644 pac/atsamda1j/src/tc3/count32/intenset.rs create mode 100644 pac/atsamda1j/src/tc3/count32/intflag.rs create mode 100644 pac/atsamda1j/src/tc3/count32/readreq.rs create mode 100644 pac/atsamda1j/src/tc3/count32/status.rs create mode 100644 pac/atsamda1j/src/tc3/count8.rs create mode 100644 pac/atsamda1j/src/tc3/count8/cc.rs create mode 100644 pac/atsamda1j/src/tc3/count8/count.rs create mode 100644 pac/atsamda1j/src/tc3/count8/ctrla.rs create mode 100644 pac/atsamda1j/src/tc3/count8/ctrlbclr.rs create mode 100644 pac/atsamda1j/src/tc3/count8/ctrlbset.rs create mode 100644 pac/atsamda1j/src/tc3/count8/ctrlc.rs create mode 100644 pac/atsamda1j/src/tc3/count8/dbgctrl.rs create mode 100644 pac/atsamda1j/src/tc3/count8/evctrl.rs create mode 100644 pac/atsamda1j/src/tc3/count8/intenclr.rs create mode 100644 pac/atsamda1j/src/tc3/count8/intenset.rs create mode 100644 pac/atsamda1j/src/tc3/count8/intflag.rs create mode 100644 pac/atsamda1j/src/tc3/count8/per.rs create mode 100644 pac/atsamda1j/src/tc3/count8/readreq.rs create mode 100644 pac/atsamda1j/src/tc3/count8/status.rs create mode 100644 pac/atsamda1j/src/tcc0.rs create mode 100644 pac/atsamda1j/src/tcc0/cc.rs create mode 100644 pac/atsamda1j/src/tcc0/cc_dith4_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/cc_dith5_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/cc_dith6_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/ccb.rs create mode 100644 pac/atsamda1j/src/tcc0/ccb_dith4_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/ccb_dith5_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/ccb_dith6_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/count.rs create mode 100644 pac/atsamda1j/src/tcc0/count_dith4_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/count_dith5_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/count_dith6_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/ctrla.rs create mode 100644 pac/atsamda1j/src/tcc0/ctrlbclr.rs create mode 100644 pac/atsamda1j/src/tcc0/ctrlbset.rs create mode 100644 pac/atsamda1j/src/tcc0/dbgctrl.rs create mode 100644 pac/atsamda1j/src/tcc0/drvctrl.rs create mode 100644 pac/atsamda1j/src/tcc0/evctrl.rs create mode 100644 pac/atsamda1j/src/tcc0/fctrla.rs create mode 100644 pac/atsamda1j/src/tcc0/fctrlb.rs create mode 100644 pac/atsamda1j/src/tcc0/intenclr.rs create mode 100644 pac/atsamda1j/src/tcc0/intenset.rs create mode 100644 pac/atsamda1j/src/tcc0/intflag.rs create mode 100644 pac/atsamda1j/src/tcc0/patt.rs create mode 100644 pac/atsamda1j/src/tcc0/pattb.rs create mode 100644 pac/atsamda1j/src/tcc0/per.rs create mode 100644 pac/atsamda1j/src/tcc0/per_dith4_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/per_dith5_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/per_dith6_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/perb.rs create mode 100644 pac/atsamda1j/src/tcc0/perb_dith4_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/perb_dith5_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/perb_dith6_mode.rs create mode 100644 pac/atsamda1j/src/tcc0/status.rs create mode 100644 pac/atsamda1j/src/tcc0/syncbusy.rs create mode 100644 pac/atsamda1j/src/tcc0/wave.rs create mode 100644 pac/atsamda1j/src/tcc0/waveb.rs create mode 100644 pac/atsamda1j/src/tcc0/wexctrl.rs create mode 100644 pac/atsamda1j/src/usb.rs create mode 100644 pac/atsamda1j/src/usb/device.rs create mode 100644 pac/atsamda1j/src/usb/device/ctrla.rs create mode 100644 pac/atsamda1j/src/usb/device/ctrlb.rs create mode 100644 pac/atsamda1j/src/usb/device/dadd.rs create mode 100644 pac/atsamda1j/src/usb/device/descadd.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint/epcfg.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint/epintenclr.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint/epintenset.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint/epintflag.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint/epstatus.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint/epstatusclr.rs create mode 100644 pac/atsamda1j/src/usb/device/device_endpoint/epstatusset.rs create mode 100644 pac/atsamda1j/src/usb/device/epintsmry.rs create mode 100644 pac/atsamda1j/src/usb/device/fnum.rs create mode 100644 pac/atsamda1j/src/usb/device/fsmstatus.rs create mode 100644 pac/atsamda1j/src/usb/device/intenclr.rs create mode 100644 pac/atsamda1j/src/usb/device/intenset.rs create mode 100644 pac/atsamda1j/src/usb/device/intflag.rs create mode 100644 pac/atsamda1j/src/usb/device/padcal.rs create mode 100644 pac/atsamda1j/src/usb/device/qosctrl.rs create mode 100644 pac/atsamda1j/src/usb/device/status.rs create mode 100644 pac/atsamda1j/src/usb/device/syncbusy.rs create mode 100644 pac/atsamda1j/src/usb/host.rs create mode 100644 pac/atsamda1j/src/usb/host/ctrla.rs create mode 100644 pac/atsamda1j/src/usb/host/ctrlb.rs create mode 100644 pac/atsamda1j/src/usb/host/descadd.rs create mode 100644 pac/atsamda1j/src/usb/host/flenhigh.rs create mode 100644 pac/atsamda1j/src/usb/host/fnum.rs create mode 100644 pac/atsamda1j/src/usb/host/fsmstatus.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/binterval.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/pcfg.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/pintenclr.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/pintenset.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/pintflag.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/pstatus.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/pstatusclr.rs create mode 100644 pac/atsamda1j/src/usb/host/host_pipe/pstatusset.rs create mode 100644 pac/atsamda1j/src/usb/host/hsofc.rs create mode 100644 pac/atsamda1j/src/usb/host/intenclr.rs create mode 100644 pac/atsamda1j/src/usb/host/intenset.rs create mode 100644 pac/atsamda1j/src/usb/host/intflag.rs create mode 100644 pac/atsamda1j/src/usb/host/padcal.rs create mode 100644 pac/atsamda1j/src/usb/host/pintsmry.rs create mode 100644 pac/atsamda1j/src/usb/host/qosctrl.rs create mode 100644 pac/atsamda1j/src/usb/host/status.rs create mode 100644 pac/atsamda1j/src/usb/host/syncbusy.rs create mode 100644 pac/atsamda1j/src/wdt.rs create mode 100644 pac/atsamda1j/src/wdt/clear.rs create mode 100644 pac/atsamda1j/src/wdt/config.rs create mode 100644 pac/atsamda1j/src/wdt/ctrl.rs create mode 100644 pac/atsamda1j/src/wdt/ewctrl.rs create mode 100644 pac/atsamda1j/src/wdt/intenclr.rs create mode 100644 pac/atsamda1j/src/wdt/intenset.rs create mode 100644 pac/atsamda1j/src/wdt/intflag.rs create mode 100644 pac/atsamda1j/src/wdt/status.rs create mode 100644 svd/ATSAMDA1E14B.svd create mode 100644 svd/ATSAMDA1E15B.svd create mode 100644 svd/ATSAMDA1E16B.svd create mode 100644 svd/ATSAMDA1G14B.svd create mode 100644 svd/ATSAMDA1G15B.svd create mode 100644 svd/ATSAMDA1G16B.svd create mode 100644 svd/ATSAMDA1J14B.svd create mode 100644 svd/ATSAMDA1J15B.svd create mode 100644 svd/ATSAMDA1J16B.svd create mode 100644 svd/devices/atsamda1e14b.xsl create mode 100644 svd/devices/atsamda1e15b.xsl create mode 100644 svd/devices/atsamda1e16b.xsl create mode 100644 svd/devices/atsamda1g14b.xsl create mode 100644 svd/devices/atsamda1g15b.xsl create mode 100644 svd/devices/atsamda1g16b.xsl create mode 100644 svd/devices/atsamda1j14b.xsl create mode 100644 svd/devices/atsamda1j15b.xsl create mode 100644 svd/devices/atsamda1j16b.xsl create mode 100644 svd/devices/include/atsamda1.xsl diff --git a/hal/CHANGELOG.md b/hal/CHANGELOG.md index 5a29b43e820..d781d85d4f4 100644 --- a/hal/CHANGELOG.md +++ b/hal/CHANGELOG.md @@ -1,6 +1,7 @@ # Unreleased Changes - Add support for L-Variant of the SAMD21D +- Add support for the SAMDA1[EGJ] # v0.15.0 diff --git a/hal/Cargo.toml b/hal/Cargo.toml index 1ef47c7a476..446110ffb09 100644 --- a/hal/Cargo.toml +++ b/hal/Cargo.toml @@ -7,7 +7,7 @@ authors = [ "Michael van Niekerk ", "Jesse Braham ", ] -description = "HAL and Peripheral access API for ATSAMD11, ATSAMD21, ATSAMD51, ATSAME51, ATSAME53 and ATSAME54 microcontrollers" +description = "HAL and Peripheral access API for ATSAMD11, ATSAMD21/ATSAMDA1, ATSAMD51, ATSAME51, ATSAME53 and ATSAME54 microcontrollers" keywords = ["no-std", "arm", "cortex-m", "embedded-hal"] categories = ["embedded", "hardware-support", "no-std"] license = "MIT OR Apache-2.0" @@ -60,6 +60,21 @@ version = "1.0" # Each of the supported chips is listed as an optional dependency here. # This makes it available when the corresponding feature name is referenced. # We use a feature named "samdFOO" to pull in the dependency named "atsamdFOO" +[dependencies.atsamda1e] +path = "../pac/atsamda1e" +version = "0.12" +optional = true + +[dependencies.atsamda1g] +path = "../pac/atsamda1g" +version = "0.12" +optional = true + +[dependencies.atsamda1j] +path = "../pac/atsamda1j" +version = "0.12" +optional = true + [dependencies.atsamd11c] path = "../pac/atsamd11c" version = "0.12" @@ -165,6 +180,13 @@ device = [] # Bypasses compile-time checks that a specific device is enabled. library = [] +samda1 = ["device"] # Convenience feature for shared configuration of samda1 chips. +samda1e = ["atsamda1e", "samda1"] +samda1e-rt = ["samda1e", "atsamda1e/rt"] +samda1g = ["atsamda1g", "samda1"] +samda1g-rt = ["samda1g", "atsamda1g/rt"] +samda1j = ["atsamda1j", "samda1"] +samda1j-rt = ["samda1j", "atsamda1j/rt"] samd11 = ["device"] # Convenience feature for shared configuration of samd11 chips. samd11c = ["atsamd11c", "samd11"] samd11c-rt = ["samd11c", "atsamd11c/rt"] @@ -207,6 +229,8 @@ same54n = ["atsame54n", "same54", "min-samd51n"] same54n-rt = ["same54n", "atsame54n/rt"] same54p = ["atsame54p", "same54", "min-samd51p"] same54p-rt = ["same54p", "atsame54p/rt"] +min-samda1g = [] +min-samda1j = ["min-samda1g"] min-samd21g = [] min-samd21j = ["min-samd21g"] min-samd51g = [] diff --git a/hal/README.md b/hal/README.md index 46618b46fa9..828d7c87552 100644 --- a/hal/README.md +++ b/hal/README.md @@ -10,6 +10,9 @@ This crate provides a type-safe API for working with `samd11`, `samd21`, `samd51 ## Supported Devices +* `atsamda1e` (via the `samda1e` feature) [[pac]](https://github.com/atsamd-rs/atsamd/tree/master/pac/atsamda1e) +* `atsamda1g` (via the `samda1g` feature) [[pac]](https://github.com/atsamd-rs/atsamd/tree/master/pac/atsamda1g) +* `atsamda1j` (via the `samda1j` feature) [[pac]](https://github.com/atsamd-rs/atsamd/tree/master/pac/atsamda1j) * `atsamd11c` (via the `samd11c` feature) [[pac]](https://github.com/atsamd-rs/atsamd/tree/master/pac/atsamd11c) * `atsamd21e` (via the `samd21e` feature) [[pac]](https://github.com/atsamd-rs/atsamd/tree/master/pac/atsamd21e) * `atsamd21g` (via the `samd21g` feature) [[pac]](https://github.com/atsamd-rs/atsamd/tree/master/pac/atsamd21g) diff --git a/hal/src/dmac/channel/mod.rs b/hal/src/dmac/channel/mod.rs index 88a9d3be33d..2709a2148ca 100644 --- a/hal/src/dmac/channel/mod.rs +++ b/hal/src/dmac/channel/mod.rs @@ -8,7 +8,7 @@ //! requires setting a priority level, as well as enabling or disabling //! interrupt requests (only for the specific channel being initialized). #![cfg_attr( - not(any(feature = "samd11", feature = "samd21")), + not(any(feature = "samda1", feature = "samd11", feature = "samd21")), doc = "# Burst Length and FIFO Threshold (SAMD51/SAME5x only) The transfer burst length can be configured through the @@ -145,7 +145,7 @@ impl Channel { // Software reset the channel for good measure self._reset_private(); - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] // Setup priority level self.regs.chctrlb.modify(|_, w| w.lvl().bits(lvl as u8)); @@ -253,7 +253,7 @@ impl Channel { // SAFETY: This is actually safe because we are writing the correct enum value // (imported from the PAC) into the register unsafe { - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] self.regs.chctrlb.modify(|_, w| { w.trigsrc().bits(trig_src as u8); w.trigact().bits(trig_act as u8) diff --git a/hal/src/dmac/channel/reg.rs b/hal/src/dmac/channel/reg.rs index 78ce37fa0c9..23b8fa6b0b6 100644 --- a/hal/src/dmac/channel/reg.rs +++ b/hal/src/dmac/channel/reg.rs @@ -24,7 +24,7 @@ use crate::pac::{ Peripherals, DMAC, }; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] use pac::dmac as channel_regs; #[cfg(feature = "min-samd51g")] @@ -56,7 +56,7 @@ pub(super) trait Register { /// the CHID register, then access the channel control registers. /// If an interrupt were to change the CHID register and not reset it /// to the expected value, we would be faced with undefined behaviour. - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[inline] fn with_chid R, R>(&mut self, fun: F) -> R { // SAFETY: This method is ONLY safe if the individual channels are GUARANTEED diff --git a/hal/src/dmac/dma_controller.rs b/hal/src/dmac/dma_controller.rs index e5814d7d871..a60c1466345 100644 --- a/hal/src/dmac/dma_controller.rs +++ b/hal/src/dmac/dma_controller.rs @@ -22,7 +22,7 @@ use modular_bitfield::prelude::*; use seq_macro::seq; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub use crate::pac::dmac::chctrlb::{ LVL_A as PriorityLevel, TRIGACT_A as TriggerAction, TRIGSRC_A as TriggerSource, }; @@ -134,7 +134,7 @@ impl DmaController { #[inline] pub fn init(mut dmac: DMAC, _pm: &mut PM) -> Self { // ----- Initialize clocking ----- // - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] { // Enable clocking _pm.ahbmask.modify(|_, w| w.dmac_().set_bit()); @@ -230,7 +230,7 @@ impl DmaController { Self::swreset(&mut self.dmac); - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] { // Disable the DMAC clocking _pm.apbbmask.modify(|_, w| w.dmac_().clear_bit()); diff --git a/hal/src/dmac/mod.rs b/hal/src/dmac/mod.rs index ed808f5dabf..7545aa92b75 100644 --- a/hal/src/dmac/mod.rs +++ b/hal/src/dmac/mod.rs @@ -284,7 +284,7 @@ macro_rules! with_num_channels { }; } -#[cfg(all(feature = "samd21", feature = "max-channels"))] +#[cfg(all(any(feature = "samda1", feature = "samd21"), feature = "max-channels"))] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { @@ -308,7 +308,7 @@ macro_rules! with_num_channels { }; } -#[cfg(all(feature = "samd21", not(feature = "max-channels")))] +#[cfg(all(any(feature = "samda1", feature = "samd21"), not(feature = "max-channels")))] #[macro_export] macro_rules! with_num_channels { ($some_macro:ident) => { diff --git a/hal/src/gpio/dynpin.rs b/hal/src/gpio/dynpin.rs index 18ca9ceb0b1..79b4f59d505 100644 --- a/hal/src/gpio/dynpin.rs +++ b/hal/src/gpio/dynpin.rs @@ -112,7 +112,7 @@ pub enum DynAlternate { E, F, G, - #[cfg(any(feature = "samd21", feature = "min-samd51g"))] + #[cfg(any(feature = "samda1", feature = "samd21", feature = "min-samd51g"))] H, #[cfg(feature = "min-samd51g")] I, @@ -184,7 +184,7 @@ macro_rules! dyn_alternate { } dyn_alternate!(B, C, D, E, F, G); -#[cfg(any(feature = "samd21", feature = "min-samd51g"))] +#[cfg(any(feature = "samda1", feature = "samd21", feature = "min-samd51g"))] dyn_alternate!(H); #[cfg(feature = "min-samd51g")] dyn_alternate!(I, J, K, L, M, N); @@ -197,7 +197,7 @@ dyn_alternate!(I, J, K, L, M, N); #[derive(PartialEq, Clone, Copy)] pub enum DynGroup { A, - #[cfg(any(feature = "samd21", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "samd21", feature = "min-samd51g"))] B, #[cfg(feature = "min-samd51n")] C, diff --git a/hal/src/gpio/pin.rs b/hal/src/gpio/pin.rs index 4601b4d83b4..f29a5f4f2c4 100644 --- a/hal/src/gpio/pin.rs +++ b/hal/src/gpio/pin.rs @@ -341,7 +341,7 @@ macro_rules! alternate { alternate!(B, C, D, E, F, G); -#[cfg(any(feature = "samd21", feature = "min-samd51g"))] +#[cfg(any(feature = "samda1", feature = "samd21", feature = "min-samd51g"))] alternate!(H); #[cfg(feature = "min-samd51g")] @@ -749,7 +749,7 @@ impl_core_convert_from!( AlternateE, AlternateF, AlternateG, - #[cfg(any(feature = "samd21", feature = "min-samd51g"))] + #[cfg(any(feature = "samda1", feature = "samd21", feature = "min-samd51g"))] AlternateH, #[cfg(feature = "min-samd51g")] AlternateI, @@ -1084,9 +1084,9 @@ declare_pins!( (PA10, 10), #[cfg(not(feature = "samd11"))] (PA11, 11), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] (PA12, 12), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] (PA13, 13), (PA14, 14), (PA15, 15), @@ -1098,9 +1098,9 @@ declare_pins!( (PA18, 18), #[cfg(not(feature = "samd11"))] (PA19, 19), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] (PA20, 20), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] (PA21, 21), #[cfg(not(feature = "samd11c"))] (PA22, 22), @@ -1110,47 +1110,47 @@ declare_pins!( (PA25, 25), #[cfg(not(feature = "samd11"))] (PA27, 27), - #[cfg(all(any(feature = "samd11", feature = "samd21"), not(feature = "samd21el")))] + #[cfg(all(any(feature = "samda1", feature = "samd11", feature = "samd21"), not(feature = "samd21el")))] (PA28, 28), (PA30, 30), (PA31, 31), } B { - #[cfg(any(feature = "min-samd21j", feature = "samd21gl", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "samd21gl", feature = "min-samd51j"))] (PB00, 00), - #[cfg(any(feature = "min-samd21j", feature = "samd21gl", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "samd21gl", feature = "min-samd51j"))] (PB01, 01), - #[cfg(any(feature = "min-samd21g", feature = "samd21el", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "samd21el", feature = "min-samd51g"))] (PB02, 02), - #[cfg(any(feature = "min-samd21g", feature = "samd21el", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "samd21el", feature = "min-samd51g"))] (PB03, 03), - #[cfg(any(feature = "min-samd21j", feature = "samd21el", feature = "samd21gl", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "samd21el", feature = "samd21gl", feature = "min-samd51j"))] (PB04, 04), - #[cfg(any(feature = "min-samd21j", feature = "samd21el", feature = "samd21gl", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "samd21el", feature = "samd21gl", feature = "min-samd51j"))] (PB05, 05), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB06, 06), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB07, 07), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21g", feature = "min-samd51g"))] (PB08, 08), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] (PB09, 09), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] (PB10, 10), - #[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] (PB11, 11), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB12, 12), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB13, 13), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB14, 14), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB15, 15), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB16, 16), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB17, 17), #[cfg(feature = "min-samd51n")] (PB18, 18), @@ -1160,9 +1160,9 @@ declare_pins!( (PB20, 20), #[cfg(feature = "min-samd51n")] (PB21, 21), - #[cfg(all(any(feature = "min-samd21g", feature = "min-samd51g"), not(feature = "samd21gl")))] + #[cfg(all(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"), not(feature = "samd21gl")))] (PB22, 22), - #[cfg(all(any(feature = "min-samd21g", feature = "min-samd51g"), not(feature = "samd21gl")))] + #[cfg(all(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"), not(feature = "samd21gl")))] (PB23, 23), #[cfg(feature = "min-samd51n")] (PB24, 24), @@ -1176,9 +1176,9 @@ declare_pins!( (PB28, 28), #[cfg(feature = "min-samd51p")] (PB29, 29), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB30, 30), - #[cfg(any(feature = "min-samd21j", feature = "min-samd51j"))] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j", feature = "min-samd51j"))] (PB31, 31), } C { diff --git a/hal/src/gpio/reg.rs b/hal/src/gpio/reg.rs index 1211d0f213e..60e06404453 100644 --- a/hal/src/gpio/reg.rs +++ b/hal/src/gpio/reg.rs @@ -4,7 +4,7 @@ use crate::pac::port::{ PMUX0_ as PMUX, WRCONFIG, }; -#[cfg(feature = "min-samd51g")] +#[cfg(any(feature = "samda1", feature = "min-samd51g"))] use crate::pac::port::group::{ CTRL, DIR, DIRCLR, DIRSET, DIRTGL, IN, OUT, OUTCLR, OUTSET, OUTTGL, PINCFG, PMUX, WRCONFIG, }; @@ -122,7 +122,7 @@ impl From for ModeFields { G => { fields.pmux = 6; } - #[cfg(any(feature = "samd21", feature = "min-samd51g"))] + #[cfg(any(feature = "samda1", feature = "samd21", feature = "min-samd51g"))] H => { fields.pmux = 7; } @@ -163,8 +163,8 @@ impl From for ModeFields { /// Represent the [`PORT`] register block /// -/// The SAMx5x PACs have a GROUP type to represent each [`PORT`] group, but the -/// SAMD11 and SAMD21 PACs do not. Manually re-implement it here. +/// The SAMx5x and SAMDA1 PACs have a GROUP type to represent each [`PORT`] group, +/// but the SAMD11 and SAMD21 PACs do not. Manually re-implement it here. #[repr(C)] #[allow(clippy::upper_case_acronyms)] pub(super) struct GROUP { @@ -231,7 +231,7 @@ pub(super) unsafe trait RegisterInterface { fn group(&self) -> &GROUP { let offset = match self.id().group { DynGroup::A => 0, - #[cfg(any(feature = "samd21", feature = "min-samd51g"))] + #[cfg(any(feature = "min-samda1g", feature = "samd21", feature = "min-samd51g"))] DynGroup::B => 1, #[cfg(feature = "min-samd51n")] DynGroup::C => 2, diff --git a/hal/src/lib.rs b/hal/src/lib.rs index 7bc015994b3..919ae762541 100644 --- a/hal/src/lib.rs +++ b/hal/src/lib.rs @@ -13,6 +13,15 @@ compile_error!( specifying the `library` feature" ); +#[cfg(feature = "samda1e")] +pub use atsamda1e as pac; + +#[cfg(feature = "samda1g")] +pub use atsamda1g as pac; + +#[cfg(feature = "samda1j")] +pub use atsamda1j as pac; + #[cfg(feature = "samd11c")] pub use atsamd11c as pac; @@ -105,13 +114,13 @@ compile_error!("'usb' is enabled, but USB isn't supported on SAMD11"); #[cfg(all( feature = "usb", - not(any(feature = "samd21", feature = "min-samd51g", feature = "library")) + not(any(feature = "samda1", feature = "samd21", feature = "min-samd51g", feature = "library")) ))] compile_error!("The 'usb' feature is enabled, but not a chip with USB support"); -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub mod thumbv6m; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub use crate::thumbv6m::*; #[cfg(feature = "min-samd51g")] diff --git a/hal/src/rtc.rs b/hal/src/rtc.rs index 93f4609fe12..94ce4e20e88 100644 --- a/hal/src/rtc.rs +++ b/hal/src/rtc.rs @@ -27,8 +27,8 @@ use crate::pac::{ rtc::mode2::CTRLA as MODE2_CTRLA, MCLK as PM, }; -// SAMD11/SAMD21 imports -#[cfg(any(feature = "samd11", feature = "samd21"))] +// SAMD11/SAMD21/SAMDA1 imports +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] use crate::pac::{ rtc::mode0::ctrl::PRESCALER_A, rtc::mode0::CTRL as MODE0_CTRLA, rtc::mode2::CTRL as MODE2_CTRLA, PM, @@ -114,7 +114,7 @@ impl Rtc { fn mode0_ctrla(&self) -> &MODE0_CTRLA { #[cfg(feature = "min-samd51g")] return &self.mode0().ctrla; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] return &self.mode0().ctrl; } @@ -122,7 +122,7 @@ impl Rtc { fn mode2_ctrla(&self) -> &MODE2_CTRLA { #[cfg(feature = "min-samd51g")] return &self.mode2().ctrla; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] return &self.mode2().ctrl; } @@ -130,7 +130,7 @@ impl Rtc { fn sync(&self) { #[cfg(feature = "min-samd51g")] while self.mode2().syncbusy.read().bits() != 0 {} - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] while self.mode2().status.read().syncbusy().bit_is_set() {} } @@ -244,8 +244,8 @@ impl Rtc { /// Returns the internal counter value. #[inline] pub fn count32(&self) -> u32 { - // synchronize this read on SAMD11/21. SAMx5x is automatically synchronized - #[cfg(any(feature = "samd11", feature = "samd21"))] + // synchronize this read on SAMD11/21/A1. SAMx5x is automatically synchronized + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] { self.mode0().readreq.modify(|_, w| w.rcont().set_bit()); self.sync(); @@ -306,8 +306,8 @@ impl Rtc { /// Returns the current clock/calendar value. pub fn current_time(&self) -> Datetime { - // synchronize this read on SAMD11/21. SAMx5x is automatically synchronized - #[cfg(any(feature = "samd11", feature = "samd21"))] + // synchronize this read on SAMD11/21/A1. SAMx5x is automatically synchronized + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] { self.mode2().readreq.modify(|_, w| w.rcont().set_bit()); self.sync(); @@ -358,7 +358,10 @@ impl CountDown for Rtc { while self.mode0_ctrla().read().swrst().bit_is_set() {} // set cycles to compare to... + #[cfg(not(feature = "samda1"))] self.mode0().comp[0].write(|w| unsafe { w.comp().bits(cycles) }); + #[cfg(feature = "samda1")] + self.mode0().comp.write(|w| unsafe { w.comp().bits(cycles) }); self.mode0_ctrla().modify(|_, w| { // set clock divider... w.prescaler().variant(divider); diff --git a/hal/src/sercom/dma.rs b/hal/src/sercom/dma.rs index f742fdf7fd7..3c15e7e9c0d 100644 --- a/hal/src/sercom/dma.rs +++ b/hal/src/sercom/dma.rs @@ -100,7 +100,7 @@ impl I2c { #[cfg(feature = "min-samd51g")] let trigger_action = TriggerAction::BURST; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -148,7 +148,7 @@ impl I2c { #[cfg(feature = "min-samd51g")] let trigger_action = TriggerAction::BURST; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -224,7 +224,7 @@ where #[cfg(feature = "min-samd51g")] let trigger_action = TriggerAction::BURST; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -262,7 +262,7 @@ where #[cfg(feature = "min-samd51g")] let trigger_action = TriggerAction::BURST; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -330,7 +330,7 @@ where #[cfg(feature = "min-samd51g")] let trigger_action = TriggerAction::BURST; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check @@ -368,7 +368,7 @@ where #[cfg(feature = "min-samd51g")] let trigger_action = TriggerAction::BURST; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] let trigger_action = TriggerAction::BEAT; // SAFETY: This is safe because the of the `'static` bound check diff --git a/hal/src/sercom/i2c.rs b/hal/src/sercom/i2c.rs index 19d27cd0c02..be469632b78 100644 --- a/hal/src/sercom/i2c.rs +++ b/hal/src/sercom/i2c.rs @@ -255,7 +255,7 @@ fn i2c_send_with_dma>(i2c: I2c, c " )] -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[path = "i2c/pads_thumbv6m.rs"] mod pads; diff --git a/hal/src/sercom/i2c/pads_thumbv6m.rs b/hal/src/sercom/i2c/pads_thumbv6m.rs index 7bd11070c3a..61934a47afa 100644 --- a/hal/src/sercom/i2c/pads_thumbv6m.rs +++ b/hal/src/sercom/i2c/pads_thumbv6m.rs @@ -136,7 +136,7 @@ pub type PadsFromIds = Pads, Pad /// /// [`Pin`]: crate::gpio::Pin /// [`PinId`]: crate::gpio::PinId -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] pub type PadsFromIds = Pads, Pad>; //============================================================================= diff --git a/hal/src/sercom/mod.rs b/hal/src/sercom/mod.rs index eb16b808062..c0967b6fea8 100644 --- a/hal/src/sercom/mod.rs +++ b/hal/src/sercom/mod.rs @@ -40,13 +40,13 @@ use crate::pac; #[cfg(feature = "min-samd51g")] use pac::MCLK as APB_CLK_CTRL; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] use pac::PM as APB_CLK_CTRL; use pac::{sercom0, SERCOM0, SERCOM1}; -#[cfg(any(feature = "samd21", feature = "min-samd51g"))] +#[cfg(any(feature = "samda1", feature = "samd21", feature = "min-samd51g"))] use pac::{SERCOM2, SERCOM3}; -#[cfg(any(feature = "min-samd21g", feature = "min-samd51g"))] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g", feature = "min-samd51g"))] use pac::{SERCOM4, SERCOM5}; #[cfg(feature = "min-samd51n")] use pac::{SERCOM6, SERCOM7}; @@ -108,11 +108,11 @@ macro_rules! sercom { }; } -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] sercom!(apbcmask: (0, 1)); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] sercom!(apbcmask: (2, 3)); -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] sercom!(apbcmask: (4, 5)); #[cfg(feature = "min-samd51g")] diff --git a/hal/src/sercom/pad.rs b/hal/src/sercom/pad.rs index 6909a11467e..7d86c12134c 100644 --- a/hal/src/sercom/pad.rs +++ b/hal/src/sercom/pad.rs @@ -48,7 +48,7 @@ use crate::gpio::OptionalPinId; use crate::gpio::{AnyPin, OptionalPin, Pin, PinId, PinMode}; use crate::typelevel::{NoneT, Sealed}; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[path = "pad/impl_pad_thumbv6m.rs"] mod impl_pad; diff --git a/hal/src/sercom/pad/impl_pad_thumbv6m.rs b/hal/src/sercom/pad/impl_pad_thumbv6m.rs index b8af601bac1..35915ae58d9 100644 --- a/hal/src/sercom/pad/impl_pad_thumbv6m.rs +++ b/hal/src/sercom/pad/impl_pad_thumbv6m.rs @@ -42,7 +42,7 @@ macro_rules! pad_info { type PinMode = Alternate<$Cfg>; } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] impl GetPad<$Sercom> for $PinId { type PadNum = $PadNum; type PinMode = Alternate<$Cfg>; @@ -111,11 +111,11 @@ macro_rules! pad_table { } pad_table!( - #[cfg(all(feature = "samd21",not(any(feature = "samd21el", feature = "samd21gl"))))] + #[cfg(all(any(feature = "samda1", feature = "samd21"),not(any(feature = "samd21el", feature = "samd21gl"))))] PA00 { D: (Sercom1, Pad0), } - #[cfg(all(feature = "samd21",not(any(feature = "samd21el", feature = "samd21gl"))))] + #[cfg(all(any(feature = "samda1", feature = "samd21"),not(any(feature = "samd21el", feature = "samd21gl"))))] PA01 { D: (Sercom1, Pad1), } @@ -129,11 +129,11 @@ pad_table!( C: (Sercom0, Pad3), D: (Sercom0, Pad1), } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA06 { D: (Sercom0, Pad2), } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA07 { D: (Sercom0, Pad3), } @@ -142,9 +142,9 @@ pad_table!( C: (Sercom1, Pad2), #[cfg(feature = "samd11")] D: (Sercom0, Pad2), - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom0, Pad0) + I2C, - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] D: (Sercom2, Pad0) + I2C, } PA09 { @@ -152,27 +152,27 @@ pad_table!( C: (Sercom1, Pad3), #[cfg(feature = "samd11")] D: (Sercom0, Pad3), - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom0, Pad1) + I2C, - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] D: (Sercom2, Pad1) + I2C, } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA10 { C: (Sercom0, Pad2), D: (Sercom2, Pad2), } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA11 { C: (Sercom0, Pad3), D: (Sercom2, Pad3), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA12 { C: (Sercom2, Pad0) + I2C, D: (Sercom4, Pad0) + I2C, } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA13 { C: (Sercom2, Pad1) + I2C, D: (Sercom4, Pad1) + I2C, @@ -180,75 +180,75 @@ pad_table!( PA14 { #[cfg(feature = "samd11")] C: (Sercom0, Pad0) + I2C, - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom2, Pad2), - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] D: (Sercom4, Pad2), } PA15 { #[cfg(feature = "samd11")] C: (Sercom0, Pad1) + I2C, - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom2, Pad3), - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] D: (Sercom4, Pad3), } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA16 { C: (Sercom1, Pad0) + I2C, D: (Sercom3, Pad0) + I2C, } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA17 { C: (Sercom1, Pad1) + I2C, D: (Sercom3, Pad1) + I2C, } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA18 { C: (Sercom1, Pad2), D: (Sercom3, Pad2), } - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] PA19 { C: (Sercom1, Pad3), D: (Sercom3, Pad3), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA20 { C: (Sercom5, Pad2), D: (Sercom3, Pad2), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA21 { C: (Sercom5, Pad3), D: (Sercom3, Pad3), } PA22 { - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom3, Pad0) + I2C, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] D: (Sercom5, Pad0) + I2C, } PA23 { - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom3, Pad1) + I2C, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] D: (Sercom5, Pad1) + I2C, } PA24 { #[cfg(feature = "samd11")] C: (Sercom1, Pad2), - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom3, Pad2), - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] D: (Sercom5, Pad2), } PA25 { #[cfg(feature = "samd11")] C: (Sercom1, Pad3), - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] C: (Sercom3, Pad3), - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] D: (Sercom5, Pad3), } PA30 { @@ -261,75 +261,75 @@ pad_table!( C: (Sercom1, Pad1), D: (Sercom1, Pad3), } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB00 { D: (Sercom5, Pad2), } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB01 { D: (Sercom5, Pad3), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB02 { D: (Sercom5, Pad0), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB03 { D: (Sercom5, Pad1), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB08 { D: (Sercom4, Pad0), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB09 { D: (Sercom4, Pad1), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB10 { D: (Sercom4, Pad2), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB11 { D: (Sercom4, Pad3), } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB12 { C: (Sercom4, Pad0) + I2C, } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB13 { C: (Sercom4, Pad1) + I2C, } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB14 { C: (Sercom4, Pad2), } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB15 { C: (Sercom4, Pad3), } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB16 { C: (Sercom5, Pad0) + I2C, } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB17 { C: (Sercom5, Pad1) + I2C, } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB22 { D: (Sercom5, Pad2), } - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB23 { D: (Sercom5, Pad3), } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB30 { D: (Sercom5, Pad0) + I2C, } - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB31 { D: (Sercom5, Pad1) + I2C, } diff --git a/hal/src/sercom/spi.rs b/hal/src/sercom/spi.rs index c54c4571c36..2f991e6f816 100644 --- a/hal/src/sercom/spi.rs +++ b/hal/src/sercom/spi.rs @@ -14,7 +14,7 @@ //! An SPI peripheral can use up to four [`Pin`]s as [`Sercom`] pads. However, //! only certain `Pin` combinations are acceptable. All `Pin`s must be mapped to //! the same `Sercom`, and for SAMx5x chips, they must also belong to the same -#![cfg_attr(any(feature = "samd11", feature = "samd21"), doc = "`IoSet`.")] +#![cfg_attr(any(feature = "samda1", feature = "samd11", feature = "samd21"), doc = "`IoSet`.")] #![cfg_attr(feature = "min-samd51g", doc = "[`IoSet`].")] //! This HAL makes it impossible to use invalid `Pin` combinations, and the //! [`Pads`] struct is responsible for enforcing these constraints. @@ -65,7 +65,7 @@ use atsamd_hal::typelevel::NoneT; // SAMx5x-specific imports use atsamd_hal::sercom::pad::IoSet1; -// SAMD21 version +// SAMD21/SAMDA1 version type Pads = spi::PadsFromIds; // SAMx5x version type Pads = spi::PadsFromIds; @@ -116,7 +116,7 @@ type Pads = spi::PadsFromIds; //! [`Size`] type that varies by chip. [`Size`] essentially acts as a trait //! alias. On SAMD11 and SAMD21 chips, it represents the #![cfg_attr( - any(feature = "samd11", feature = "samd21"), + any(feature = "samda1", feature = "samd11", feature = "samd21"), doc = "[`CharSize`], which can either be [`EightBit`] or [`NineBit`]. " )] #![cfg_attr( @@ -124,11 +124,11 @@ type Pads = spi::PadsFromIds; doc = "`CharSize`, which can either be `EightBit` or `NineBit`. " )] //! While on SAMx5x chips, it represents the transaction -#![cfg_attr(any(feature = "samd11", feature = "samd21"), doc = "`Length`")] +#![cfg_attr(any(feature = "samda1", feature = "samd11", feature = "samd21"), doc = "`Length`")] #![cfg_attr(feature = "min-samd51g", doc = "[`Length`]")] //! in bytes, using type-level numbers provided by the [`typenum`] crate. Valid //! transaction lengths, from `U1` to `U255`, are re-exported in the -#![cfg_attr(any(feature = "samd11", feature = "samd21"), doc = "`lengths`")] +#![cfg_attr(any(feature = "samda1", feature = "samd11", feature = "samd21"), doc = "`lengths`")] #![cfg_attr(feature = "min-samd51g", doc = "[`lengths`]")] //! sub-module. //! @@ -332,10 +332,10 @@ use reg::Registers; #[cfg(any(feature = "samd11", feature = "samd21"))] use crate::pac::sercom0::spi::ctrla::MODE_A; -#[cfg(feature = "min-samd51g")] +#[cfg(any(feature = "samda1", feature = "min-samd51g"))] use crate::pac::sercom0::spim::ctrla::MODE_A; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[path = "spi/pads_thumbv6m.rs"] mod pads; @@ -345,7 +345,7 @@ mod pads; pub use pads::*; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[path = "spi/char_size.rs"] mod size; @@ -363,7 +363,7 @@ pub mod lengths { }); } -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[path = "spi/impl_ehal_thumbv6m.rs"] pub mod impl_ehal; @@ -511,7 +511,7 @@ impl MasterMode for MasterHWSS {} //============================================================================= /// Type alias for the width of the `DATA` register -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub type DataWidth = u16; /// Type alias for the width of the `DATA` register @@ -520,15 +520,15 @@ pub type DataWidth = u32; /// Trait alias whose definition varies by chip /// -/// On SAMD11 and SAMD21 chips, this represents the [`CharSize`]. -#[cfg(any(feature = "samd11", feature = "samd21"))] +/// On SAMD11 and SAMD21/SAMDA1 chips, this represents the [`CharSize`]. +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub trait Size: CharSize {} -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] impl Size for C {} /// Type alias for the default [`Size`] type, which varies by chip -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub type DefaultSize = EightBit; /// Trait alias whose definition varies by chip @@ -552,7 +552,7 @@ pub type DefaultSize = typenum::U1; /// read or write of the `DATA` register pub trait AtomicSize: Size {} -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] impl AtomicSize for C {} #[cfg(feature = "min-samd51g")] @@ -654,7 +654,7 @@ impl Config

{ regs.reset(); regs.set_op_mode(Master::MODE, Master::MSSEN); regs.set_dipo_dopo(P::DIPO_DOPO); - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] regs.set_char_size(EightBit::BITS); #[cfg(feature = "min-samd51g")] regs.set_length(1); @@ -674,12 +674,12 @@ impl Config

{ /// configuration. The default [`OpMode`] is [`Master`], while the default /// [`Size`] is an #[cfg_attr( - any(feature = "samd11", feature = "samd21"), + any(feature = "samda1", feature = "samd11", feature = "samd21"), doc = "[`EightBit`] [`CharSize`]" )] #[cfg_attr(feature = "min-samd51g", doc = "`EightBit` `CharSize`")] - /// for SAMD11 and SAMD21 chips or a - #[cfg_attr(any(feature = "samd11", feature = "samd21"), doc = "`Length` of `U1`")] + /// for SAMD11 and SAMD21/SAMDA1 chips or a + #[cfg_attr(any(feature = "samda1", feature = "samd11", feature = "samd21"), doc = "`Length` of `U1`")] #[cfg_attr(feature = "min-samd51g", doc = "[`Length`] of `U1`")] /// for SAMx5x chips. Note that [`Config`] takes ownership of both the /// PAC [`Sercom`] struct as well as the [`Pads`]. @@ -759,7 +759,7 @@ where } /// Change the [`CharSize`] using the builder pattern - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[inline] pub fn char_size(mut self) -> Config { self.regs.set_char_size(C2::BITS); diff --git a/hal/src/sercom/spi/char_size.rs b/hal/src/sercom/spi/char_size.rs index 19945a6d446..73d9f11c1d7 100644 --- a/hal/src/sercom/spi/char_size.rs +++ b/hal/src/sercom/spi/char_size.rs @@ -1,5 +1,5 @@ //! Define a trait to track the [`CharSize`], which represents the [`Config`] -//! [`Size`] for SAMD11 and SAMD21 chips +//! [`Size`] for SAMD11 and SAMD21/SAMDA1 chips //! //! [`Config`]: super::Config //! [`Size`]: super::Size diff --git a/hal/src/sercom/spi/impl_ehal_thumbv6m.rs b/hal/src/sercom/spi/impl_ehal_thumbv6m.rs index ebf502ac5fc..4ac4773224d 100644 --- a/hal/src/sercom/spi/impl_ehal_thumbv6m.rs +++ b/hal/src/sercom/spi/impl_ehal_thumbv6m.rs @@ -8,7 +8,7 @@ //! //! # Variations by [`Size`] //! -//! SAMD11 and SAMD21 chips do not have 32-bit extension mode, so their +//! SAMD11 and SAMD21/SAMDA1 chips do not have 32-bit extension mode, so their //! transaction `Size` can only vary by the [`CharSize`]. Both options, //! [`EightBit`] and [`NineBit`], are [`AtomicSize`]s, because each can be //! completed with a single read/write of the `DATA` register. Consequently, diff --git a/hal/src/sercom/spi/pads_thumbv6m.rs b/hal/src/sercom/spi/pads_thumbv6m.rs index 3db30a72770..f181b8b9454 100644 --- a/hal/src/sercom/spi/pads_thumbv6m.rs +++ b/hal/src/sercom/spi/pads_thumbv6m.rs @@ -5,7 +5,7 @@ use core::marker::PhantomData; -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] use crate::gpio::AnyPin; use crate::sercom::*; use crate::typelevel::{NoneT, Sealed}; @@ -284,7 +284,7 @@ where } } -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] impl Pads where S: Sercom, @@ -404,7 +404,7 @@ where /// [`Pin`]: crate::gpio::Pin /// [`PinId`]: crate::gpio::PinId /// [`OptionalPinId`]: crate::gpio::OptionalPinId -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] pub type PadsFromIds = Pads< S, >::Pad, diff --git a/hal/src/sercom/spi/reg.rs b/hal/src/sercom/spi/reg.rs index 5a21ee8b2db..7faf1ceeb3d 100644 --- a/hal/src/sercom/spi/reg.rs +++ b/hal/src/sercom/spi/reg.rs @@ -4,12 +4,12 @@ use embedded_hal::spi; #[cfg(any(feature = "samd11", feature = "samd21"))] use crate::pac::sercom0::SPI; -#[cfg(feature = "min-samd51g")] +#[cfg(any(feature = "samda1", feature = "min-samd51g"))] use crate::pac::sercom0::SPIM; #[cfg(any(feature = "samd11", feature = "samd21"))] use crate::pac::sercom0::spi::ctrla::MODE_A; -#[cfg(feature = "min-samd51g")] +#[cfg(any(feature = "samda1", feature = "min-samd51g"))] use crate::pac::sercom0::spim::ctrla::MODE_A; use crate::sercom::Sercom; @@ -42,7 +42,7 @@ impl Registers { self.sercom.spi() } - #[cfg(feature = "min-samd51g")] + #[cfg(any(feature = "samda1", feature = "min-samd51g"))] #[inline] pub fn spi(&self) -> &SPIM { self.sercom.spim() @@ -65,10 +65,16 @@ impl Registers { #[inline] pub fn set_dipo_dopo(&mut self, dipo_dopo: (u8, u8)) { let (dipo, dopo) = dipo_dopo; + #[cfg(not(feature = "samda1"))] self.spi().ctrla.modify(|_, w| unsafe { w.dipo().bits(dipo); w.dopo().bits(dopo) }); + #[cfg(feature = "samda1")] + self.spi().ctrla.modify(|_, w| { + w.dipo().bits(dipo); + w.dopo().bits(dopo) + }); } /// Configure the SPI operating mode @@ -109,7 +115,7 @@ impl Registers { } /// Set the character size - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[inline] pub fn set_char_size(&mut self, bits: u8) { self.spi() diff --git a/hal/src/sercom/spi_future.rs b/hal/src/sercom/spi_future.rs index 213e17d0cb3..300060ba57d 100644 --- a/hal/src/sercom/spi_future.rs +++ b/hal/src/sercom/spi_future.rs @@ -190,10 +190,10 @@ use { typenum::Unsigned, }; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] use core::mem::size_of; -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] type Data = u16; #[cfg(feature = "min-samd51g")] @@ -212,7 +212,7 @@ pub trait CheckBufLen: AnySpi { /// This value is zero for an [`Spi`] with [`DynLength`] const LEN: usize = ::USIZE; - #[cfg(any(feature = "samd11", feature = "samd21"))] + #[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] /// [`Spi`] transaction length /// /// [`Spi`]: super::spi::Spi @@ -267,7 +267,7 @@ pub trait CheckBufLen: AnySpi { } } -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] impl CheckBufLen for S {} #[cfg(feature = "min-samd51g")] diff --git a/hal/src/sercom/uart.rs b/hal/src/sercom/uart.rs index 4d6bc133aa1..d3d39aba5be 100644 --- a/hal/src/sercom/uart.rs +++ b/hal/src/sercom/uart.rs @@ -387,7 +387,7 @@ let (chan1, rx, rx_buffer) = rx_dma.wait(); " )] -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] #[path = "uart/pads_thumbv6m.rs"] mod pads; @@ -416,7 +416,7 @@ use core::{convert::TryInto, marker::PhantomData}; use num_traits::AsPrimitive; /// Size of the SERCOM's `DATA` register -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub type DataReg = u16; /// Size of the SERCOM's `DATA` register diff --git a/hal/src/sercom/uart/config.rs b/hal/src/sercom/uart/config.rs index 9e6bc50bc16..b13ac8aef24 100644 --- a/hal/src/sercom/uart/config.rs +++ b/hal/src/sercom/uart/config.rs @@ -50,7 +50,7 @@ where /// Clock type needed to create a new [`Config`]. [`PM`](pac::PM) for thumbv6m /// targets. -#[cfg(any(feature = "samd11", feature = "samd21"))] +#[cfg(any(feature = "samda1", feature = "samd11", feature = "samd21"))] pub type Clock = pac::PM; /// Clock type needed to create a new [`Config`]. [`MCLK`](pac::MCLK) for diff --git a/hal/src/sercom/uart/pads_thumbv6m.rs b/hal/src/sercom/uart/pads_thumbv6m.rs index 4fd2ca42d5d..0b8dd97c6be 100644 --- a/hal/src/sercom/uart/pads_thumbv6m.rs +++ b/hal/src/sercom/uart/pads_thumbv6m.rs @@ -264,7 +264,7 @@ where } } -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] impl Pads where S: Sercom, @@ -367,7 +367,7 @@ where /// [`PinId`]: crate::gpio::PinId /// [`OptionalPinId`]: crate::gpio::OptionalPinId -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] pub type PadsFromIds = Pads< S, >::Pad, diff --git a/hal/src/sercom/uart/reg.rs b/hal/src/sercom/uart/reg.rs index 2abdb9b5595..328a3dce61a 100644 --- a/hal/src/sercom/uart/reg.rs +++ b/hal/src/sercom/uart/reg.rs @@ -8,7 +8,7 @@ use crate::sercom::*; #[cfg(any(feature = "samd11", feature = "samd21"))] use pac::sercom0::usart::ctrla::MODE_A; -#[cfg(feature = "min-samd51g")] +#[cfg(any(feature = "samda1", feature = "min-samd51g"))] use pac::sercom0::usart_int::ctrla::MODE_A; use crate::time::Hertz; @@ -37,7 +37,7 @@ impl Registers { /// Helper function to access the underlying `USART_INT` from the given /// `SERCOM` - #[cfg(feature = "min-samd51g")] + #[cfg(any(feature = "samda1", feature = "min-samd51g"))] #[inline] fn usart(&self) -> &pac::sercom0::USART_INT { self.sercom.usart_int() diff --git a/hal/src/thumbv6m/adc.rs b/hal/src/thumbv6m/adc.rs index 21072c97cc2..ac5bd319f6e 100644 --- a/hal/src/thumbv6m/adc.rs +++ b/hal/src/thumbv6m/adc.rs @@ -186,7 +186,7 @@ adc_pins! { PA15: 7 } -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] adc_pins! { PA02: 0, PA03: 1, @@ -200,7 +200,7 @@ adc_pins! { PA11: 19 } -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] adc_pins! { PB02: 10, PB03: 11, @@ -208,7 +208,7 @@ adc_pins! { PB09: 3 } -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] adc_pins! { PB00: 8, PB01: 9, diff --git a/hal/src/thumbv6m/calibration.rs b/hal/src/thumbv6m/calibration.rs index fb4228206c4..24f7657dc36 100644 --- a/hal/src/thumbv6m/calibration.rs +++ b/hal/src/thumbv6m/calibration.rs @@ -58,4 +58,9 @@ pub fn usb_trim_cal() -> u8 { return cal_with_errata(4, 23, 7, 7, 5) as u8; #[cfg(feature = "samd21")] return cal_with_errata(4, 23, 7, 7, 3) as u8; + // 2022-08-30 RMM: I couldn't find the errata in the SAMD21/DA1 that explains the previous + // case, but since the DA1 seems to be very close to identical to the D21 I've brought it + // over + #[cfg(feature = "samda1")] + return cal_with_errata(4, 23, 7, 7, 3) as u8; } diff --git a/hal/src/thumbv6m/clock/v1.rs b/hal/src/thumbv6m/clock/v1.rs index 5aa738c7786..f7f28566c6e 100644 --- a/hal/src/thumbv6m/clock/v1.rs +++ b/hal/src/thumbv6m/clock/v1.rs @@ -162,7 +162,7 @@ impl GenericClockController { let mut state = State { gclk }; set_flash_to_half_auto_wait_state(nvmctrl); - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] set_flash_manual_write(nvmctrl); enable_gclk_apb(pm); if use_external_crystal { @@ -225,11 +225,11 @@ impl GenericClockController { let mut state = State { gclk }; // No wait states needed <= 24 MHz @ 3.3v (ref. 37.12 NVM characteristics) - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] set_flash_manual_write(nvmctrl); // Get rid of unused warning - #[cfg(not(feature = "samd21"))] + #[cfg(not(any(feature = "samda1", feature = "samd21")))] let _ = nvmctrl; enable_gclk_apb(pm); @@ -440,19 +440,21 @@ clock_generator!( (ac_dig, AcDigClock, AC_DIG), (dac, DacClock, DAC), ); -// samd21 -#[cfg(feature = "samd21")] +// samd21/samda1 +#[cfg(any(feature = "samda1", feature = "samd21"))] clock_generator!( (tcc0_tcc1, Tcc0Tcc1Clock, TCC0_TCC1, Tcc0Tcc1), (tcc2_tc3, Tcc2Tc3Clock, TCC2_TC3, Tcc2Tc3), (tc4_tc5, Tc4Tc5Clock, TC4_TC5, Tc4Tc5), - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21j"))] (tc6_tc7, Tc6Tc7Clock, TC6_TC7, Tc6Tc7), (sercom0_core, Sercom0CoreClock, SERCOM0_CORE, Sercom0), (sercom1_core, Sercom1CoreClock, SERCOM1_CORE, Sercom1), (sercom2_core, Sercom2CoreClock, SERCOM2_CORE, Sercom2), (sercom3_core, Sercom3CoreClock, SERCOM3_CORE, Sercom3), + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] (sercom4_core, Sercom4CoreClock, SERCOM4_CORE, Sercom4), + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] (sercom5_core, Sercom5CoreClock, SERCOM5_CORE, Sercom5), (usb, UsbClock, USB, Usb), (rtc, RtcClock, RTC, Rtc), @@ -490,7 +492,7 @@ fn set_flash_to_half_auto_wait_state(nvmctrl: &mut NVMCTRL) { } /// Prevent automatic writes to flash by pointers to flash area -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] fn set_flash_manual_write(nvmctrl: &mut NVMCTRL) { nvmctrl.ctrlb.modify(|_, w| w.manw().set_bit()); } @@ -521,10 +523,13 @@ pub fn enable_internal_32kosc(sysctrl: &mut SYSCTRL) { /// Turn on the external 32hkz oscillator pub fn enable_external_32kosc(sysctrl: &mut SYSCTRL) { sysctrl.xosc32k.modify(|_, w| { + #[cfg(not(feature = "samda1"))] unsafe { // 6 here means: use 64k cycles of OSCULP32k to start up this oscillator w.startup().bits(6); } + #[cfg(feature = "samda1")] + w.startup().bits(6); w.ondemand().clear_bit(); // Enable 32khz output w.en32k().set_bit(); @@ -617,7 +622,7 @@ fn configure_and_enable_dfll48m(sysctrl: &mut SYSCTRL, use_external_crystal: boo // and finally enable it! sysctrl.dfllctrl.modify(|_, w| w.enable().set_bit()); - #[cfg(feature = "samd21")] + #[cfg(any(feature = "samda1", feature = "samd21"))] if use_external_crystal { // wait for lock while sysctrl.pclksr.read().dflllckc().bit_is_clear() diff --git a/hal/src/thumbv6m/clock/v2/gclkio.rs b/hal/src/thumbv6m/clock/v2/gclkio.rs index eeb0d088adc..0d53f147cdf 100644 --- a/hal/src/thumbv6m/clock/v2/gclkio.rs +++ b/hal/src/thumbv6m/clock/v2/gclkio.rs @@ -90,9 +90,9 @@ impl GclkIo for gpio::PA15 {} impl GclkIo for gpio::PA16 {} impl GclkIo for gpio::PA17 {} -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] impl GclkIo for gpio::PA20 {} -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] impl GclkIo for gpio::PA21 {} impl GclkIo for gpio::PA22 {} impl GclkIo for gpio::PA23 {} @@ -101,28 +101,28 @@ impl GclkIo for gpio::PA27 {} impl GclkIo for gpio::PA28 {} impl GclkIo for gpio::PA30 {} -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] impl GclkIo for gpio::PB10 {} -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] impl GclkIo for gpio::PB11 {} -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] impl GclkIo for gpio::PB12 {} -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] impl GclkIo for gpio::PB13 {} -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] impl GclkIo for gpio::PB14 {} -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] impl GclkIo for gpio::PB15 {} -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] impl GclkIo for gpio::PB16 {} -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] impl GclkIo for gpio::PB17 {} -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] impl GclkIo for gpio::PB22 {} -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] impl GclkIo for gpio::PB23 {} //============================================================================== diff --git a/hal/src/thumbv6m/clock/v2/osc32k.rs b/hal/src/thumbv6m/clock/v2/osc32k.rs index d63faefb1ac..c21fc52874f 100644 --- a/hal/src/thumbv6m/clock/v2/osc32k.rs +++ b/hal/src/thumbv6m/clock/v2/osc32k.rs @@ -88,8 +88,12 @@ impl Osc32kToken { #[inline] fn set_start_up(&mut self, start_up: Startup) { + #[cfg(not(feature = "samda1"))] self.osc32k() .modify(|_, w| unsafe { w.startup().bits(start_up.into()) }); + #[cfg(feature = "samda1")] + self.osc32k() + .modify(|_, w| w.startup().bits(start_up.into())); } #[inline] diff --git a/hal/src/thumbv6m/clock/v2/pclk.rs b/hal/src/thumbv6m/clock/v2/pclk.rs index 5310fe0ad5c..a43e87caa7e 100644 --- a/hal/src/thumbv6m/clock/v2/pclk.rs +++ b/hal/src/thumbv6m/clock/v2/pclk.rs @@ -192,14 +192,14 @@ macro_rules! with_pclk_types_ids { (Sercom1 = 21, sercom1) (Sercom2 = 22, sercom2) (Sercom3 = 23, sercom3) - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] (Sercom4 = 24, sercom4) - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] (Sercom5 = 25, sercom5) (Tcc0Tcc1 = 26, tcc0_tcc1) (Tcc2Tc3 = 27, tcc2_tc3) (Tc4Tc5 = 28, tc4_tc5) - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] (Tc6Tc7 = 29, tc6_tc7) (Adc = 30, adc) (AcDig = 31, ac_dig) diff --git a/hal/src/thumbv6m/clock/v2/types.rs b/hal/src/thumbv6m/clock/v2/types.rs index a90739e14b0..b95c9ec6389 100644 --- a/hal/src/thumbv6m/clock/v2/types.rs +++ b/hal/src/thumbv6m/clock/v2/types.rs @@ -20,7 +20,7 @@ use crate::typelevel::Sealed; pub use crate::sercom::{Sercom0, Sercom1, Sercom2, Sercom3}; -#[cfg(feature = "min-samd21g")] +#[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] pub use crate::sercom::{Sercom4, Sercom5}; macro_rules! create_types { @@ -66,7 +66,7 @@ create_types!(SysCtrl); create_types!(Tcc0Tcc1, Tcc0, Tcc1); create_types!(Tcc2Tc3, Tcc2, Tc3); create_types!(Tc4Tc5, Tc4, Tc5); -#[cfg(feature = "min-samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] create_types!(Tc6Tc7, Tc6, Tc7); create_types!(Usb); create_types!(Wdt); diff --git a/hal/src/thumbv6m/clock/v2/xosc.rs b/hal/src/thumbv6m/clock/v2/xosc.rs index af4011fb814..9c41c4e0473 100644 --- a/hal/src/thumbv6m/clock/v2/xosc.rs +++ b/hal/src/thumbv6m/clock/v2/xosc.rs @@ -171,8 +171,12 @@ impl XoscToken { #[inline] fn set_start_up(&mut self, start_up: Startup) { + #[cfg(not(feature = "samda1"))] self.xosc() .modify(|_, w| unsafe { w.startup().bits(start_up.into()) }); + #[cfg(feature = "samda1")] + self.xosc() + .modify(|_, w| w.startup().bits(start_up.into())); } #[inline] diff --git a/hal/src/thumbv6m/clock/v2/xosc32k.rs b/hal/src/thumbv6m/clock/v2/xosc32k.rs index 049161a5eb2..a0b29212903 100644 --- a/hal/src/thumbv6m/clock/v2/xosc32k.rs +++ b/hal/src/thumbv6m/clock/v2/xosc32k.rs @@ -89,8 +89,12 @@ impl Xosc32kToken { #[inline] fn set_start_up(&mut self, start_up: Startup) { + #[cfg(not(feature = "samda1"))] self.xosc32k() .modify(|_, w| unsafe { w.startup().bits(start_up.into()) }); + #[cfg(feature = "samda1")] + self.xosc32k() + .modify(|_, w| w.startup().bits(start_up.into())); } #[inline] diff --git a/hal/src/thumbv6m/eic/pin.rs b/hal/src/thumbv6m/eic/pin.rs index fdb7424fff6..c027a636670 100644 --- a/hal/src/thumbv6m/eic/pin.rs +++ b/hal/src/thumbv6m/eic/pin.rs @@ -253,148 +253,148 @@ ei!(ExtInt[7] { PA09, }); -// SAMD21 +// SAMD21/SAMDA1 -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[0] { #[cfg(not(any(feature = "samd21el", feature = "samd21gl")))] PA00, PA16, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB00, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB16, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[1] { #[cfg(not(any(feature = "samd21el", feature = "samd21gl")))] PA01, PA17, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB01, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB17, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[2] { PA02, PA18, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB02, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[3] { PA03, PA19, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB03, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[4] { PA04, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA20, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB04, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[5] { PA05, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA21, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB05, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[6] { PA06, PA22, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB06, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB22, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[7] { PA07, PA23, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB07, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB23, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[8] { #[cfg(not(feature = "samd21el"))] PA28, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB08, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[9] { PA09, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB09, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[10] { PA10, PA30, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB10, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[11] { PA11, PA31, - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PB11, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[12] { - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA12, PA24, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB12, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[13] { - #[cfg(feature = "min-samd21g")] + #[cfg(any(feature = "min-samda1g", feature = "min-samd21g"))] PA13, PA25, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB13, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[14] { PA14, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB14, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB30, }); -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] ei!(ExtInt[15] { PA15, PA27, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB15, - #[cfg(feature = "min-samd21j")] + #[cfg(any(feature = "min-samda1j", feature = "min-samd21j"))] PB31, }); diff --git a/hal/src/thumbv6m/mod.rs b/hal/src/thumbv6m/mod.rs index 06b668f15a9..c83ef8d069a 100644 --- a/hal/src/thumbv6m/mod.rs +++ b/hal/src/thumbv6m/mod.rs @@ -21,7 +21,7 @@ pub mod watchdog; #[cfg(feature = "usb")] #[cfg(all( - feature = "samd21", + any(feature = "samda1", feature = "samd21"), not(any(feature = "samd21el", feature = "samd21gl")) ))] pub mod usb; diff --git a/hal/src/thumbv6m/pwm.rs b/hal/src/thumbv6m/pwm.rs index a1455846bc9..40e184014b0 100644 --- a/hal/src/thumbv6m/pwm.rs +++ b/hal/src/thumbv6m/pwm.rs @@ -6,9 +6,9 @@ use crate::timer_params::TimerParams; use crate::pac::{PM, TCC0}; #[cfg(feature = "samd11")] use crate::pac::{TC1, TC2}; -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] use crate::pac::{TC3, TC4, TC5, TCC1, TCC2}; -#[cfg(feature = "samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "samd21j"))] use crate::pac::{TC6, TC7}; // Timer/Counter (TCx) @@ -136,14 +136,14 @@ pwm! { Pwm2: (TC2, Tc1Tc2Clock, apbcmask, tc2_, Pwm2Wrapper), } -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] pwm! { Pwm3: (TC3, Tcc2Tc3Clock, apbcmask, tc3_, Pwm3Wrapper), Pwm4: (TC4, Tc4Tc5Clock, apbcmask, tc4_, Pwm4Wrapper), Pwm5: (TC5, Tc4Tc5Clock, apbcmask, tc5_, Pwm5Wrapper), } -#[cfg(feature = "samd21j")] +#[cfg(any(feature = "min-samda1j", feature = "samd21j"))] pwm! { Pwm6: (TC6, Tc6Tc7Clock, apbcmask, tc6_, Pwm6Wrapper), Pwm7: (TC7, Tc6Tc7Clock, apbcmask, tc7_, Pwm7Wrapper), @@ -281,9 +281,10 @@ pwm_tcc! { Pwm0: (TCC0, Tcc0Clock, apbcmask, tcc0_, Pwm0Wrapper), } -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] pwm_tcc! { Pwm0: (TCC0, Tcc0Tcc1Clock, apbcmask, tcc0_, Pwm0Wrapper), Pwm1: (TCC1, Tcc0Tcc1Clock, apbcmask, tcc1_, Pwm1Wrapper), Pwm2: (TCC2, Tcc2Tc3Clock, apbcmask, tcc2_, Pwm2Wrapper), } + diff --git a/hal/src/thumbv6m/timer.rs b/hal/src/thumbv6m/timer.rs index eeb324490e8..0c964d69bb9 100644 --- a/hal/src/thumbv6m/timer.rs +++ b/hal/src/thumbv6m/timer.rs @@ -2,13 +2,13 @@ use crate::ehal::timer::{CountDown, Periodic}; #[cfg(feature = "samd11")] use crate::pac::tc1::COUNT16; -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] use crate::pac::tc3::COUNT16; #[allow(unused)] #[cfg(feature = "samd11")] use crate::pac::{PM, TC1}; #[allow(unused)] -#[cfg(feature = "samd21")] +#[cfg(any(feature = "samda1", feature = "samd21"))] use crate::pac::{PM, TC3, TC4, TC5}; use crate::timer_params::TimerParams; @@ -178,8 +178,8 @@ impl TimerCounter<$TC> tc! { TimerCounter1: (TC1, tc1_, Tc1Tc2Clock), } -// samd21 -#[cfg(feature = "samd21")] +// samd21/da1 +#[cfg(any(feature = "samda1", feature = "samd21"))] tc! { TimerCounter3: (TC3, tc3_, Tcc2Tc3Clock), TimerCounter4: (TC4, tc4_, Tc4Tc5Clock), diff --git a/hal/src/thumbv7em/clock/v1.rs b/hal/src/thumbv7em/clock/v1.rs index d36bbd6c3c4..65e9bcc6b4c 100644 --- a/hal/src/thumbv7em/clock/v1.rs +++ b/hal/src/thumbv7em/clock/v1.rs @@ -424,7 +424,9 @@ clock_generator!( (tcc0_tcc1, Tcc0Tcc1Clock, TCC0_TCC1, Tcc0Tcc1), (tc2_tc3, Tc2Tc3Clock, TC2_TC3, Tc2Tc3), (tcc2_tcc3, Tcc2Tcc3Clock, TCC2_TCC3, Tcc2Tcc3), + #[cfg(feature = "min-samd51j")] (tc4_tc5, Tc4Tc5Clock, TC4_TC5, Tc4Tc5), + #[cfg(feature = "min-samd51j")] (tcc4, Tcc4Clock, TCC4, Tcc4), #[cfg(feature = "min-samd51n")] (tc6_tc7, Tc6Tc7Clock, TC6_TC7, Tc6Tc7), @@ -464,7 +466,9 @@ clock_generator!( (ac, AcClock, AC, Ac), (ccl, CclClock, CCL, Ccl), (dac, DacClock, DAC, Dac), + #[cfg(feature = "min-samd51j")] (i2s0, I2S0Clock, I2S0, I2S0), + #[cfg(feature = "min-samd51j")] (i2s1, I2S1Clock, I2S1, I2S1), (sdhc0, Sdhc0Clock, SDHC0, Sdhc0), #[cfg(feature = "min-samd51n")] diff --git a/hal/src/thumbv7em/clock/v2.rs b/hal/src/thumbv7em/clock/v2.rs index aa6320f184a..89177837fcf 100644 --- a/hal/src/thumbv7em/clock/v2.rs +++ b/hal/src/thumbv7em/clock/v2.rs @@ -169,6 +169,7 @@ impl PrivateDecrement for Enabled { impl Counter for Enabled {} /// Test +#[cfg(feature="min-samd51j")] // due to PB14 pin usage pub fn test() { use crate::{ clock::v2::{ diff --git a/pac/atsamda1e/Cargo.toml b/pac/atsamda1e/Cargo.toml new file mode 100644 index 00000000000..09912765c88 --- /dev/null +++ b/pac/atsamda1e/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamda1e" +description = "Peripheral access API for ATSAMDA1E microcontrollers (generated using svd2rust)" +version = "0.12.0" +authors = ["Wez Furlong ", "Paul Sajna "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamda1e/README.md b/pac/atsamda1e/README.md new file mode 100644 index 00000000000..71b59013372 --- /dev/null +++ b/pac/atsamda1e/README.md @@ -0,0 +1,26 @@ +# ATSAMDA1E + +A peripheral access crate for the ATSAMDA1E chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamda1e.svg)](https://crates.io/crates/atsamda1e) + +## [Documentation](https://docs.rs/atsamda1e) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamda1e/build.rs b/pac/atsamda1e/build.rs new file mode 100644 index 00000000000..597923f5089 --- /dev/null +++ b/pac/atsamda1e/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamda1e/device.x b/pac/atsamda1e/device.x new file mode 100644 index 00000000000..c0f686af5ad --- /dev/null +++ b/pac/atsamda1e/device.x @@ -0,0 +1,29 @@ +PROVIDE(PM = DefaultHandler); +PROVIDE(SYSCTRL = DefaultHandler); +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(USB = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(SERCOM4 = DefaultHandler); +PROVIDE(SERCOM5 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(TC5 = DefaultHandler); +PROVIDE(TC6 = DefaultHandler); +PROVIDE(TC7 = DefaultHandler); +PROVIDE(ADC = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(DAC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); +PROVIDE(I2S = DefaultHandler); + diff --git a/pac/atsamda1e/src/ac.rs b/pac/atsamda1e/src/ac.rs new file mode 100644 index 00000000000..ed9e2eeafde --- /dev/null +++ b/pac/atsamda1e/src/ac.rs @@ -0,0 +1,80 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x09 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x0a - Status C"] + pub statusc: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x0c - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x03], + #[doc = "0x10..0x18 - Comparator Control n"] + pub compctrl: [crate::Reg; 2], + _reserved11: [u8; 0x08], + #[doc = "0x20 - Scaler n"] + pub scaler: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; diff --git a/pac/atsamda1e/src/ac/compctrl.rs b/pac/atsamda1e/src/ac/compctrl.rs new file mode 100644 index 00000000000..531766edc60 --- /dev/null +++ b/pac/atsamda1e/src/ac/compctrl.rs @@ -0,0 +1,927 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "1: High speed"] + HIGH = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 1 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEG_A { + match self.bits { + 0 => MUXNEG_A::PIN0, + 1 => MUXNEG_A::PIN1, + 2 => MUXNEG_A::PIN2, + 3 => MUXNEG_A::PIN3, + 4 => MUXNEG_A::GND, + 5 => MUXNEG_A::VSCALE, + 6 => MUXNEG_A::BANDGAP, + 7 => MUXNEG_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXNEG_A::DAC + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEG_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXPOS_A { + match self.bits { + 0 => MUXPOS_A::PIN0, + 1 => MUXPOS_A::PIN1, + 2 => MUXPOS_A::PIN2, + 3 => MUXPOS_A::PIN3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:13 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 2:3 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bits 5:6 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:13 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/ctrla.rs b/pac/atsamda1e/src/ac/ctrla.rs new file mode 100644 index 00000000000..1a9beb48325 --- /dev/null +++ b/pac/atsamda1e/src/ac/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LPMUX` reader - Low-Power Mux"] +pub struct LPMUX_R(crate::FieldReader); +impl LPMUX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMUX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMUX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMUX` writer - Low-Power Mux"] +pub struct LPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> LPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Low-Power Mux"] + #[inline(always)] + pub fn lpmux(&self) -> LPMUX_R { + LPMUX_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Low-Power Mux"] + #[inline(always)] + pub fn lpmux(&mut self) -> LPMUX_W { + LPMUX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/ctrlb.rs b/pac/atsamda1e/src/ac/ctrlb.rs new file mode 100644 index 00000000000..68aa8d2a20b --- /dev/null +++ b/pac/atsamda1e/src/ac/ctrlb.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/evctrl.rs b/pac/atsamda1e/src/ac/evctrl.rs new file mode 100644 index 00000000000..88fbebc8430 --- /dev/null +++ b/pac/atsamda1e/src/ac/evctrl.rs @@ -0,0 +1,301 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/intenclr.rs b/pac/atsamda1e/src/ac/intenclr.rs new file mode 100644 index 00000000000..45e3320d293 --- /dev/null +++ b/pac/atsamda1e/src/ac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/intenset.rs b/pac/atsamda1e/src/ac/intenset.rs new file mode 100644 index 00000000000..5354a4d111d --- /dev/null +++ b/pac/atsamda1e/src/ac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/intflag.rs b/pac/atsamda1e/src/ac/intflag.rs new file mode 100644 index 00000000000..7da0fea7569 --- /dev/null +++ b/pac/atsamda1e/src/ac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/scaler.rs b/pac/atsamda1e/src/ac/scaler.rs new file mode 100644 index 00000000000..091cacfaeb4 --- /dev/null +++ b/pac/atsamda1e/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/statusa.rs b/pac/atsamda1e/src/ac/statusa.rs new file mode 100644 index 00000000000..7b98c567e8a --- /dev/null +++ b/pac/atsamda1e/src/ac/statusa.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/statusb.rs b/pac/atsamda1e/src/ac/statusb.rs new file mode 100644 index 00000000000..fa16c8bda71 --- /dev/null +++ b/pac/atsamda1e/src/ac/statusb.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/statusc.rs b/pac/atsamda1e/src/ac/statusc.rs new file mode 100644 index 00000000000..7bef2226d54 --- /dev/null +++ b/pac/atsamda1e/src/ac/statusc.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/ac/winctrl.rs b/pac/atsamda1e/src/ac/winctrl.rs new file mode 100644 index 00000000000..3259570489e --- /dev/null +++ b/pac/atsamda1e/src/ac/winctrl.rs @@ -0,0 +1,225 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc.rs b/pac/atsamda1e/src/adc.rs new file mode 100644 index 00000000000..33524a423c2 --- /dev/null +++ b/pac/atsamda1e/src/adc.rs @@ -0,0 +1,130 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x02 - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x03 - Sampling Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x08 - Window Monitor Control"] + pub winctrl: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x0c - Software Trigger"] + pub swtrig: crate::Reg, + _reserved7: [u8; 0x03], + #[doc = "0x10 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x14 - Event Control"] + pub evctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x16 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x17 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x19 - Status"] + pub status: crate::Reg, + #[doc = "0x1a - Result"] + pub result: crate::Reg, + #[doc = "0x1c - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + _reserved15: [u8; 0x02], + #[doc = "0x20 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x24 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x26 - Offset Correction"] + pub offsetcorr: crate::Reg, + #[doc = "0x28 - Calibration"] + pub calib: crate::Reg, + #[doc = "0x2a - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sampling Time Control"] +pub mod sampctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Monitor Control"] +pub mod winctrl; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1e/src/adc/avgctrl.rs b/pac/atsamda1e/src/adc/avgctrl.rs new file mode 100644 index 00000000000..ddb735715c9 --- /dev/null +++ b/pac/atsamda1e/src/adc/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/calib.rs b/pac/atsamda1e/src/adc/calib.rs new file mode 100644 index 00000000000..553ad515946 --- /dev/null +++ b/pac/atsamda1e/src/adc/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LINEARITY_CAL` reader - Linearity Calibration Value"] +pub struct LINEARITY_CAL_R(crate::FieldReader); +impl LINEARITY_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINEARITY_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINEARITY_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINEARITY_CAL` writer - Linearity Calibration Value"] +pub struct LINEARITY_CAL_W<'a> { + w: &'a mut W, +} +impl<'a> LINEARITY_CAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Field `BIAS_CAL` reader - Bias Calibration Value"] +pub struct BIAS_CAL_R(crate::FieldReader); +impl BIAS_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIAS_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIAS_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIAS_CAL` writer - Bias Calibration Value"] +pub struct BIAS_CAL_W<'a> { + w: &'a mut W, +} +impl<'a> BIAS_CAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Linearity Calibration Value"] + #[inline(always)] + pub fn linearity_cal(&self) -> LINEARITY_CAL_R { + LINEARITY_CAL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Bias Calibration Value"] + #[inline(always)] + pub fn bias_cal(&self) -> BIAS_CAL_R { + BIAS_CAL_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Linearity Calibration Value"] + #[inline(always)] + pub fn linearity_cal(&mut self) -> LINEARITY_CAL_W { + LINEARITY_CAL_W { w: self } + } + #[doc = "Bits 8:10 - Bias Calibration Value"] + #[inline(always)] + pub fn bias_cal(&mut self) -> BIAS_CAL_W { + BIAS_CAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/ctrla.rs b/pac/atsamda1e/src/adc/ctrla.rs new file mode 100644 index 00000000000..117922e5aae --- /dev/null +++ b/pac/atsamda1e/src/adc/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/ctrlb.rs b/pac/atsamda1e/src/adc/ctrlb.rs new file mode 100644 index 00000000000..79137605c46 --- /dev/null +++ b/pac/atsamda1e/src/adc/ctrlb.rs @@ -0,0 +1,530 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enabled"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enabled"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit result"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit result"] + _10BIT = 2, + #[doc = "3: 8-bit result"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit result"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit result"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit result"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 4"] + DIV4 = 0, + #[doc = "1: Peripheral clock divided by 8"] + DIV8 = 1, + #[doc = "2: Peripheral clock divided by 16"] + DIV16 = 2, + #[doc = "3: Peripheral clock divided by 32"] + DIV32 = 3, + #[doc = "4: Peripheral clock divided by 64"] + DIV64 = 4, + #[doc = "5: Peripheral clock divided by 128"] + DIV128 = 5, + #[doc = "6: Peripheral clock divided by 256"] + DIV256 = 6, + #[doc = "7: Peripheral clock divided by 512"] + DIV512 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV4, + 1 => PRESCALER_A::DIV8, + 2 => PRESCALER_A::DIV16, + 3 => PRESCALER_A::DIV32, + 4 => PRESCALER_A::DIV64, + 5 => PRESCALER_A::DIV128, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV512, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Peripheral clock divided by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enabled"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enabled"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/dbgctrl.rs b/pac/atsamda1e/src/adc/dbgctrl.rs new file mode 100644 index 00000000000..53636eb2b33 --- /dev/null +++ b/pac/atsamda1e/src/adc/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/evctrl.rs b/pac/atsamda1e/src/adc/evctrl.rs new file mode 100644 index 00000000000..cf040e96c73 --- /dev/null +++ b/pac/atsamda1e/src/adc/evctrl.rs @@ -0,0 +1,254 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event In"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event In"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCEI` reader - Synchronization Event In"] +pub struct SYNCEI_R(crate::FieldReader); +impl SYNCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCEI` writer - Synchronization Event In"] +pub struct SYNCEI_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event In"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Synchronization Event In"] + #[inline(always)] + pub fn syncei(&self) -> SYNCEI_R { + SYNCEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event In"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Synchronization Event In"] + #[inline(always)] + pub fn syncei(&mut self) -> SYNCEI_W { + SYNCEI_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/gaincorr.rs b/pac/atsamda1e/src/adc/gaincorr.rs new file mode 100644 index 00000000000..496cb8c6021 --- /dev/null +++ b/pac/atsamda1e/src/adc/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/inputctrl.rs b/pac/atsamda1e/src/adc/inputctrl.rs new file mode 100644 index 00000000000..8a7dc86535b --- /dev/null +++ b/pac/atsamda1e/src/adc/inputctrl.rs @@ -0,0 +1,853 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + PIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + PIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + PIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + PIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + PIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + PIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + PIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + PIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + PIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + PIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + PIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + PIN11 = 11, + #[doc = "12: ADC AIN12 Pin"] + PIN12 = 12, + #[doc = "13: ADC AIN13 Pin"] + PIN13 = 13, + #[doc = "14: ADC AIN14 Pin"] + PIN14 = 14, + #[doc = "15: ADC AIN15 Pin"] + PIN15 = 15, + #[doc = "16: ADC AIN16 Pin"] + PIN16 = 16, + #[doc = "17: ADC AIN17 Pin"] + PIN17 = 17, + #[doc = "18: ADC AIN18 Pin"] + PIN18 = 18, + #[doc = "19: ADC AIN19 Pin"] + PIN19 = 19, + #[doc = "24: Temperature Reference"] + TEMP = 24, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "28: DAC Output"] + DAC = 28, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::PIN4), + 5 => Some(MUXPOS_A::PIN5), + 6 => Some(MUXPOS_A::PIN6), + 7 => Some(MUXPOS_A::PIN7), + 8 => Some(MUXPOS_A::PIN8), + 9 => Some(MUXPOS_A::PIN9), + 10 => Some(MUXPOS_A::PIN10), + 11 => Some(MUXPOS_A::PIN11), + 12 => Some(MUXPOS_A::PIN12), + 13 => Some(MUXPOS_A::PIN13), + 14 => Some(MUXPOS_A::PIN14), + 15 => Some(MUXPOS_A::PIN15), + 16 => Some(MUXPOS_A::PIN16), + 17 => Some(MUXPOS_A::PIN17), + 18 => Some(MUXPOS_A::PIN18), + 19 => Some(MUXPOS_A::PIN19), + 24 => Some(MUXPOS_A::TEMP), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + 28 => Some(MUXPOS_A::DAC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `PIN4`"] + #[inline(always)] + pub fn is_pin4(&self) -> bool { + **self == MUXPOS_A::PIN4 + } + #[doc = "Checks if the value of the field is `PIN5`"] + #[inline(always)] + pub fn is_pin5(&self) -> bool { + **self == MUXPOS_A::PIN5 + } + #[doc = "Checks if the value of the field is `PIN6`"] + #[inline(always)] + pub fn is_pin6(&self) -> bool { + **self == MUXPOS_A::PIN6 + } + #[doc = "Checks if the value of the field is `PIN7`"] + #[inline(always)] + pub fn is_pin7(&self) -> bool { + **self == MUXPOS_A::PIN7 + } + #[doc = "Checks if the value of the field is `PIN8`"] + #[inline(always)] + pub fn is_pin8(&self) -> bool { + **self == MUXPOS_A::PIN8 + } + #[doc = "Checks if the value of the field is `PIN9`"] + #[inline(always)] + pub fn is_pin9(&self) -> bool { + **self == MUXPOS_A::PIN9 + } + #[doc = "Checks if the value of the field is `PIN10`"] + #[inline(always)] + pub fn is_pin10(&self) -> bool { + **self == MUXPOS_A::PIN10 + } + #[doc = "Checks if the value of the field is `PIN11`"] + #[inline(always)] + pub fn is_pin11(&self) -> bool { + **self == MUXPOS_A::PIN11 + } + #[doc = "Checks if the value of the field is `PIN12`"] + #[inline(always)] + pub fn is_pin12(&self) -> bool { + **self == MUXPOS_A::PIN12 + } + #[doc = "Checks if the value of the field is `PIN13`"] + #[inline(always)] + pub fn is_pin13(&self) -> bool { + **self == MUXPOS_A::PIN13 + } + #[doc = "Checks if the value of the field is `PIN14`"] + #[inline(always)] + pub fn is_pin14(&self) -> bool { + **self == MUXPOS_A::PIN14 + } + #[doc = "Checks if the value of the field is `PIN15`"] + #[inline(always)] + pub fn is_pin15(&self) -> bool { + **self == MUXPOS_A::PIN15 + } + #[doc = "Checks if the value of the field is `PIN16`"] + #[inline(always)] + pub fn is_pin16(&self) -> bool { + **self == MUXPOS_A::PIN16 + } + #[doc = "Checks if the value of the field is `PIN17`"] + #[inline(always)] + pub fn is_pin17(&self) -> bool { + **self == MUXPOS_A::PIN17 + } + #[doc = "Checks if the value of the field is `PIN18`"] + #[inline(always)] + pub fn is_pin18(&self) -> bool { + **self == MUXPOS_A::PIN18 + } + #[doc = "Checks if the value of the field is `PIN19`"] + #[inline(always)] + pub fn is_pin19(&self) -> bool { + **self == MUXPOS_A::PIN19 + } + #[doc = "Checks if the value of the field is `TEMP`"] + #[inline(always)] + pub fn is_temp(&self) -> bool { + **self == MUXPOS_A::TEMP + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXPOS_A::DAC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn pin4(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn pin5(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn pin6(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn pin7(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn pin8(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn pin9(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn pin10(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn pin11(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN11) + } + #[doc = "ADC AIN12 Pin"] + #[inline(always)] + pub fn pin12(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN12) + } + #[doc = "ADC AIN13 Pin"] + #[inline(always)] + pub fn pin13(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN13) + } + #[doc = "ADC AIN14 Pin"] + #[inline(always)] + pub fn pin14(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN14) + } + #[doc = "ADC AIN15 Pin"] + #[inline(always)] + pub fn pin15(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN15) + } + #[doc = "ADC AIN16 Pin"] + #[inline(always)] + pub fn pin16(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN16) + } + #[doc = "ADC AIN17 Pin"] + #[inline(always)] + pub fn pin17(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN17) + } + #[doc = "ADC AIN18 Pin"] + #[inline(always)] + pub fn pin18(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN18) + } + #[doc = "ADC AIN19 Pin"] + #[inline(always)] + pub fn pin19(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN19) + } + #[doc = "Temperature Reference"] + #[inline(always)] + pub fn temp(self) -> &'a mut W { + self.variant(MUXPOS_A::TEMP) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = "DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXPOS_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + PIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + PIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + PIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + PIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + PIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + PIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + PIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + PIN7 = 7, + #[doc = "24: Internal Ground"] + GND = 24, + #[doc = "25: I/O Ground"] + IOGND = 25, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::PIN0), + 1 => Some(MUXNEG_A::PIN1), + 2 => Some(MUXNEG_A::PIN2), + 3 => Some(MUXNEG_A::PIN3), + 4 => Some(MUXNEG_A::PIN4), + 5 => Some(MUXNEG_A::PIN5), + 6 => Some(MUXNEG_A::PIN6), + 7 => Some(MUXNEG_A::PIN7), + 24 => Some(MUXNEG_A::GND), + 25 => Some(MUXNEG_A::IOGND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `PIN4`"] + #[inline(always)] + pub fn is_pin4(&self) -> bool { + **self == MUXNEG_A::PIN4 + } + #[doc = "Checks if the value of the field is `PIN5`"] + #[inline(always)] + pub fn is_pin5(&self) -> bool { + **self == MUXNEG_A::PIN5 + } + #[doc = "Checks if the value of the field is `PIN6`"] + #[inline(always)] + pub fn is_pin6(&self) -> bool { + **self == MUXNEG_A::PIN6 + } + #[doc = "Checks if the value of the field is `PIN7`"] + #[inline(always)] + pub fn is_pin7(&self) -> bool { + **self == MUXNEG_A::PIN7 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `IOGND`"] + #[inline(always)] + pub fn is_iognd(&self) -> bool { + **self == MUXNEG_A::IOGND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn pin4(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn pin5(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn pin6(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn pin7(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN7) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "I/O Ground"] + #[inline(always)] + pub fn iognd(self) -> &'a mut W { + self.variant(MUXNEG_A::IOGND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `INPUTSCAN` reader - Number of Input Channels Included in Scan"] +pub struct INPUTSCAN_R(crate::FieldReader); +impl INPUTSCAN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INPUTSCAN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTSCAN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTSCAN` writer - Number of Input Channels Included in Scan"] +pub struct INPUTSCAN_W<'a> { + w: &'a mut W, +} +impl<'a> INPUTSCAN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INPUTOFFSET` reader - Positive Mux Setting Offset"] +pub struct INPUTOFFSET_R(crate::FieldReader); +impl INPUTOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INPUTOFFSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTOFFSET` writer - Positive Mux Setting Offset"] +pub struct INPUTOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> INPUTOFFSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Gain Factor Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 1x"] + _1X = 0, + #[doc = "1: 2x"] + _2X = 1, + #[doc = "2: 4x"] + _4X = 2, + #[doc = "3: 8x"] + _8X = 3, + #[doc = "4: 16x"] + _16X = 4, + #[doc = "15: 1/2x"] + DIV2 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Gain Factor Selection"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::_1X), + 1 => Some(GAIN_A::_2X), + 2 => Some(GAIN_A::_4X), + 3 => Some(GAIN_A::_8X), + 4 => Some(GAIN_A::_16X), + 15 => Some(GAIN_A::DIV2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1X`"] + #[inline(always)] + pub fn is_1x(&self) -> bool { + **self == GAIN_A::_1X + } + #[doc = "Checks if the value of the field is `_2X`"] + #[inline(always)] + pub fn is_2x(&self) -> bool { + **self == GAIN_A::_2X + } + #[doc = "Checks if the value of the field is `_4X`"] + #[inline(always)] + pub fn is_4x(&self) -> bool { + **self == GAIN_A::_4X + } + #[doc = "Checks if the value of the field is `_8X`"] + #[inline(always)] + pub fn is_8x(&self) -> bool { + **self == GAIN_A::_8X + } + #[doc = "Checks if the value of the field is `_16X`"] + #[inline(always)] + pub fn is_16x(&self) -> bool { + **self == GAIN_A::_16X + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == GAIN_A::DIV2 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Gain Factor Selection"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1x"] + #[inline(always)] + pub fn _1x(self) -> &'a mut W { + self.variant(GAIN_A::_1X) + } + #[doc = "2x"] + #[inline(always)] + pub fn _2x(self) -> &'a mut W { + self.variant(GAIN_A::_2X) + } + #[doc = "4x"] + #[inline(always)] + pub fn _4x(self) -> &'a mut W { + self.variant(GAIN_A::_4X) + } + #[doc = "8x"] + #[inline(always)] + pub fn _8x(self) -> &'a mut W { + self.variant(GAIN_A::_8X) + } + #[doc = "16x"] + #[inline(always)] + pub fn _16x(self) -> &'a mut W { + self.variant(GAIN_A::_16X) + } + #[doc = "1/2x"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(GAIN_A::DIV2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] + #[inline(always)] + pub fn inputscan(&self) -> INPUTSCAN_R { + INPUTSCAN_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Positive Mux Setting Offset"] + #[inline(always)] + pub fn inputoffset(&self) -> INPUTOFFSET_R { + INPUTOFFSET_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Gain Factor Selection"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] + #[inline(always)] + pub fn inputscan(&mut self) -> INPUTSCAN_W { + INPUTSCAN_W { w: self } + } + #[doc = "Bits 20:23 - Positive Mux Setting Offset"] + #[inline(always)] + pub fn inputoffset(&mut self) -> INPUTOFFSET_W { + INPUTOFFSET_W { w: self } + } + #[doc = "Bits 24:27 - Gain Factor Selection"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/intenclr.rs b/pac/atsamda1e/src/adc/intenclr.rs new file mode 100644 index 00000000000..453afa12c61 --- /dev/null +++ b/pac/atsamda1e/src/adc/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/intenset.rs b/pac/atsamda1e/src/adc/intenset.rs new file mode 100644 index 00000000000..0d36429e544 --- /dev/null +++ b/pac/atsamda1e/src/adc/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/intflag.rs b/pac/atsamda1e/src/adc/intflag.rs new file mode 100644 index 00000000000..fec838269e9 --- /dev/null +++ b/pac/atsamda1e/src/adc/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/offsetcorr.rs b/pac/atsamda1e/src/adc/offsetcorr.rs new file mode 100644 index 00000000000..24a97427c64 --- /dev/null +++ b/pac/atsamda1e/src/adc/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/refctrl.rs b/pac/atsamda1e/src/adc/refctrl.rs new file mode 100644 index 00000000000..8053351459b --- /dev/null +++ b/pac/atsamda1e/src/adc/refctrl.rs @@ -0,0 +1,238 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: 1.0V voltage reference"] + INT1V = 0, + #[doc = "1: 1/1.48 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA (only for VDDANA > 2.0V)"] + INTVCC1 = 2, + #[doc = "3: External reference A"] + AREFA = 3, + #[doc = "4: External reference B"] + AREFB = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 4 => Some(REFSEL_A::AREFB), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + **self == REFSEL_A::AREFB + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.0V voltage reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "1/1.48 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA (only for VDDANA > 2.0V)"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External reference A"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "External reference B"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSEL_A::AREFB) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/result.rs b/pac/atsamda1e/src/adc/result.rs new file mode 100644 index 00000000000..f93bf58c6ba --- /dev/null +++ b/pac/atsamda1e/src/adc/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Conversion Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Conversion Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/sampctrl.rs b/pac/atsamda1e/src/adc/sampctrl.rs new file mode 100644 index 00000000000..b8cbc598b10 --- /dev/null +++ b/pac/atsamda1e/src/adc/sampctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sampling Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/status.rs b/pac/atsamda1e/src/adc/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1e/src/adc/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/swtrig.rs b/pac/atsamda1e/src/adc/swtrig.rs new file mode 100644 index 00000000000..111c0662dea --- /dev/null +++ b/pac/atsamda1e/src/adc/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Conversion Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Conversion Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - ADC Start Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - ADC Start Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Conversion Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ADC Start Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Conversion Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - ADC Start Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/winctrl.rs b/pac/atsamda1e/src/adc/winctrl.rs new file mode 100644 index 00000000000..6dd12786c7f --- /dev/null +++ b/pac/atsamda1e/src/adc/winctrl.rs @@ -0,0 +1,191 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: Mode 1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: Mode 2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: Mode 3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: Mode 4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "Mode 1: RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "Mode 2: RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "Mode 3: WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "Mode 4: !(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/winlt.rs b/pac/atsamda1e/src/adc/winlt.rs new file mode 100644 index 00000000000..2a339768476 --- /dev/null +++ b/pac/atsamda1e/src/adc/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/adc/winut.rs b/pac/atsamda1e/src/adc/winut.rs new file mode 100644 index 00000000000..0ea12317493 --- /dev/null +++ b/pac/atsamda1e/src/adc/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac.rs b/pac/atsamda1e/src/dac.rs new file mode 100644 index 00000000000..1816621e5db --- /dev/null +++ b/pac/atsamda1e/src/dac.rs @@ -0,0 +1,60 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Data"] + pub data: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x0c - Data Buffer"] + pub databuf: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DATABUF register accessor: an alias for `Reg`"] +pub type DATABUF = crate::Reg; +#[doc = "Data Buffer"] +pub mod databuf; diff --git a/pac/atsamda1e/src/dac/ctrla.rs b/pac/atsamda1e/src/dac/ctrla.rs new file mode 100644 index 00000000000..117922e5aae --- /dev/null +++ b/pac/atsamda1e/src/dac/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/ctrlb.rs b/pac/atsamda1e/src/dac/ctrlb.rs new file mode 100644 index 00000000000..1da837c6d4a --- /dev/null +++ b/pac/atsamda1e/src/dac/ctrlb.rs @@ -0,0 +1,400 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EOEN` reader - External Output Enable"] +pub struct EOEN_R(crate::FieldReader); +impl EOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EOEN` writer - External Output Enable"] +pub struct EOEN_W<'a> { + w: &'a mut W, +} +impl<'a> EOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `IOEN` reader - Internal Output Enable"] +pub struct IOEN_R(crate::FieldReader); +impl IOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOEN` writer - Internal Output Enable"] +pub struct IOEN_W<'a> { + w: &'a mut W, +} +impl<'a> IOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VPD` reader - Voltage Pump Disable"] +pub struct VPD_R(crate::FieldReader); +impl VPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VPD` writer - Voltage Pump Disable"] +pub struct VPD_W<'a> { + w: &'a mut W, +} +impl<'a> VPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BDWP` reader - Bypass DATABUF Write Protection"] +pub struct BDWP_R(crate::FieldReader); +impl BDWP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BDWP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BDWP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BDWP` writer - Bypass DATABUF Write Protection"] +pub struct BDWP_W<'a> { + w: &'a mut W, +} +impl<'a> BDWP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal 1.0V reference"] + INT1V = 0, + #[doc = "1: AVCC"] + AVCC = 1, + #[doc = "2: External reference"] + VREFP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::AVCC), + 2 => Some(REFSEL_A::VREFP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `AVCC`"] + #[inline(always)] + pub fn is_avcc(&self) -> bool { + **self == REFSEL_A::AVCC + } + #[doc = "Checks if the value of the field is `VREFP`"] + #[inline(always)] + pub fn is_vrefp(&self) -> bool { + **self == REFSEL_A::VREFP + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal 1.0V reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "AVCC"] + #[inline(always)] + pub fn avcc(self) -> &'a mut W { + self.variant(REFSEL_A::AVCC) + } + #[doc = "External reference"] + #[inline(always)] + pub fn vrefp(self) -> &'a mut W { + self.variant(REFSEL_A::VREFP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&self) -> EOEN_R { + EOEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&self) -> IOEN_R { + IOEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&self) -> VPD_R { + VPD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Bypass DATABUF Write Protection"] + #[inline(always)] + pub fn bdwp(&self) -> BDWP_R { + BDWP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&mut self) -> EOEN_W { + EOEN_W { w: self } + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&mut self) -> IOEN_W { + IOEN_W { w: self } + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&mut self) -> VPD_W { + VPD_W { w: self } + } + #[doc = "Bit 4 - Bypass DATABUF Write Protection"] + #[inline(always)] + pub fn bdwp(&mut self) -> BDWP_W { + BDWP_W { w: self } + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/data.rs b/pac/atsamda1e/src/dac/data.rs new file mode 100644 index 00000000000..4caca5e0a51 --- /dev/null +++ b/pac/atsamda1e/src/dac/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data value to be converted"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data value to be converted"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/databuf.rs b/pac/atsamda1e/src/dac/databuf.rs new file mode 100644 index 00000000000..1e945f893ff --- /dev/null +++ b/pac/atsamda1e/src/dac/databuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATABUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATABUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATABUF` reader - Data Buffer"] +pub struct DATABUF_R(crate::FieldReader); +impl DATABUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATABUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATABUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATABUF` writer - Data Buffer"] +pub struct DATABUF_W<'a> { + w: &'a mut W, +} +impl<'a> DATABUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&self) -> DATABUF_R { + DATABUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&mut self) -> DATABUF_W { + DATABUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databuf](index.html) module"] +pub struct DATABUF_SPEC; +impl crate::RegisterSpec for DATABUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [databuf::R](R) reader structure"] +impl crate::Readable for DATABUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [databuf::W](W) writer structure"] +impl crate::Writable for DATABUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATABUF to value 0"] +impl crate::Resettable for DATABUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/evctrl.rs b/pac/atsamda1e/src/dac/evctrl.rs new file mode 100644 index 00000000000..7d48fce2186 --- /dev/null +++ b/pac/atsamda1e/src/dac/evctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTYEO` reader - Data Buffer Empty Event Output"] +pub struct EMPTYEO_R(crate::FieldReader); +impl EMPTYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTYEO` writer - Data Buffer Empty Event Output"] +pub struct EMPTYEO_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&self) -> EMPTYEO_R { + EMPTYEO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&mut self) -> EMPTYEO_W { + EMPTYEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/intenclr.rs b/pac/atsamda1e/src/dac/intenclr.rs new file mode 100644 index 00000000000..5d97a2c4cd4 --- /dev/null +++ b/pac/atsamda1e/src/dac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/intenset.rs b/pac/atsamda1e/src/dac/intenset.rs new file mode 100644 index 00000000000..27b8e50d55a --- /dev/null +++ b/pac/atsamda1e/src/dac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/intflag.rs b/pac/atsamda1e/src/dac/intflag.rs new file mode 100644 index 00000000000..0df47b31e15 --- /dev/null +++ b/pac/atsamda1e/src/dac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dac/status.rs b/pac/atsamda1e/src/dac/status.rs new file mode 100644 index 00000000000..2667b356df2 --- /dev/null +++ b/pac/atsamda1e/src/dac/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy Status"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy Status"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac.rs b/pac/atsamda1e/src/dmac.rs new file mode 100644 index 00000000000..c23d3669755 --- /dev/null +++ b/pac/atsamda1e/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamda1e/src/dmac/active.rs b/pac/atsamda1e/src/dmac/active.rs new file mode 100644 index 00000000000..c3cc5a0420b --- /dev/null +++ b/pac/atsamda1e/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/baseaddr.rs b/pac/atsamda1e/src/dmac/baseaddr.rs new file mode 100644 index 00000000000..cec8c8cf077 --- /dev/null +++ b/pac/atsamda1e/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/busych.rs b/pac/atsamda1e/src/dmac/busych.rs new file mode 100644 index 00000000000..6f9419d5828 --- /dev/null +++ b/pac/atsamda1e/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/chctrla.rs b/pac/atsamda1e/src/dmac/chctrla.rs new file mode 100644 index 00000000000..49471b92938 --- /dev/null +++ b/pac/atsamda1e/src/dmac/chctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/chctrlb.rs b/pac/atsamda1e/src/dmac/chctrlb.rs new file mode 100644 index 00000000000..c52f6f8de35 --- /dev/null +++ b/pac/atsamda1e/src/dmac/chctrlb.rs @@ -0,0 +1,1331 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Peripheral Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: SERCOM0 RX Trigger"] + SERCOM0_RX = 1, + #[doc = "2: SERCOM0 TX Trigger"] + SERCOM0_TX = 2, + #[doc = "3: SERCOM1 RX Trigger"] + SERCOM1_RX = 3, + #[doc = "4: SERCOM1 TX Trigger"] + SERCOM1_TX = 4, + #[doc = "5: SERCOM2 RX Trigger"] + SERCOM2_RX = 5, + #[doc = "6: SERCOM2 TX Trigger"] + SERCOM2_TX = 6, + #[doc = "7: SERCOM3 RX Trigger"] + SERCOM3_RX = 7, + #[doc = "8: SERCOM3 TX Trigger"] + SERCOM3_TX = 8, + #[doc = "9: SERCOM4 RX Trigger"] + SERCOM4_RX = 9, + #[doc = "10: SERCOM4 TX Trigger"] + SERCOM4_TX = 10, + #[doc = "11: SERCOM5 RX Trigger"] + SERCOM5_RX = 11, + #[doc = "12: SERCOM5 TX Trigger"] + SERCOM5_TX = 12, + #[doc = "13: TCC0 Overflow Trigger"] + TCC0_OVF = 13, + #[doc = "14: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 14, + #[doc = "15: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 15, + #[doc = "16: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 16, + #[doc = "17: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 17, + #[doc = "18: TCC1 Overflow Trigger"] + TCC1_OVF = 18, + #[doc = "19: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 19, + #[doc = "20: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 20, + #[doc = "21: TCC2 Overflow Trigger"] + TCC2_OVF = 21, + #[doc = "22: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 22, + #[doc = "23: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 23, + #[doc = "24: TC3 Overflow Trigger"] + TC3_OVF = 24, + #[doc = "25: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 25, + #[doc = "26: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 26, + #[doc = "27: TC4 Overflow Trigger"] + TC4_OVF = 27, + #[doc = "28: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 28, + #[doc = "29: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 29, + #[doc = "30: TC5 Overflow Trigger"] + TC5_OVF = 30, + #[doc = "31: TC5 Match/Compare 0 Trigger"] + TC5_MC0 = 31, + #[doc = "32: TC5 Match/Compare 1 Trigger"] + TC5_MC1 = 32, + #[doc = "33: TC6 Overflow Trigger"] + TC6_OVF = 33, + #[doc = "34: TC6 Match/Compare 0 Trigger"] + TC6_MC0 = 34, + #[doc = "35: TC6 Match/Compare 1 Trigger"] + TC6_MC1 = 35, + #[doc = "36: TC7 Overflow Trigger"] + TC7_OVF = 36, + #[doc = "37: TC7 Match/Compare 0 Trigger"] + TC7_MC0 = 37, + #[doc = "38: TC7 Match/Compare 1 Trigger"] + TC7_MC1 = 38, + #[doc = "39: ADC Result Ready Trigger"] + ADC_RESRDY = 39, + #[doc = "40: DAC Empty Trigger"] + DAC_EMPTY = 40, + #[doc = "41: I2S RX 0 Trigger"] + I2S_RX_0 = 41, + #[doc = "42: I2S RX 1 Trigger"] + I2S_RX_1 = 42, + #[doc = "43: I2S TX 0 Trigger"] + I2S_TX_0 = 43, + #[doc = "44: I2S TX 1 Trigger"] + I2S_TX_1 = 44, + #[doc = "45: TCC3 Overflow Trigger"] + TCC3_OVF = 45, + #[doc = "46: TCC3 Match/Compare 0 Trigger"] + TCC3_MC0 = 46, + #[doc = "47: TCC3 Match/Compare 1 Trigger"] + TCC3_MC1 = 47, + #[doc = "48: Match/Compare 2 Trigger"] + TCC3_MC2 = 48, + #[doc = "49: Match/Compare 3 Trigger"] + TCC3_MC3 = 49, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Peripheral Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::SERCOM0_RX), + 2 => Some(TRIGSRC_A::SERCOM0_TX), + 3 => Some(TRIGSRC_A::SERCOM1_RX), + 4 => Some(TRIGSRC_A::SERCOM1_TX), + 5 => Some(TRIGSRC_A::SERCOM2_RX), + 6 => Some(TRIGSRC_A::SERCOM2_TX), + 7 => Some(TRIGSRC_A::SERCOM3_RX), + 8 => Some(TRIGSRC_A::SERCOM3_TX), + 9 => Some(TRIGSRC_A::SERCOM4_RX), + 10 => Some(TRIGSRC_A::SERCOM4_TX), + 11 => Some(TRIGSRC_A::SERCOM5_RX), + 12 => Some(TRIGSRC_A::SERCOM5_TX), + 13 => Some(TRIGSRC_A::TCC0_OVF), + 14 => Some(TRIGSRC_A::TCC0_MC0), + 15 => Some(TRIGSRC_A::TCC0_MC1), + 16 => Some(TRIGSRC_A::TCC0_MC2), + 17 => Some(TRIGSRC_A::TCC0_MC3), + 18 => Some(TRIGSRC_A::TCC1_OVF), + 19 => Some(TRIGSRC_A::TCC1_MC0), + 20 => Some(TRIGSRC_A::TCC1_MC1), + 21 => Some(TRIGSRC_A::TCC2_OVF), + 22 => Some(TRIGSRC_A::TCC2_MC0), + 23 => Some(TRIGSRC_A::TCC2_MC1), + 24 => Some(TRIGSRC_A::TC3_OVF), + 25 => Some(TRIGSRC_A::TC3_MC0), + 26 => Some(TRIGSRC_A::TC3_MC1), + 27 => Some(TRIGSRC_A::TC4_OVF), + 28 => Some(TRIGSRC_A::TC4_MC0), + 29 => Some(TRIGSRC_A::TC4_MC1), + 30 => Some(TRIGSRC_A::TC5_OVF), + 31 => Some(TRIGSRC_A::TC5_MC0), + 32 => Some(TRIGSRC_A::TC5_MC1), + 33 => Some(TRIGSRC_A::TC6_OVF), + 34 => Some(TRIGSRC_A::TC6_MC0), + 35 => Some(TRIGSRC_A::TC6_MC1), + 36 => Some(TRIGSRC_A::TC7_OVF), + 37 => Some(TRIGSRC_A::TC7_MC0), + 38 => Some(TRIGSRC_A::TC7_MC1), + 39 => Some(TRIGSRC_A::ADC_RESRDY), + 40 => Some(TRIGSRC_A::DAC_EMPTY), + 41 => Some(TRIGSRC_A::I2S_RX_0), + 42 => Some(TRIGSRC_A::I2S_RX_1), + 43 => Some(TRIGSRC_A::I2S_TX_0), + 44 => Some(TRIGSRC_A::I2S_TX_1), + 45 => Some(TRIGSRC_A::TCC3_OVF), + 46 => Some(TRIGSRC_A::TCC3_MC0), + 47 => Some(TRIGSRC_A::TCC3_MC1), + 48 => Some(TRIGSRC_A::TCC3_MC2), + 49 => Some(TRIGSRC_A::TCC3_MC3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `TC5_OVF`"] + #[inline(always)] + pub fn is_tc5_ovf(&self) -> bool { + **self == TRIGSRC_A::TC5_OVF + } + #[doc = "Checks if the value of the field is `TC5_MC0`"] + #[inline(always)] + pub fn is_tc5_mc0(&self) -> bool { + **self == TRIGSRC_A::TC5_MC0 + } + #[doc = "Checks if the value of the field is `TC5_MC1`"] + #[inline(always)] + pub fn is_tc5_mc1(&self) -> bool { + **self == TRIGSRC_A::TC5_MC1 + } + #[doc = "Checks if the value of the field is `TC6_OVF`"] + #[inline(always)] + pub fn is_tc6_ovf(&self) -> bool { + **self == TRIGSRC_A::TC6_OVF + } + #[doc = "Checks if the value of the field is `TC6_MC0`"] + #[inline(always)] + pub fn is_tc6_mc0(&self) -> bool { + **self == TRIGSRC_A::TC6_MC0 + } + #[doc = "Checks if the value of the field is `TC6_MC1`"] + #[inline(always)] + pub fn is_tc6_mc1(&self) -> bool { + **self == TRIGSRC_A::TC6_MC1 + } + #[doc = "Checks if the value of the field is `TC7_OVF`"] + #[inline(always)] + pub fn is_tc7_ovf(&self) -> bool { + **self == TRIGSRC_A::TC7_OVF + } + #[doc = "Checks if the value of the field is `TC7_MC0`"] + #[inline(always)] + pub fn is_tc7_mc0(&self) -> bool { + **self == TRIGSRC_A::TC7_MC0 + } + #[doc = "Checks if the value of the field is `TC7_MC1`"] + #[inline(always)] + pub fn is_tc7_mc1(&self) -> bool { + **self == TRIGSRC_A::TC7_MC1 + } + #[doc = "Checks if the value of the field is `ADC_RESRDY`"] + #[inline(always)] + pub fn is_adc_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `I2S_RX_0`"] + #[inline(always)] + pub fn is_i2s_rx_0(&self) -> bool { + **self == TRIGSRC_A::I2S_RX_0 + } + #[doc = "Checks if the value of the field is `I2S_RX_1`"] + #[inline(always)] + pub fn is_i2s_rx_1(&self) -> bool { + **self == TRIGSRC_A::I2S_RX_1 + } + #[doc = "Checks if the value of the field is `I2S_TX_0`"] + #[inline(always)] + pub fn is_i2s_tx_0(&self) -> bool { + **self == TRIGSRC_A::I2S_TX_0 + } + #[doc = "Checks if the value of the field is `I2S_TX_1`"] + #[inline(always)] + pub fn is_i2s_tx_1(&self) -> bool { + **self == TRIGSRC_A::I2S_TX_1 + } + #[doc = "Checks if the value of the field is `TCC3_OVF`"] + #[inline(always)] + pub fn is_tcc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC3_OVF + } + #[doc = "Checks if the value of the field is `TCC3_MC0`"] + #[inline(always)] + pub fn is_tcc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC0 + } + #[doc = "Checks if the value of the field is `TCC3_MC1`"] + #[inline(always)] + pub fn is_tcc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC1 + } + #[doc = "Checks if the value of the field is `TCC3_MC2`"] + #[inline(always)] + pub fn is_tcc3_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC2 + } + #[doc = "Checks if the value of the field is `TCC3_MC3`"] + #[inline(always)] + pub fn is_tcc3_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC3 + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Peripheral Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "TC5 Overflow Trigger"] + #[inline(always)] + pub fn tc5_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_OVF) + } + #[doc = "TC5 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc5_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC0) + } + #[doc = "TC5 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc5_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC1) + } + #[doc = "TC6 Overflow Trigger"] + #[inline(always)] + pub fn tc6_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_OVF) + } + #[doc = "TC6 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc6_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC0) + } + #[doc = "TC6 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc6_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC1) + } + #[doc = "TC7 Overflow Trigger"] + #[inline(always)] + pub fn tc7_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_OVF) + } + #[doc = "TC7 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc7_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC0) + } + #[doc = "TC7 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc7_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC1) + } + #[doc = "ADC Result Ready Trigger"] + #[inline(always)] + pub fn adc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "I2S RX 0 Trigger"] + #[inline(always)] + pub fn i2s_rx_0(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_RX_0) + } + #[doc = "I2S RX 1 Trigger"] + #[inline(always)] + pub fn i2s_rx_1(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_RX_1) + } + #[doc = "I2S TX 0 Trigger"] + #[inline(always)] + pub fn i2s_tx_0(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_TX_0) + } + #[doc = "I2S TX 1 Trigger"] + #[inline(always)] + pub fn i2s_tx_1(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_TX_1) + } + #[doc = "TCC3 Overflow Trigger"] + #[inline(always)] + pub fn tcc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_OVF) + } + #[doc = "TCC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC0) + } + #[doc = "TCC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC1) + } + #[doc = "Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc3_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC2) + } + #[doc = "Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc3_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Peripheral Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Peripheral Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/chid.rs b/pac/atsamda1e/src/dmac/chid.rs new file mode 100644 index 00000000000..19151d8e10b --- /dev/null +++ b/pac/atsamda1e/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/chintenclr.rs b/pac/atsamda1e/src/dmac/chintenclr.rs new file mode 100644 index 00000000000..e9e3e0d2e41 --- /dev/null +++ b/pac/atsamda1e/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/chintenset.rs b/pac/atsamda1e/src/dmac/chintenset.rs new file mode 100644 index 00000000000..473843d7f81 --- /dev/null +++ b/pac/atsamda1e/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/chintflag.rs b/pac/atsamda1e/src/dmac/chintflag.rs new file mode 100644 index 00000000000..dd8e72546c1 --- /dev/null +++ b/pac/atsamda1e/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/chstatus.rs b/pac/atsamda1e/src/dmac/chstatus.rs new file mode 100644 index 00000000000..f9432e61dab --- /dev/null +++ b/pac/atsamda1e/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/crcchksum.rs b/pac/atsamda1e/src/dmac/crcchksum.rs new file mode 100644 index 00000000000..89eb5b38a09 --- /dev/null +++ b/pac/atsamda1e/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/crcctrl.rs b/pac/atsamda1e/src/dmac/crcctrl.rs new file mode 100644 index 00000000000..a1d022dd9e6 --- /dev/null +++ b/pac/atsamda1e/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: Byte bus access"] + BYTE = 0, + #[doc = "1: Half-word bus access"] + HWORD = 1, + #[doc = "2: Word bus access"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Byte bus access"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "Half-word bus access"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "Word bus access"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/crcdatain.rs b/pac/atsamda1e/src/dmac/crcdatain.rs new file mode 100644 index 00000000000..ca0879a1213 --- /dev/null +++ b/pac/atsamda1e/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/crcstatus.rs b/pac/atsamda1e/src/dmac/crcstatus.rs new file mode 100644 index 00000000000..a132e9d5cd0 --- /dev/null +++ b/pac/atsamda1e/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/ctrl.rs b/pac/atsamda1e/src/dmac/ctrl.rs new file mode 100644 index 00000000000..fabae9d82a6 --- /dev/null +++ b/pac/atsamda1e/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/dbgctrl.rs b/pac/atsamda1e/src/dmac/dbgctrl.rs new file mode 100644 index 00000000000..53636eb2b33 --- /dev/null +++ b/pac/atsamda1e/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/intpend.rs b/pac/atsamda1e/src/dmac/intpend.rs new file mode 100644 index 00000000000..a107c4c32e6 --- /dev/null +++ b/pac/atsamda1e/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/intstatus.rs b/pac/atsamda1e/src/dmac/intstatus.rs new file mode 100644 index 00000000000..74a836f4a2f --- /dev/null +++ b/pac/atsamda1e/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/pendch.rs b/pac/atsamda1e/src/dmac/pendch.rs new file mode 100644 index 00000000000..8bb68ff8fa5 --- /dev/null +++ b/pac/atsamda1e/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/prictrl0.rs b/pac/atsamda1e/src/dmac/prictrl0.rs new file mode 100644 index 00000000000..ad795d0ba68 --- /dev/null +++ b/pac/atsamda1e/src/dmac/prictrl0.rs @@ -0,0 +1,402 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/qosctrl.rs b/pac/atsamda1e/src/dmac/qosctrl.rs new file mode 100644 index 00000000000..2f8906f0614 --- /dev/null +++ b/pac/atsamda1e/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x15"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x15 + } +} diff --git a/pac/atsamda1e/src/dmac/swtrigctrl.rs b/pac/atsamda1e/src/dmac/swtrigctrl.rs new file mode 100644 index 00000000000..8590fef852d --- /dev/null +++ b/pac/atsamda1e/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dmac/wrbaddr.rs b/pac/atsamda1e/src/dmac/wrbaddr.rs new file mode 100644 index 00000000000..ccf2a376b85 --- /dev/null +++ b/pac/atsamda1e/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu.rs b/pac/atsamda1e/src/dsu.rs new file mode 100644 index 00000000000..499c49a0262 --- /dev/null +++ b/pac/atsamda1e/src/dsu.rs @@ -0,0 +1,134 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved8: [u8; 0x0fe4], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved11: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + _reserved13: [u8; 0x0c], + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamda1e/src/dsu/addr.rs b/pac/atsamda1e/src/dsu/addr.rs new file mode 100644 index 00000000000..1e0a7ad719c --- /dev/null +++ b/pac/atsamda1e/src/dsu/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/cid0.rs b/pac/atsamda1e/src/dsu/cid0.rs new file mode 100644 index 00000000000..b3c2373dfc9 --- /dev/null +++ b/pac/atsamda1e/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamda1e/src/dsu/cid1.rs b/pac/atsamda1e/src/dsu/cid1.rs new file mode 100644 index 00000000000..3628ceac64a --- /dev/null +++ b/pac/atsamda1e/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1e/src/dsu/cid2.rs b/pac/atsamda1e/src/dsu/cid2.rs new file mode 100644 index 00000000000..714078d5c43 --- /dev/null +++ b/pac/atsamda1e/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1e/src/dsu/cid3.rs b/pac/atsamda1e/src/dsu/cid3.rs new file mode 100644 index 00000000000..a345af7b516 --- /dev/null +++ b/pac/atsamda1e/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamda1e/src/dsu/ctrl.rs b/pac/atsamda1e/src/dsu/ctrl.rs new file mode 100644 index 00000000000..ab4b0cd332d --- /dev/null +++ b/pac/atsamda1e/src/dsu/ctrl.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Check"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory Built-In Self-Test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Check"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory Built-In Self-Test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/data.rs b/pac/atsamda1e/src/dsu/data.rs new file mode 100644 index 00000000000..193cc49a07f --- /dev/null +++ b/pac/atsamda1e/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/dcc.rs b/pac/atsamda1e/src/dsu/dcc.rs new file mode 100644 index 00000000000..354323a499e --- /dev/null +++ b/pac/atsamda1e/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/did.rs b/pac/atsamda1e/src/dsu/did.rs new file mode 100644 index 00000000000..a2788d59eff --- /dev/null +++ b/pac/atsamda1e/src/dsu/did.rs @@ -0,0 +1,153 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Identification"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERIES` reader - Product Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAMILY` reader - Product Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Identification"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Product Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Product Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1001_156a"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1001_156a + } +} diff --git a/pac/atsamda1e/src/dsu/end.rs b/pac/atsamda1e/src/dsu/end.rs new file mode 100644 index 00000000000..cce2edea2bc --- /dev/null +++ b/pac/atsamda1e/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/entry0.rs b/pac/atsamda1e/src/dsu/entry0.rs new file mode 100644 index 00000000000..d8563990e82 --- /dev/null +++ b/pac/atsamda1e/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamda1e/src/dsu/entry1.rs b/pac/atsamda1e/src/dsu/entry1.rs new file mode 100644 index 00000000000..8a5358aaa93 --- /dev/null +++ b/pac/atsamda1e/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x3002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3002 + } +} diff --git a/pac/atsamda1e/src/dsu/length.rs b/pac/atsamda1e/src/dsu/length.rs new file mode 100644 index 00000000000..2dc771f74df --- /dev/null +++ b/pac/atsamda1e/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/memtype.rs b/pac/atsamda1e/src/dsu/memtype.rs new file mode 100644 index 00000000000..3cc841e2ba7 --- /dev/null +++ b/pac/atsamda1e/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/pid0.rs b/pac/atsamda1e/src/dsu/pid0.rs new file mode 100644 index 00000000000..98028ea6283 --- /dev/null +++ b/pac/atsamda1e/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamda1e/src/dsu/pid1.rs b/pac/atsamda1e/src/dsu/pid1.rs new file mode 100644 index 00000000000..4f94b853507 --- /dev/null +++ b/pac/atsamda1e/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamda1e/src/dsu/pid2.rs b/pac/atsamda1e/src/dsu/pid2.rs new file mode 100644 index 00000000000..d8f8ed10192 --- /dev/null +++ b/pac/atsamda1e/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamda1e/src/dsu/pid3.rs b/pac/atsamda1e/src/dsu/pid3.rs new file mode 100644 index 00000000000..c0a8fb2d7f9 --- /dev/null +++ b/pac/atsamda1e/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/pid4.rs b/pac/atsamda1e/src/dsu/pid4.rs new file mode 100644 index 00000000000..d239852ee8f --- /dev/null +++ b/pac/atsamda1e/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB Count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB Count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/statusa.rs b/pac/atsamda1e/src/dsu/statusa.rs new file mode 100644 index 00000000000..c7b90a13e49 --- /dev/null +++ b/pac/atsamda1e/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/dsu/statusb.rs b/pac/atsamda1e/src/dsu/statusb.rs new file mode 100644 index 00000000000..3dc6ea897d3 --- /dev/null +++ b/pac/atsamda1e/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x10"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1e/src/eic.rs b/pac/atsamda1e/src/eic.rs new file mode 100644 index 00000000000..dcfa8655a9f --- /dev/null +++ b/pac/atsamda1e/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status"] + pub status: crate::Reg, + #[doc = "0x02 - Non-Maskable Interrupt Control"] + pub nmictrl: crate::Reg, + #[doc = "0x03 - Non-Maskable Interrupt Flag Status and Clear"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0c - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x10 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x14 - Wake-Up Enable"] + pub wakeup: crate::Reg, + #[doc = "0x18..0x20 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "Non-Maskable Interrupt Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "Non-Maskable Interrupt Flag Status and Clear"] +pub mod nmiflag; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "WAKEUP register accessor: an alias for `Reg`"] +pub type WAKEUP = crate::Reg; +#[doc = "Wake-Up Enable"] +pub mod wakeup; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamda1e/src/eic/config.rs b/pac/atsamda1e/src/eic/config.rs new file mode 100644 index 00000000000..5223e0514d5 --- /dev/null +++ b/pac/atsamda1e/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense 0 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense 0 Configuration"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense 0 Configuration"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter 0 Enable"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter 0 Enable"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense 1 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense 1 Configuration"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense 1 Configuration"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter 1 Enable"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter 1 Enable"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense 2 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense 2 Configuration"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense 2 Configuration"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter 2 Enable"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter 2 Enable"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense 3 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense 3 Configuration"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense 3 Configuration"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter 3 Enable"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter 3 Enable"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense 4 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense 4 Configuration"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense 4 Configuration"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter 4 Enable"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter 4 Enable"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense 5 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense 5 Configuration"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense 5 Configuration"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter 5 Enable"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter 5 Enable"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense 6 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense 6 Configuration"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense 6 Configuration"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter 6 Enable"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter 6 Enable"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense 7 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense 7 Configuration"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense 7 Configuration"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter 7 Enable"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter 7 Enable"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense 0 Configuration"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter 0 Enable"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense 1 Configuration"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter 1 Enable"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense 2 Configuration"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter 2 Enable"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense 3 Configuration"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter 3 Enable"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense 4 Configuration"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter 4 Enable"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense 5 Configuration"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter 5 Enable"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense 6 Configuration"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter 6 Enable"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense 7 Configuration"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter 7 Enable"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense 0 Configuration"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter 0 Enable"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense 1 Configuration"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter 1 Enable"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense 2 Configuration"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter 2 Enable"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense 3 Configuration"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter 3 Enable"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense 4 Configuration"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter 4 Enable"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense 5 Configuration"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter 5 Enable"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense 6 Configuration"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter 6 Enable"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense 7 Configuration"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter 7 Enable"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/ctrl.rs b/pac/atsamda1e/src/eic/ctrl.rs new file mode 100644 index 00000000000..3d5f7d86a1f --- /dev/null +++ b/pac/atsamda1e/src/eic/ctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/evctrl.rs b/pac/atsamda1e/src/eic/evctrl.rs new file mode 100644 index 00000000000..660952cdc88 --- /dev/null +++ b/pac/atsamda1e/src/eic/evctrl.rs @@ -0,0 +1,818 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO0` reader - External Interrupt 0 Event Output Enable"] +pub struct EXTINTEO0_R(crate::FieldReader); +impl EXTINTEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO0` writer - External Interrupt 0 Event Output Enable"] +pub struct EXTINTEO0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINTEO1` reader - External Interrupt 1 Event Output Enable"] +pub struct EXTINTEO1_R(crate::FieldReader); +impl EXTINTEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO1` writer - External Interrupt 1 Event Output Enable"] +pub struct EXTINTEO1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINTEO2` reader - External Interrupt 2 Event Output Enable"] +pub struct EXTINTEO2_R(crate::FieldReader); +impl EXTINTEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO2` writer - External Interrupt 2 Event Output Enable"] +pub struct EXTINTEO2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINTEO3` reader - External Interrupt 3 Event Output Enable"] +pub struct EXTINTEO3_R(crate::FieldReader); +impl EXTINTEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO3` writer - External Interrupt 3 Event Output Enable"] +pub struct EXTINTEO3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINTEO4` reader - External Interrupt 4 Event Output Enable"] +pub struct EXTINTEO4_R(crate::FieldReader); +impl EXTINTEO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO4` writer - External Interrupt 4 Event Output Enable"] +pub struct EXTINTEO4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINTEO5` reader - External Interrupt 5 Event Output Enable"] +pub struct EXTINTEO5_R(crate::FieldReader); +impl EXTINTEO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO5` writer - External Interrupt 5 Event Output Enable"] +pub struct EXTINTEO5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINTEO6` reader - External Interrupt 6 Event Output Enable"] +pub struct EXTINTEO6_R(crate::FieldReader); +impl EXTINTEO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO6` writer - External Interrupt 6 Event Output Enable"] +pub struct EXTINTEO6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINTEO7` reader - External Interrupt 7 Event Output Enable"] +pub struct EXTINTEO7_R(crate::FieldReader); +impl EXTINTEO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO7` writer - External Interrupt 7 Event Output Enable"] +pub struct EXTINTEO7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINTEO8` reader - External Interrupt 8 Event Output Enable"] +pub struct EXTINTEO8_R(crate::FieldReader); +impl EXTINTEO8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO8` writer - External Interrupt 8 Event Output Enable"] +pub struct EXTINTEO8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINTEO9` reader - External Interrupt 9 Event Output Enable"] +pub struct EXTINTEO9_R(crate::FieldReader); +impl EXTINTEO9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO9` writer - External Interrupt 9 Event Output Enable"] +pub struct EXTINTEO9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINTEO10` reader - External Interrupt 10 Event Output Enable"] +pub struct EXTINTEO10_R(crate::FieldReader); +impl EXTINTEO10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO10` writer - External Interrupt 10 Event Output Enable"] +pub struct EXTINTEO10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINTEO11` reader - External Interrupt 11 Event Output Enable"] +pub struct EXTINTEO11_R(crate::FieldReader); +impl EXTINTEO11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO11` writer - External Interrupt 11 Event Output Enable"] +pub struct EXTINTEO11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINTEO12` reader - External Interrupt 12 Event Output Enable"] +pub struct EXTINTEO12_R(crate::FieldReader); +impl EXTINTEO12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO12` writer - External Interrupt 12 Event Output Enable"] +pub struct EXTINTEO12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINTEO13` reader - External Interrupt 13 Event Output Enable"] +pub struct EXTINTEO13_R(crate::FieldReader); +impl EXTINTEO13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO13` writer - External Interrupt 13 Event Output Enable"] +pub struct EXTINTEO13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINTEO14` reader - External Interrupt 14 Event Output Enable"] +pub struct EXTINTEO14_R(crate::FieldReader); +impl EXTINTEO14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO14` writer - External Interrupt 14 Event Output Enable"] +pub struct EXTINTEO14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINTEO15` reader - External Interrupt 15 Event Output Enable"] +pub struct EXTINTEO15_R(crate::FieldReader); +impl EXTINTEO15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO15` writer - External Interrupt 15 Event Output Enable"] +pub struct EXTINTEO15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] + #[inline(always)] + pub fn extinteo0(&self) -> EXTINTEO0_R { + EXTINTEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] + #[inline(always)] + pub fn extinteo1(&self) -> EXTINTEO1_R { + EXTINTEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] + #[inline(always)] + pub fn extinteo2(&self) -> EXTINTEO2_R { + EXTINTEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] + #[inline(always)] + pub fn extinteo3(&self) -> EXTINTEO3_R { + EXTINTEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] + #[inline(always)] + pub fn extinteo4(&self) -> EXTINTEO4_R { + EXTINTEO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] + #[inline(always)] + pub fn extinteo5(&self) -> EXTINTEO5_R { + EXTINTEO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] + #[inline(always)] + pub fn extinteo6(&self) -> EXTINTEO6_R { + EXTINTEO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] + #[inline(always)] + pub fn extinteo7(&self) -> EXTINTEO7_R { + EXTINTEO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] + #[inline(always)] + pub fn extinteo8(&self) -> EXTINTEO8_R { + EXTINTEO8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] + #[inline(always)] + pub fn extinteo9(&self) -> EXTINTEO9_R { + EXTINTEO9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] + #[inline(always)] + pub fn extinteo10(&self) -> EXTINTEO10_R { + EXTINTEO10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] + #[inline(always)] + pub fn extinteo11(&self) -> EXTINTEO11_R { + EXTINTEO11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] + #[inline(always)] + pub fn extinteo12(&self) -> EXTINTEO12_R { + EXTINTEO12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] + #[inline(always)] + pub fn extinteo13(&self) -> EXTINTEO13_R { + EXTINTEO13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] + #[inline(always)] + pub fn extinteo14(&self) -> EXTINTEO14_R { + EXTINTEO14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] + #[inline(always)] + pub fn extinteo15(&self) -> EXTINTEO15_R { + EXTINTEO15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] + #[inline(always)] + pub fn extinteo0(&mut self) -> EXTINTEO0_W { + EXTINTEO0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] + #[inline(always)] + pub fn extinteo1(&mut self) -> EXTINTEO1_W { + EXTINTEO1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] + #[inline(always)] + pub fn extinteo2(&mut self) -> EXTINTEO2_W { + EXTINTEO2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] + #[inline(always)] + pub fn extinteo3(&mut self) -> EXTINTEO3_W { + EXTINTEO3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] + #[inline(always)] + pub fn extinteo4(&mut self) -> EXTINTEO4_W { + EXTINTEO4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] + #[inline(always)] + pub fn extinteo5(&mut self) -> EXTINTEO5_W { + EXTINTEO5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] + #[inline(always)] + pub fn extinteo6(&mut self) -> EXTINTEO6_W { + EXTINTEO6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] + #[inline(always)] + pub fn extinteo7(&mut self) -> EXTINTEO7_W { + EXTINTEO7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] + #[inline(always)] + pub fn extinteo8(&mut self) -> EXTINTEO8_W { + EXTINTEO8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] + #[inline(always)] + pub fn extinteo9(&mut self) -> EXTINTEO9_W { + EXTINTEO9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] + #[inline(always)] + pub fn extinteo10(&mut self) -> EXTINTEO10_W { + EXTINTEO10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] + #[inline(always)] + pub fn extinteo11(&mut self) -> EXTINTEO11_W { + EXTINTEO11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] + #[inline(always)] + pub fn extinteo12(&mut self) -> EXTINTEO12_W { + EXTINTEO12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] + #[inline(always)] + pub fn extinteo13(&mut self) -> EXTINTEO13_W { + EXTINTEO13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] + #[inline(always)] + pub fn extinteo14(&mut self) -> EXTINTEO14_W { + EXTINTEO14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] + #[inline(always)] + pub fn extinteo15(&mut self) -> EXTINTEO15_W { + EXTINTEO15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/intenclr.rs b/pac/atsamda1e/src/eic/intenclr.rs new file mode 100644 index 00000000000..e8e877b5ed3 --- /dev/null +++ b/pac/atsamda1e/src/eic/intenclr.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0 Enable"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0 Enable"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1 Enable"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1 Enable"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2 Enable"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2 Enable"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3 Enable"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3 Enable"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4 Enable"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4 Enable"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5 Enable"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5 Enable"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6 Enable"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6 Enable"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7 Enable"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7 Enable"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8 Enable"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8 Enable"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9 Enable"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9 Enable"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10 Enable"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10 Enable"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11 Enable"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11 Enable"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12 Enable"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12 Enable"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13 Enable"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13 Enable"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14 Enable"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14 Enable"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15 Enable"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15 Enable"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/intenset.rs b/pac/atsamda1e/src/eic/intenset.rs new file mode 100644 index 00000000000..2ff10d0def2 --- /dev/null +++ b/pac/atsamda1e/src/eic/intenset.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0 Enable"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0 Enable"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1 Enable"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1 Enable"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2 Enable"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2 Enable"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3 Enable"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3 Enable"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4 Enable"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4 Enable"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5 Enable"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5 Enable"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6 Enable"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6 Enable"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7 Enable"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7 Enable"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8 Enable"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8 Enable"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9 Enable"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9 Enable"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10 Enable"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10 Enable"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11 Enable"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11 Enable"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12 Enable"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12 Enable"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13 Enable"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13 Enable"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14 Enable"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14 Enable"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15 Enable"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15 Enable"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/intflag.rs b/pac/atsamda1e/src/eic/intflag.rs new file mode 100644 index 00000000000..057d3868ffd --- /dev/null +++ b/pac/atsamda1e/src/eic/intflag.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/nmictrl.rs b/pac/atsamda1e/src/eic/nmictrl.rs new file mode 100644 index 00000000000..9abdb233a86 --- /dev/null +++ b/pac/atsamda1e/src/eic/nmictrl.rs @@ -0,0 +1,251 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Non-Maskable Interrupt Sense\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - Non-Maskable Interrupt Sense"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - Non-Maskable Interrupt Sense"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/nmiflag.rs b/pac/atsamda1e/src/eic/nmiflag.rs new file mode 100644 index 00000000000..b2e0be1761d --- /dev/null +++ b/pac/atsamda1e/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - Non-Maskable Interrupt"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - Non-Maskable Interrupt"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/status.rs b/pac/atsamda1e/src/eic/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1e/src/eic/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/eic/wakeup.rs b/pac/atsamda1e/src/eic/wakeup.rs new file mode 100644 index 00000000000..2c5d046923a --- /dev/null +++ b/pac/atsamda1e/src/eic/wakeup.rs @@ -0,0 +1,818 @@ +#[doc = "Register `WAKEUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAKEUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WAKEUPEN0` reader - External Interrupt 0 Wake-up Enable"] +pub struct WAKEUPEN0_R(crate::FieldReader); +impl WAKEUPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN0` writer - External Interrupt 0 Wake-up Enable"] +pub struct WAKEUPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `WAKEUPEN1` reader - External Interrupt 1 Wake-up Enable"] +pub struct WAKEUPEN1_R(crate::FieldReader); +impl WAKEUPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN1` writer - External Interrupt 1 Wake-up Enable"] +pub struct WAKEUPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAKEUPEN2` reader - External Interrupt 2 Wake-up Enable"] +pub struct WAKEUPEN2_R(crate::FieldReader); +impl WAKEUPEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN2` writer - External Interrupt 2 Wake-up Enable"] +pub struct WAKEUPEN2_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WAKEUPEN3` reader - External Interrupt 3 Wake-up Enable"] +pub struct WAKEUPEN3_R(crate::FieldReader); +impl WAKEUPEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN3` writer - External Interrupt 3 Wake-up Enable"] +pub struct WAKEUPEN3_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUPEN4` reader - External Interrupt 4 Wake-up Enable"] +pub struct WAKEUPEN4_R(crate::FieldReader); +impl WAKEUPEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN4` writer - External Interrupt 4 Wake-up Enable"] +pub struct WAKEUPEN4_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WAKEUPEN5` reader - External Interrupt 5 Wake-up Enable"] +pub struct WAKEUPEN5_R(crate::FieldReader); +impl WAKEUPEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN5` writer - External Interrupt 5 Wake-up Enable"] +pub struct WAKEUPEN5_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `WAKEUPEN6` reader - External Interrupt 6 Wake-up Enable"] +pub struct WAKEUPEN6_R(crate::FieldReader); +impl WAKEUPEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN6` writer - External Interrupt 6 Wake-up Enable"] +pub struct WAKEUPEN6_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WAKEUPEN7` reader - External Interrupt 7 Wake-up Enable"] +pub struct WAKEUPEN7_R(crate::FieldReader); +impl WAKEUPEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN7` writer - External Interrupt 7 Wake-up Enable"] +pub struct WAKEUPEN7_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WAKEUPEN8` reader - External Interrupt 8 Wake-up Enable"] +pub struct WAKEUPEN8_R(crate::FieldReader); +impl WAKEUPEN8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN8` writer - External Interrupt 8 Wake-up Enable"] +pub struct WAKEUPEN8_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `WAKEUPEN9` reader - External Interrupt 9 Wake-up Enable"] +pub struct WAKEUPEN9_R(crate::FieldReader); +impl WAKEUPEN9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN9` writer - External Interrupt 9 Wake-up Enable"] +pub struct WAKEUPEN9_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `WAKEUPEN10` reader - External Interrupt 10 Wake-up Enable"] +pub struct WAKEUPEN10_R(crate::FieldReader); +impl WAKEUPEN10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN10` writer - External Interrupt 10 Wake-up Enable"] +pub struct WAKEUPEN10_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `WAKEUPEN11` reader - External Interrupt 11 Wake-up Enable"] +pub struct WAKEUPEN11_R(crate::FieldReader); +impl WAKEUPEN11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN11` writer - External Interrupt 11 Wake-up Enable"] +pub struct WAKEUPEN11_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `WAKEUPEN12` reader - External Interrupt 12 Wake-up Enable"] +pub struct WAKEUPEN12_R(crate::FieldReader); +impl WAKEUPEN12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN12` writer - External Interrupt 12 Wake-up Enable"] +pub struct WAKEUPEN12_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `WAKEUPEN13` reader - External Interrupt 13 Wake-up Enable"] +pub struct WAKEUPEN13_R(crate::FieldReader); +impl WAKEUPEN13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN13` writer - External Interrupt 13 Wake-up Enable"] +pub struct WAKEUPEN13_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `WAKEUPEN14` reader - External Interrupt 14 Wake-up Enable"] +pub struct WAKEUPEN14_R(crate::FieldReader); +impl WAKEUPEN14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN14` writer - External Interrupt 14 Wake-up Enable"] +pub struct WAKEUPEN14_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `WAKEUPEN15` reader - External Interrupt 15 Wake-up Enable"] +pub struct WAKEUPEN15_R(crate::FieldReader); +impl WAKEUPEN15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN15` writer - External Interrupt 15 Wake-up Enable"] +pub struct WAKEUPEN15_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen0(&self) -> WAKEUPEN0_R { + WAKEUPEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen1(&self) -> WAKEUPEN1_R { + WAKEUPEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen2(&self) -> WAKEUPEN2_R { + WAKEUPEN2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen3(&self) -> WAKEUPEN3_R { + WAKEUPEN3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen4(&self) -> WAKEUPEN4_R { + WAKEUPEN4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen5(&self) -> WAKEUPEN5_R { + WAKEUPEN5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen6(&self) -> WAKEUPEN6_R { + WAKEUPEN6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen7(&self) -> WAKEUPEN7_R { + WAKEUPEN7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen8(&self) -> WAKEUPEN8_R { + WAKEUPEN8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen9(&self) -> WAKEUPEN9_R { + WAKEUPEN9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen10(&self) -> WAKEUPEN10_R { + WAKEUPEN10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen11(&self) -> WAKEUPEN11_R { + WAKEUPEN11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen12(&self) -> WAKEUPEN12_R { + WAKEUPEN12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen13(&self) -> WAKEUPEN13_R { + WAKEUPEN13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen14(&self) -> WAKEUPEN14_R { + WAKEUPEN14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen15(&self) -> WAKEUPEN15_R { + WAKEUPEN15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen0(&mut self) -> WAKEUPEN0_W { + WAKEUPEN0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen1(&mut self) -> WAKEUPEN1_W { + WAKEUPEN1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen2(&mut self) -> WAKEUPEN2_W { + WAKEUPEN2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen3(&mut self) -> WAKEUPEN3_W { + WAKEUPEN3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen4(&mut self) -> WAKEUPEN4_W { + WAKEUPEN4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen5(&mut self) -> WAKEUPEN5_W { + WAKEUPEN5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen6(&mut self) -> WAKEUPEN6_W { + WAKEUPEN6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen7(&mut self) -> WAKEUPEN7_W { + WAKEUPEN7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen8(&mut self) -> WAKEUPEN8_W { + WAKEUPEN8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen9(&mut self) -> WAKEUPEN9_W { + WAKEUPEN9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen10(&mut self) -> WAKEUPEN10_W { + WAKEUPEN10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen11(&mut self) -> WAKEUPEN11_W { + WAKEUPEN11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen12(&mut self) -> WAKEUPEN12_W { + WAKEUPEN12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen13(&mut self) -> WAKEUPEN13_W { + WAKEUPEN13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen14(&mut self) -> WAKEUPEN14_W { + WAKEUPEN14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen15(&mut self) -> WAKEUPEN15_W { + WAKEUPEN15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Wake-Up Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wakeup](index.html) module"] +pub struct WAKEUP_SPEC; +impl crate::RegisterSpec for WAKEUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wakeup::R](R) reader structure"] +impl crate::Readable for WAKEUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wakeup::W](W) writer structure"] +impl crate::Writable for WAKEUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAKEUP to value 0"] +impl crate::Resettable for WAKEUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/evsys.rs b/pac/atsamda1e/src/evsys.rs new file mode 100644 index 00000000000..73f42bb8158 --- /dev/null +++ b/pac/atsamda1e/src/evsys.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Channel"] + pub channel: crate::Reg, + #[doc = "0x08 - User Multiplexer"] + pub user: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer"] +pub mod user; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; diff --git a/pac/atsamda1e/src/evsys/channel.rs b/pac/atsamda1e/src/evsys/channel.rs new file mode 100644 index 00000000000..e17ac9fdf25 --- /dev/null +++ b/pac/atsamda1e/src/evsys/channel.rs @@ -0,0 +1,398 @@ +#[doc = "Register `CHANNEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `SWEVT` reader - Software Event"] +pub struct SWEVT_R(crate::FieldReader); +impl SWEVT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWEVT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWEVT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWEVT` writer - Software Event"] +pub struct SWEVT_W<'a> { + w: &'a mut W, +} +impl<'a> SWEVT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 26)) | ((value as u32 & 0x03) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Software Event"] + #[inline(always)] + pub fn swevt(&self) -> SWEVT_R { + SWEVT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:25 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 26:27 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 26) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Bit 8 - Software Event"] + #[inline(always)] + pub fn swevt(&mut self) -> SWEVT_W { + SWEVT_W { w: self } + } + #[doc = "Bits 16:22 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 24:25 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 26:27 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL to value 0"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/evsys/chstatus.rs b/pac/atsamda1e/src/evsys/chstatus.rs new file mode 100644 index 00000000000..9f5bba4c55c --- /dev/null +++ b/pac/atsamda1e/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0x000f_00ff"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x000f_00ff + } +} diff --git a/pac/atsamda1e/src/evsys/ctrl.rs b/pac/atsamda1e/src/evsys/ctrl.rs new file mode 100644 index 00000000000..0c1cacd5ec1 --- /dev/null +++ b/pac/atsamda1e/src/evsys/ctrl.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `GCLKREQ` writer - Generic Clock Requests"] +pub struct GCLKREQ_W<'a> { + w: &'a mut W, +} +impl<'a> GCLKREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 4 - Generic Clock Requests"] + #[inline(always)] + pub fn gclkreq(&mut self) -> GCLKREQ_W { + GCLKREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/evsys/intenclr.rs b/pac/atsamda1e/src/evsys/intenclr.rs new file mode 100644 index 00000000000..bb007d3cdd4 --- /dev/null +++ b/pac/atsamda1e/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/evsys/intenset.rs b/pac/atsamda1e/src/evsys/intenset.rs new file mode 100644 index 00000000000..a2c0b908380 --- /dev/null +++ b/pac/atsamda1e/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/evsys/intflag.rs b/pac/atsamda1e/src/evsys/intflag.rs new file mode 100644 index 00000000000..7fac4593d6d --- /dev/null +++ b/pac/atsamda1e/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/evsys/user.rs b/pac/atsamda1e/src/evsys/user.rs new file mode 100644 index 00000000000..06019221dab --- /dev/null +++ b/pac/atsamda1e/src/evsys/user.rs @@ -0,0 +1,176 @@ +#[doc = "Register `USER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `USER` reader - User Multiplexer Selection"] +pub struct USER_R(crate::FieldReader); +impl USER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + USER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USER` writer - User Multiplexer Selection"] +pub struct USER_W<'a> { + w: &'a mut W, +} +impl<'a> USER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Channel Event Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHANNEL_A { + #[doc = "0: No Channel Output Selected"] + _0 = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHANNEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHANNEL_A::_0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == CHANNEL_A::_0 + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHANNEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Channel Output Selected"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(CHANNEL_A::_0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - User Multiplexer Selection"] + #[inline(always)] + pub fn user(&self) -> USER_R { + USER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - User Multiplexer Selection"] + #[inline(always)] + pub fn user(&mut self) -> USER_W { + USER_W { w: self } + } + #[doc = "Bits 8:12 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/gclk.rs b/pac/atsamda1e/src/gclk.rs new file mode 100644 index 00000000000..c8e002f5502 --- /dev/null +++ b/pac/atsamda1e/src/gclk.rs @@ -0,0 +1,34 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status"] + pub status: crate::Reg, + #[doc = "0x02 - Generic Clock Control"] + pub clkctrl: crate::Reg, + #[doc = "0x04 - Generic Clock Generator Control"] + pub genctrl: crate::Reg, + #[doc = "0x08 - Generic Clock Generator Division"] + pub gendiv: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "CLKCTRL register accessor: an alias for `Reg`"] +pub type CLKCTRL = crate::Reg; +#[doc = "Generic Clock Control"] +pub mod clkctrl; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "GENDIV register accessor: an alias for `Reg`"] +pub type GENDIV = crate::Reg; +#[doc = "Generic Clock Generator Division"] +pub mod gendiv; diff --git a/pac/atsamda1e/src/gclk/clkctrl.rs b/pac/atsamda1e/src/gclk/clkctrl.rs new file mode 100644 index 00000000000..513de299ef9 --- /dev/null +++ b/pac/atsamda1e/src/gclk/clkctrl.rs @@ -0,0 +1,865 @@ +#[doc = "Register `CLKCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Selection ID\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ID_A { + #[doc = "0: DFLL48"] + DFLL48 = 0, + #[doc = "1: FDPLL"] + FDPLL = 1, + #[doc = "2: FDPLL32K"] + FDPLL32K = 2, + #[doc = "3: WDT"] + WDT = 3, + #[doc = "4: RTC"] + RTC = 4, + #[doc = "5: EIC"] + EIC = 5, + #[doc = "6: USB"] + USB = 6, + #[doc = "7: EVSYS_0"] + EVSYS_0 = 7, + #[doc = "8: EVSYS_1"] + EVSYS_1 = 8, + #[doc = "9: EVSYS_2"] + EVSYS_2 = 9, + #[doc = "10: EVSYS_3"] + EVSYS_3 = 10, + #[doc = "11: EVSYS_4"] + EVSYS_4 = 11, + #[doc = "12: EVSYS_5"] + EVSYS_5 = 12, + #[doc = "13: EVSYS_6"] + EVSYS_6 = 13, + #[doc = "14: EVSYS_7"] + EVSYS_7 = 14, + #[doc = "15: EVSYS_8"] + EVSYS_8 = 15, + #[doc = "16: EVSYS_9"] + EVSYS_9 = 16, + #[doc = "17: EVSYS_10"] + EVSYS_10 = 17, + #[doc = "18: EVSYS_11"] + EVSYS_11 = 18, + #[doc = "19: SERCOMX_SLOW"] + SERCOMX_SLOW = 19, + #[doc = "20: SERCOM0_CORE"] + SERCOM0_CORE = 20, + #[doc = "21: SERCOM1_CORE"] + SERCOM1_CORE = 21, + #[doc = "22: SERCOM2_CORE"] + SERCOM2_CORE = 22, + #[doc = "23: SERCOM3_CORE"] + SERCOM3_CORE = 23, + #[doc = "24: SERCOM4_CORE"] + SERCOM4_CORE = 24, + #[doc = "25: SERCOM5_CORE"] + SERCOM5_CORE = 25, + #[doc = "26: TCC0_TCC1"] + TCC0_TCC1 = 26, + #[doc = "27: TCC2_TC3"] + TCC2_TC3 = 27, + #[doc = "28: TC4_TC5"] + TC4_TC5 = 28, + #[doc = "29: TC6_TC7"] + TC6_TC7 = 29, + #[doc = "30: ADC"] + ADC = 30, + #[doc = "31: AC_DIG"] + AC_DIG = 31, + #[doc = "32: AC_ANA"] + AC_ANA = 32, + #[doc = "33: DAC"] + DAC = 33, + #[doc = "35: I2S_0"] + I2S_0 = 35, + #[doc = "36: I2S_1"] + I2S_1 = 36, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ID_A) -> Self { + variant as _ + } +} +#[doc = "Field `ID` reader - Generic Clock Selection ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ID_A::DFLL48), + 1 => Some(ID_A::FDPLL), + 2 => Some(ID_A::FDPLL32K), + 3 => Some(ID_A::WDT), + 4 => Some(ID_A::RTC), + 5 => Some(ID_A::EIC), + 6 => Some(ID_A::USB), + 7 => Some(ID_A::EVSYS_0), + 8 => Some(ID_A::EVSYS_1), + 9 => Some(ID_A::EVSYS_2), + 10 => Some(ID_A::EVSYS_3), + 11 => Some(ID_A::EVSYS_4), + 12 => Some(ID_A::EVSYS_5), + 13 => Some(ID_A::EVSYS_6), + 14 => Some(ID_A::EVSYS_7), + 15 => Some(ID_A::EVSYS_8), + 16 => Some(ID_A::EVSYS_9), + 17 => Some(ID_A::EVSYS_10), + 18 => Some(ID_A::EVSYS_11), + 19 => Some(ID_A::SERCOMX_SLOW), + 20 => Some(ID_A::SERCOM0_CORE), + 21 => Some(ID_A::SERCOM1_CORE), + 22 => Some(ID_A::SERCOM2_CORE), + 23 => Some(ID_A::SERCOM3_CORE), + 24 => Some(ID_A::SERCOM4_CORE), + 25 => Some(ID_A::SERCOM5_CORE), + 26 => Some(ID_A::TCC0_TCC1), + 27 => Some(ID_A::TCC2_TC3), + 28 => Some(ID_A::TC4_TC5), + 29 => Some(ID_A::TC6_TC7), + 30 => Some(ID_A::ADC), + 31 => Some(ID_A::AC_DIG), + 32 => Some(ID_A::AC_ANA), + 33 => Some(ID_A::DAC), + 35 => Some(ID_A::I2S_0), + 36 => Some(ID_A::I2S_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DFLL48`"] + #[inline(always)] + pub fn is_dfll48(&self) -> bool { + **self == ID_A::DFLL48 + } + #[doc = "Checks if the value of the field is `FDPLL`"] + #[inline(always)] + pub fn is_fdpll(&self) -> bool { + **self == ID_A::FDPLL + } + #[doc = "Checks if the value of the field is `FDPLL32K`"] + #[inline(always)] + pub fn is_fdpll32k(&self) -> bool { + **self == ID_A::FDPLL32K + } + #[doc = "Checks if the value of the field is `WDT`"] + #[inline(always)] + pub fn is_wdt(&self) -> bool { + **self == ID_A::WDT + } + #[doc = "Checks if the value of the field is `RTC`"] + #[inline(always)] + pub fn is_rtc(&self) -> bool { + **self == ID_A::RTC + } + #[doc = "Checks if the value of the field is `EIC`"] + #[inline(always)] + pub fn is_eic(&self) -> bool { + **self == ID_A::EIC + } + #[doc = "Checks if the value of the field is `USB`"] + #[inline(always)] + pub fn is_usb(&self) -> bool { + **self == ID_A::USB + } + #[doc = "Checks if the value of the field is `EVSYS_0`"] + #[inline(always)] + pub fn is_evsys_0(&self) -> bool { + **self == ID_A::EVSYS_0 + } + #[doc = "Checks if the value of the field is `EVSYS_1`"] + #[inline(always)] + pub fn is_evsys_1(&self) -> bool { + **self == ID_A::EVSYS_1 + } + #[doc = "Checks if the value of the field is `EVSYS_2`"] + #[inline(always)] + pub fn is_evsys_2(&self) -> bool { + **self == ID_A::EVSYS_2 + } + #[doc = "Checks if the value of the field is `EVSYS_3`"] + #[inline(always)] + pub fn is_evsys_3(&self) -> bool { + **self == ID_A::EVSYS_3 + } + #[doc = "Checks if the value of the field is `EVSYS_4`"] + #[inline(always)] + pub fn is_evsys_4(&self) -> bool { + **self == ID_A::EVSYS_4 + } + #[doc = "Checks if the value of the field is `EVSYS_5`"] + #[inline(always)] + pub fn is_evsys_5(&self) -> bool { + **self == ID_A::EVSYS_5 + } + #[doc = "Checks if the value of the field is `EVSYS_6`"] + #[inline(always)] + pub fn is_evsys_6(&self) -> bool { + **self == ID_A::EVSYS_6 + } + #[doc = "Checks if the value of the field is `EVSYS_7`"] + #[inline(always)] + pub fn is_evsys_7(&self) -> bool { + **self == ID_A::EVSYS_7 + } + #[doc = "Checks if the value of the field is `EVSYS_8`"] + #[inline(always)] + pub fn is_evsys_8(&self) -> bool { + **self == ID_A::EVSYS_8 + } + #[doc = "Checks if the value of the field is `EVSYS_9`"] + #[inline(always)] + pub fn is_evsys_9(&self) -> bool { + **self == ID_A::EVSYS_9 + } + #[doc = "Checks if the value of the field is `EVSYS_10`"] + #[inline(always)] + pub fn is_evsys_10(&self) -> bool { + **self == ID_A::EVSYS_10 + } + #[doc = "Checks if the value of the field is `EVSYS_11`"] + #[inline(always)] + pub fn is_evsys_11(&self) -> bool { + **self == ID_A::EVSYS_11 + } + #[doc = "Checks if the value of the field is `SERCOMX_SLOW`"] + #[inline(always)] + pub fn is_sercomx_slow(&self) -> bool { + **self == ID_A::SERCOMX_SLOW + } + #[doc = "Checks if the value of the field is `SERCOM0_CORE`"] + #[inline(always)] + pub fn is_sercom0_core(&self) -> bool { + **self == ID_A::SERCOM0_CORE + } + #[doc = "Checks if the value of the field is `SERCOM1_CORE`"] + #[inline(always)] + pub fn is_sercom1_core(&self) -> bool { + **self == ID_A::SERCOM1_CORE + } + #[doc = "Checks if the value of the field is `SERCOM2_CORE`"] + #[inline(always)] + pub fn is_sercom2_core(&self) -> bool { + **self == ID_A::SERCOM2_CORE + } + #[doc = "Checks if the value of the field is `SERCOM3_CORE`"] + #[inline(always)] + pub fn is_sercom3_core(&self) -> bool { + **self == ID_A::SERCOM3_CORE + } + #[doc = "Checks if the value of the field is `SERCOM4_CORE`"] + #[inline(always)] + pub fn is_sercom4_core(&self) -> bool { + **self == ID_A::SERCOM4_CORE + } + #[doc = "Checks if the value of the field is `SERCOM5_CORE`"] + #[inline(always)] + pub fn is_sercom5_core(&self) -> bool { + **self == ID_A::SERCOM5_CORE + } + #[doc = "Checks if the value of the field is `TCC0_TCC1`"] + #[inline(always)] + pub fn is_tcc0_tcc1(&self) -> bool { + **self == ID_A::TCC0_TCC1 + } + #[doc = "Checks if the value of the field is `TCC2_TC3`"] + #[inline(always)] + pub fn is_tcc2_tc3(&self) -> bool { + **self == ID_A::TCC2_TC3 + } + #[doc = "Checks if the value of the field is `TC4_TC5`"] + #[inline(always)] + pub fn is_tc4_tc5(&self) -> bool { + **self == ID_A::TC4_TC5 + } + #[doc = "Checks if the value of the field is `TC6_TC7`"] + #[inline(always)] + pub fn is_tc6_tc7(&self) -> bool { + **self == ID_A::TC6_TC7 + } + #[doc = "Checks if the value of the field is `ADC`"] + #[inline(always)] + pub fn is_adc(&self) -> bool { + **self == ID_A::ADC + } + #[doc = "Checks if the value of the field is `AC_DIG`"] + #[inline(always)] + pub fn is_ac_dig(&self) -> bool { + **self == ID_A::AC_DIG + } + #[doc = "Checks if the value of the field is `AC_ANA`"] + #[inline(always)] + pub fn is_ac_ana(&self) -> bool { + **self == ID_A::AC_ANA + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == ID_A::DAC + } + #[doc = "Checks if the value of the field is `I2S_0`"] + #[inline(always)] + pub fn is_i2s_0(&self) -> bool { + **self == ID_A::I2S_0 + } + #[doc = "Checks if the value of the field is `I2S_1`"] + #[inline(always)] + pub fn is_i2s_1(&self) -> bool { + **self == ID_A::I2S_1 + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Selection ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ID_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DFLL48"] + #[inline(always)] + pub fn dfll48(self) -> &'a mut W { + self.variant(ID_A::DFLL48) + } + #[doc = "FDPLL"] + #[inline(always)] + pub fn fdpll(self) -> &'a mut W { + self.variant(ID_A::FDPLL) + } + #[doc = "FDPLL32K"] + #[inline(always)] + pub fn fdpll32k(self) -> &'a mut W { + self.variant(ID_A::FDPLL32K) + } + #[doc = "WDT"] + #[inline(always)] + pub fn wdt(self) -> &'a mut W { + self.variant(ID_A::WDT) + } + #[doc = "RTC"] + #[inline(always)] + pub fn rtc(self) -> &'a mut W { + self.variant(ID_A::RTC) + } + #[doc = "EIC"] + #[inline(always)] + pub fn eic(self) -> &'a mut W { + self.variant(ID_A::EIC) + } + #[doc = "USB"] + #[inline(always)] + pub fn usb(self) -> &'a mut W { + self.variant(ID_A::USB) + } + #[doc = "EVSYS_0"] + #[inline(always)] + pub fn evsys_0(self) -> &'a mut W { + self.variant(ID_A::EVSYS_0) + } + #[doc = "EVSYS_1"] + #[inline(always)] + pub fn evsys_1(self) -> &'a mut W { + self.variant(ID_A::EVSYS_1) + } + #[doc = "EVSYS_2"] + #[inline(always)] + pub fn evsys_2(self) -> &'a mut W { + self.variant(ID_A::EVSYS_2) + } + #[doc = "EVSYS_3"] + #[inline(always)] + pub fn evsys_3(self) -> &'a mut W { + self.variant(ID_A::EVSYS_3) + } + #[doc = "EVSYS_4"] + #[inline(always)] + pub fn evsys_4(self) -> &'a mut W { + self.variant(ID_A::EVSYS_4) + } + #[doc = "EVSYS_5"] + #[inline(always)] + pub fn evsys_5(self) -> &'a mut W { + self.variant(ID_A::EVSYS_5) + } + #[doc = "EVSYS_6"] + #[inline(always)] + pub fn evsys_6(self) -> &'a mut W { + self.variant(ID_A::EVSYS_6) + } + #[doc = "EVSYS_7"] + #[inline(always)] + pub fn evsys_7(self) -> &'a mut W { + self.variant(ID_A::EVSYS_7) + } + #[doc = "EVSYS_8"] + #[inline(always)] + pub fn evsys_8(self) -> &'a mut W { + self.variant(ID_A::EVSYS_8) + } + #[doc = "EVSYS_9"] + #[inline(always)] + pub fn evsys_9(self) -> &'a mut W { + self.variant(ID_A::EVSYS_9) + } + #[doc = "EVSYS_10"] + #[inline(always)] + pub fn evsys_10(self) -> &'a mut W { + self.variant(ID_A::EVSYS_10) + } + #[doc = "EVSYS_11"] + #[inline(always)] + pub fn evsys_11(self) -> &'a mut W { + self.variant(ID_A::EVSYS_11) + } + #[doc = "SERCOMX_SLOW"] + #[inline(always)] + pub fn sercomx_slow(self) -> &'a mut W { + self.variant(ID_A::SERCOMX_SLOW) + } + #[doc = "SERCOM0_CORE"] + #[inline(always)] + pub fn sercom0_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM0_CORE) + } + #[doc = "SERCOM1_CORE"] + #[inline(always)] + pub fn sercom1_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM1_CORE) + } + #[doc = "SERCOM2_CORE"] + #[inline(always)] + pub fn sercom2_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM2_CORE) + } + #[doc = "SERCOM3_CORE"] + #[inline(always)] + pub fn sercom3_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM3_CORE) + } + #[doc = "SERCOM4_CORE"] + #[inline(always)] + pub fn sercom4_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM4_CORE) + } + #[doc = "SERCOM5_CORE"] + #[inline(always)] + pub fn sercom5_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM5_CORE) + } + #[doc = "TCC0_TCC1"] + #[inline(always)] + pub fn tcc0_tcc1(self) -> &'a mut W { + self.variant(ID_A::TCC0_TCC1) + } + #[doc = "TCC2_TC3"] + #[inline(always)] + pub fn tcc2_tc3(self) -> &'a mut W { + self.variant(ID_A::TCC2_TC3) + } + #[doc = "TC4_TC5"] + #[inline(always)] + pub fn tc4_tc5(self) -> &'a mut W { + self.variant(ID_A::TC4_TC5) + } + #[doc = "TC6_TC7"] + #[inline(always)] + pub fn tc6_tc7(self) -> &'a mut W { + self.variant(ID_A::TC6_TC7) + } + #[doc = "ADC"] + #[inline(always)] + pub fn adc(self) -> &'a mut W { + self.variant(ID_A::ADC) + } + #[doc = "AC_DIG"] + #[inline(always)] + pub fn ac_dig(self) -> &'a mut W { + self.variant(ID_A::AC_DIG) + } + #[doc = "AC_ANA"] + #[inline(always)] + pub fn ac_ana(self) -> &'a mut W { + self.variant(ID_A::AC_ANA) + } + #[doc = "DAC"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(ID_A::DAC) + } + #[doc = "I2S_0"] + #[inline(always)] + pub fn i2s_0(self) -> &'a mut W { + self.variant(ID_A::I2S_0) + } + #[doc = "I2S_1"] + #[inline(always)] + pub fn i2s_1(self) -> &'a mut W { + self.variant(ID_A::I2S_1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLKEN` reader - Clock Enable"] +pub struct CLKEN_R(crate::FieldReader); +impl CLKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKEN` writer - Clock Enable"] +pub struct CLKEN_W<'a> { + w: &'a mut W, +} +impl<'a> CLKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Generic Clock Selection ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:11 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 14 - Clock Enable"] + #[inline(always)] + pub fn clken(&self) -> CLKEN_R { + CLKEN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Generic Clock Selection ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:11 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 14 - Clock Enable"] + #[inline(always)] + pub fn clken(&mut self) -> CLKEN_W { + CLKEN_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkctrl](index.html) module"] +pub struct CLKCTRL_SPEC; +impl crate::RegisterSpec for CLKCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [clkctrl::R](R) reader structure"] +impl crate::Readable for CLKCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkctrl::W](W) writer structure"] +impl crate::Writable for CLKCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKCTRL to value 0"] +impl crate::Resettable for CLKCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/gclk/ctrl.rs b/pac/atsamda1e/src/gclk/ctrl.rs new file mode 100644 index 00000000000..2c4cbd696a1 --- /dev/null +++ b/pac/atsamda1e/src/gclk/ctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/gclk/genctrl.rs b/pac/atsamda1e/src/gclk/genctrl.rs new file mode 100644 index 00000000000..0c339999e03 --- /dev/null +++ b/pac/atsamda1e/src/gclk/genctrl.rs @@ -0,0 +1,609 @@ +#[doc = "Register `GENCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Generic Clock Generator Selection"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Generator Selection"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC8M oscillator output"] + OSC8M = 6, + #[doc = "7: DFLL48M output"] + DFLL48M = 7, + #[doc = "8: DPLL96M output"] + DPLL96M = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::XOSC), + 1 => Some(SRC_A::GCLKIN), + 2 => Some(SRC_A::GCLKGEN1), + 3 => Some(SRC_A::OSCULP32K), + 4 => Some(SRC_A::OSC32K), + 5 => Some(SRC_A::XOSC32K), + 6 => Some(SRC_A::OSC8M), + 7 => Some(SRC_A::DFLL48M), + 8 => Some(SRC_A::DPLL96M), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC8M`"] + #[inline(always)] + pub fn is_osc8m(&self) -> bool { + **self == SRC_A::OSC8M + } + #[doc = "Checks if the value of the field is `DFLL48M`"] + #[inline(always)] + pub fn is_dfll48m(&self) -> bool { + **self == SRC_A::DFLL48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC8M oscillator output"] + #[inline(always)] + pub fn osc8m(self) -> &'a mut W { + self.variant(SRC_A::OSC8M) + } + #[doc = "DFLL48M output"] + #[inline(always)] + pub fn dfll48m(self) -> &'a mut W { + self.variant(SRC_A::DFLL48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:12 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 16 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 17 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 18 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 19 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 20 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 21 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/gclk/gendiv.rs b/pac/atsamda1e/src/gclk/gendiv.rs new file mode 100644 index 00000000000..203d2e384c0 --- /dev/null +++ b/pac/atsamda1e/src/gclk/gendiv.rs @@ -0,0 +1,140 @@ +#[doc = "Register `GENDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Generic Clock Generator Selection"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Generator Selection"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 8)) | ((value as u32 & 0xffff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:23 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 8) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:23 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gendiv](index.html) module"] +pub struct GENDIV_SPEC; +impl crate::RegisterSpec for GENDIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gendiv::R](R) reader structure"] +impl crate::Readable for GENDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gendiv::W](W) writer structure"] +impl crate::Writable for GENDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENDIV to value 0"] +impl crate::Resettable for GENDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/gclk/status.rs b/pac/atsamda1e/src/gclk/status.rs new file mode 100644 index 00000000000..2667b356df2 --- /dev/null +++ b/pac/atsamda1e/src/gclk/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy Status"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy Status"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/generic.rs b/pac/atsamda1e/src/generic.rs new file mode 100644 index 00000000000..76159643acf --- /dev/null +++ b/pac/atsamda1e/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamda1e/src/i2s.rs b/pac/atsamda1e/src/i2s.rs new file mode 100644 index 00000000000..2a81ff75c9f --- /dev/null +++ b/pac/atsamda1e/src/i2s.rs @@ -0,0 +1,58 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04..0x0c - Clock Unit n Control"] + pub clkctrl: [crate::Reg; 2], + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x02], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x18 - Synchronization Status"] + pub syncbusy: crate::Reg, + _reserved6: [u8; 0x06], + #[doc = "0x20..0x28 - Serializer n Control"] + pub serctrl: [crate::Reg; 2], + _reserved7: [u8; 0x08], + #[doc = "0x30..0x38 - Data n"] + pub data: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CLKCTRL register accessor: an alias for `Reg`"] +pub type CLKCTRL = crate::Reg; +#[doc = "Clock Unit n Control"] +pub mod clkctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "SERCTRL register accessor: an alias for `Reg`"] +pub type SERCTRL = crate::Reg; +#[doc = "Serializer n Control"] +pub mod serctrl; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data n"] +pub mod data; diff --git a/pac/atsamda1e/src/i2s/clkctrl.rs b/pac/atsamda1e/src/i2s/clkctrl.rs new file mode 100644 index 00000000000..b2d71698332 --- /dev/null +++ b/pac/atsamda1e/src/i2s/clkctrl.rs @@ -0,0 +1,1013 @@ +#[doc = "Register `CLKCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Slot Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLOTSIZE_A { + #[doc = "0: 8-bit Slot for Clock Unit n"] + _8 = 0, + #[doc = "1: 16-bit Slot for Clock Unit n"] + _16 = 1, + #[doc = "2: 24-bit Slot for Clock Unit n"] + _24 = 2, + #[doc = "3: 32-bit Slot for Clock Unit n"] + _32 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLOTSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLOTSIZE` reader - Slot Size"] +pub struct SLOTSIZE_R(crate::FieldReader); +impl SLOTSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOTSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLOTSIZE_A { + match self.bits { + 0 => SLOTSIZE_A::_8, + 1 => SLOTSIZE_A::_16, + 2 => SLOTSIZE_A::_24, + 3 => SLOTSIZE_A::_32, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SLOTSIZE_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SLOTSIZE_A::_16 + } + #[doc = "Checks if the value of the field is `_24`"] + #[inline(always)] + pub fn is_24(&self) -> bool { + **self == SLOTSIZE_A::_24 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SLOTSIZE_A::_32 + } +} +impl core::ops::Deref for SLOTSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTSIZE` writer - Slot Size"] +pub struct SLOTSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLOTSIZE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_8) + } + #[doc = "16-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_16) + } + #[doc = "24-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _24(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_24) + } + #[doc = "32-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `NBSLOTS` reader - Number of Slots in Frame"] +pub struct NBSLOTS_R(crate::FieldReader); +impl NBSLOTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NBSLOTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NBSLOTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NBSLOTS` writer - Number of Slots in Frame"] +pub struct NBSLOTS_W<'a> { + w: &'a mut W, +} +impl<'a> NBSLOTS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Frame Sync Width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSWIDTH_A { + #[doc = "0: Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"] + SLOT = 0, + #[doc = "1: Frame Sync Pulse is half a Frame wide"] + HALF = 1, + #[doc = "2: Frame Sync Pulse is 1 Bit wide"] + BIT = 2, + #[doc = "3: Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"] + BURST = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSWIDTH_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSWIDTH` reader - Frame Sync Width"] +pub struct FSWIDTH_R(crate::FieldReader); +impl FSWIDTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSWIDTH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSWIDTH_A { + match self.bits { + 0 => FSWIDTH_A::SLOT, + 1 => FSWIDTH_A::HALF, + 2 => FSWIDTH_A::BIT, + 3 => FSWIDTH_A::BURST, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `SLOT`"] + #[inline(always)] + pub fn is_slot(&self) -> bool { + **self == FSWIDTH_A::SLOT + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == FSWIDTH_A::HALF + } + #[doc = "Checks if the value of the field is `BIT`"] + #[inline(always)] + pub fn is_bit_(&self) -> bool { + **self == FSWIDTH_A::BIT + } + #[doc = "Checks if the value of the field is `BURST`"] + #[inline(always)] + pub fn is_burst(&self) -> bool { + **self == FSWIDTH_A::BURST + } +} +impl core::ops::Deref for FSWIDTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSWIDTH` writer - Frame Sync Width"] +pub struct FSWIDTH_W<'a> { + w: &'a mut W, +} +impl<'a> FSWIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FSWIDTH_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"] + #[inline(always)] + pub fn slot(self) -> &'a mut W { + self.variant(FSWIDTH_A::SLOT) + } + #[doc = "Frame Sync Pulse is half a Frame wide"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(FSWIDTH_A::HALF) + } + #[doc = "Frame Sync Pulse is 1 Bit wide"] + #[inline(always)] + pub fn bit_(self) -> &'a mut W { + self.variant(FSWIDTH_A::BIT) + } + #[doc = "Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"] + #[inline(always)] + pub fn burst(self) -> &'a mut W { + self.variant(FSWIDTH_A::BURST) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Data Delay from Frame Sync\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BITDELAY_A { + #[doc = "0: Left Justified (0 Bit Delay)"] + LJ = 0, + #[doc = "1: I2S (1 Bit Delay)"] + I2S = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BITDELAY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BITDELAY` reader - Data Delay from Frame Sync"] +pub struct BITDELAY_R(crate::FieldReader); +impl BITDELAY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BITDELAY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BITDELAY_A { + match self.bits { + false => BITDELAY_A::LJ, + true => BITDELAY_A::I2S, + } + } + #[doc = "Checks if the value of the field is `LJ`"] + #[inline(always)] + pub fn is_lj(&self) -> bool { + **self == BITDELAY_A::LJ + } + #[doc = "Checks if the value of the field is `I2S`"] + #[inline(always)] + pub fn is_i2s(&self) -> bool { + **self == BITDELAY_A::I2S + } +} +impl core::ops::Deref for BITDELAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITDELAY` writer - Data Delay from Frame Sync"] +pub struct BITDELAY_W<'a> { + w: &'a mut W, +} +impl<'a> BITDELAY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BITDELAY_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Left Justified (0 Bit Delay)"] + #[inline(always)] + pub fn lj(self) -> &'a mut W { + self.variant(BITDELAY_A::LJ) + } + #[doc = "I2S (1 Bit Delay)"] + #[inline(always)] + pub fn i2s(self) -> &'a mut W { + self.variant(BITDELAY_A::I2S) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Frame Sync Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FSSEL_A { + #[doc = "0: Divided Serial Clock n is used as Frame Sync n source"] + SCKDIV = 0, + #[doc = "1: FSn input pin is used as Frame Sync n source"] + FSPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FSSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FSSEL` reader - Frame Sync Select"] +pub struct FSSEL_R(crate::FieldReader); +impl FSSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSSEL_A { + match self.bits { + false => FSSEL_A::SCKDIV, + true => FSSEL_A::FSPIN, + } + } + #[doc = "Checks if the value of the field is `SCKDIV`"] + #[inline(always)] + pub fn is_sckdiv(&self) -> bool { + **self == FSSEL_A::SCKDIV + } + #[doc = "Checks if the value of the field is `FSPIN`"] + #[inline(always)] + pub fn is_fspin(&self) -> bool { + **self == FSSEL_A::FSPIN + } +} +impl core::ops::Deref for FSSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSSEL` writer - Frame Sync Select"] +pub struct FSSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FSSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FSSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divided Serial Clock n is used as Frame Sync n source"] + #[inline(always)] + pub fn sckdiv(self) -> &'a mut W { + self.variant(FSSEL_A::SCKDIV) + } + #[doc = "FSn input pin is used as Frame Sync n source"] + #[inline(always)] + pub fn fspin(self) -> &'a mut W { + self.variant(FSSEL_A::FSPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FSINV` reader - Frame Sync Invert"] +pub struct FSINV_R(crate::FieldReader); +impl FSINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSINV` writer - Frame Sync Invert"] +pub struct FSINV_W<'a> { + w: &'a mut W, +} +impl<'a> FSINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Serial Clock Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SCKSEL_A { + #[doc = "0: Divided Master Clock n is used as Serial Clock n source"] + MCKDIV = 0, + #[doc = "1: SCKn input pin is used as Serial Clock n source"] + SCKPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SCKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SCKSEL` reader - Serial Clock Select"] +pub struct SCKSEL_R(crate::FieldReader); +impl SCKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SCKSEL_A { + match self.bits { + false => SCKSEL_A::MCKDIV, + true => SCKSEL_A::SCKPIN, + } + } + #[doc = "Checks if the value of the field is `MCKDIV`"] + #[inline(always)] + pub fn is_mckdiv(&self) -> bool { + **self == SCKSEL_A::MCKDIV + } + #[doc = "Checks if the value of the field is `SCKPIN`"] + #[inline(always)] + pub fn is_sckpin(&self) -> bool { + **self == SCKSEL_A::SCKPIN + } +} +impl core::ops::Deref for SCKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCKSEL` writer - Serial Clock Select"] +pub struct SCKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SCKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SCKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divided Master Clock n is used as Serial Clock n source"] + #[inline(always)] + pub fn mckdiv(self) -> &'a mut W { + self.variant(SCKSEL_A::MCKDIV) + } + #[doc = "SCKn input pin is used as Serial Clock n source"] + #[inline(always)] + pub fn sckpin(self) -> &'a mut W { + self.variant(SCKSEL_A::SCKPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Master Clock Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MCKSEL_A { + #[doc = "0: GCLK_I2S_n is used as Master Clock n source"] + GCLK = 0, + #[doc = "1: MCKn input pin is used as Master Clock n source"] + MCKPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MCKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MCKSEL` reader - Master Clock Select"] +pub struct MCKSEL_R(crate::FieldReader); +impl MCKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MCKSEL_A { + match self.bits { + false => MCKSEL_A::GCLK, + true => MCKSEL_A::MCKPIN, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == MCKSEL_A::GCLK + } + #[doc = "Checks if the value of the field is `MCKPIN`"] + #[inline(always)] + pub fn is_mckpin(&self) -> bool { + **self == MCKSEL_A::MCKPIN + } +} +impl core::ops::Deref for MCKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKSEL` writer - Master Clock Select"] +pub struct MCKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> MCKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MCKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "GCLK_I2S_n is used as Master Clock n source"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(MCKSEL_A::GCLK) + } + #[doc = "MCKn input pin is used as Master Clock n source"] + #[inline(always)] + pub fn mckpin(self) -> &'a mut W { + self.variant(MCKSEL_A::MCKPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCKEN` reader - Master Clock Enable"] +pub struct MCKEN_R(crate::FieldReader); +impl MCKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKEN` writer - Master Clock Enable"] +pub struct MCKEN_W<'a> { + w: &'a mut W, +} +impl<'a> MCKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCKDIV` reader - Master Clock Division Factor"] +pub struct MCKDIV_R(crate::FieldReader); +impl MCKDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MCKDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKDIV` writer - Master Clock Division Factor"] +pub struct MCKDIV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKDIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 19)) | ((value as u32 & 0x1f) << 19); + self.w + } +} +#[doc = "Field `MCKOUTDIV` reader - Master Clock Output Division Factor"] +pub struct MCKOUTDIV_R(crate::FieldReader); +impl MCKOUTDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MCKOUTDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKOUTDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKOUTDIV` writer - Master Clock Output Division Factor"] +pub struct MCKOUTDIV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKOUTDIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `FSOUTINV` reader - Frame Sync Output Invert"] +pub struct FSOUTINV_R(crate::FieldReader); +impl FSOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSOUTINV` writer - Frame Sync Output Invert"] +pub struct FSOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> FSOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `SCKOUTINV` reader - Serial Clock Output Invert"] +pub struct SCKOUTINV_R(crate::FieldReader); +impl SCKOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCKOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCKOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCKOUTINV` writer - Serial Clock Output Invert"] +pub struct SCKOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> SCKOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `MCKOUTINV` reader - Master Clock Output Invert"] +pub struct MCKOUTINV_R(crate::FieldReader); +impl MCKOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKOUTINV` writer - Master Clock Output Invert"] +pub struct MCKOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Slot Size"] + #[inline(always)] + pub fn slotsize(&self) -> SLOTSIZE_R { + SLOTSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:4 - Number of Slots in Frame"] + #[inline(always)] + pub fn nbslots(&self) -> NBSLOTS_R { + NBSLOTS_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bits 5:6 - Frame Sync Width"] + #[inline(always)] + pub fn fswidth(&self) -> FSWIDTH_R { + FSWIDTH_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Data Delay from Frame Sync"] + #[inline(always)] + pub fn bitdelay(&self) -> BITDELAY_R { + BITDELAY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Frame Sync Select"] + #[inline(always)] + pub fn fssel(&self) -> FSSEL_R { + FSSEL_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 11 - Frame Sync Invert"] + #[inline(always)] + pub fn fsinv(&self) -> FSINV_R { + FSINV_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Serial Clock Select"] + #[inline(always)] + pub fn scksel(&self) -> SCKSEL_R { + SCKSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 16 - Master Clock Select"] + #[inline(always)] + pub fn mcksel(&self) -> MCKSEL_R { + MCKSEL_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 18 - Master Clock Enable"] + #[inline(always)] + pub fn mcken(&self) -> MCKEN_R { + MCKEN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bits 19:23 - Master Clock Division Factor"] + #[inline(always)] + pub fn mckdiv(&self) -> MCKDIV_R { + MCKDIV_R::new(((self.bits >> 19) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - Master Clock Output Division Factor"] + #[inline(always)] + pub fn mckoutdiv(&self) -> MCKOUTDIV_R { + MCKOUTDIV_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 29 - Frame Sync Output Invert"] + #[inline(always)] + pub fn fsoutinv(&self) -> FSOUTINV_R { + FSOUTINV_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Serial Clock Output Invert"] + #[inline(always)] + pub fn sckoutinv(&self) -> SCKOUTINV_R { + SCKOUTINV_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Master Clock Output Invert"] + #[inline(always)] + pub fn mckoutinv(&self) -> MCKOUTINV_R { + MCKOUTINV_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Slot Size"] + #[inline(always)] + pub fn slotsize(&mut self) -> SLOTSIZE_W { + SLOTSIZE_W { w: self } + } + #[doc = "Bits 2:4 - Number of Slots in Frame"] + #[inline(always)] + pub fn nbslots(&mut self) -> NBSLOTS_W { + NBSLOTS_W { w: self } + } + #[doc = "Bits 5:6 - Frame Sync Width"] + #[inline(always)] + pub fn fswidth(&mut self) -> FSWIDTH_W { + FSWIDTH_W { w: self } + } + #[doc = "Bit 7 - Data Delay from Frame Sync"] + #[inline(always)] + pub fn bitdelay(&mut self) -> BITDELAY_W { + BITDELAY_W { w: self } + } + #[doc = "Bit 8 - Frame Sync Select"] + #[inline(always)] + pub fn fssel(&mut self) -> FSSEL_W { + FSSEL_W { w: self } + } + #[doc = "Bit 11 - Frame Sync Invert"] + #[inline(always)] + pub fn fsinv(&mut self) -> FSINV_W { + FSINV_W { w: self } + } + #[doc = "Bit 12 - Serial Clock Select"] + #[inline(always)] + pub fn scksel(&mut self) -> SCKSEL_W { + SCKSEL_W { w: self } + } + #[doc = "Bit 16 - Master Clock Select"] + #[inline(always)] + pub fn mcksel(&mut self) -> MCKSEL_W { + MCKSEL_W { w: self } + } + #[doc = "Bit 18 - Master Clock Enable"] + #[inline(always)] + pub fn mcken(&mut self) -> MCKEN_W { + MCKEN_W { w: self } + } + #[doc = "Bits 19:23 - Master Clock Division Factor"] + #[inline(always)] + pub fn mckdiv(&mut self) -> MCKDIV_W { + MCKDIV_W { w: self } + } + #[doc = "Bits 24:28 - Master Clock Output Division Factor"] + #[inline(always)] + pub fn mckoutdiv(&mut self) -> MCKOUTDIV_W { + MCKOUTDIV_W { w: self } + } + #[doc = "Bit 29 - Frame Sync Output Invert"] + #[inline(always)] + pub fn fsoutinv(&mut self) -> FSOUTINV_W { + FSOUTINV_W { w: self } + } + #[doc = "Bit 30 - Serial Clock Output Invert"] + #[inline(always)] + pub fn sckoutinv(&mut self) -> SCKOUTINV_W { + SCKOUTINV_W { w: self } + } + #[doc = "Bit 31 - Master Clock Output Invert"] + #[inline(always)] + pub fn mckoutinv(&mut self) -> MCKOUTINV_W { + MCKOUTINV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Unit n Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkctrl](index.html) module"] +pub struct CLKCTRL_SPEC; +impl crate::RegisterSpec for CLKCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkctrl::R](R) reader structure"] +impl crate::Readable for CLKCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkctrl::W](W) writer structure"] +impl crate::Writable for CLKCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKCTRL[%s] +to value 0"] +impl crate::Resettable for CLKCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/i2s/ctrla.rs b/pac/atsamda1e/src/i2s/ctrla.rs new file mode 100644 index 00000000000..116902b0a11 --- /dev/null +++ b/pac/atsamda1e/src/i2s/ctrla.rs @@ -0,0 +1,348 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CKEN0` reader - Clock Unit 0 Enable"] +pub struct CKEN0_R(crate::FieldReader); +impl CKEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN0` writer - Clock Unit 0 Enable"] +pub struct CKEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CKEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CKEN1` reader - Clock Unit 1 Enable"] +pub struct CKEN1_R(crate::FieldReader); +impl CKEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN1` writer - Clock Unit 1 Enable"] +pub struct CKEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CKEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SEREN0` reader - Serializer 0 Enable"] +pub struct SEREN0_R(crate::FieldReader); +impl SEREN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN0` writer - Serializer 0 Enable"] +pub struct SEREN0_W<'a> { + w: &'a mut W, +} +impl<'a> SEREN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SEREN1` reader - Serializer 1 Enable"] +pub struct SEREN1_R(crate::FieldReader); +impl SEREN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN1` writer - Serializer 1 Enable"] +pub struct SEREN1_W<'a> { + w: &'a mut W, +} +impl<'a> SEREN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Unit 0 Enable"] + #[inline(always)] + pub fn cken0(&self) -> CKEN0_R { + CKEN0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Unit 1 Enable"] + #[inline(always)] + pub fn cken1(&self) -> CKEN1_R { + CKEN1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Serializer 0 Enable"] + #[inline(always)] + pub fn seren0(&self) -> SEREN0_R { + SEREN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Serializer 1 Enable"] + #[inline(always)] + pub fn seren1(&self) -> SEREN1_R { + SEREN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Clock Unit 0 Enable"] + #[inline(always)] + pub fn cken0(&mut self) -> CKEN0_W { + CKEN0_W { w: self } + } + #[doc = "Bit 3 - Clock Unit 1 Enable"] + #[inline(always)] + pub fn cken1(&mut self) -> CKEN1_W { + CKEN1_W { w: self } + } + #[doc = "Bit 4 - Serializer 0 Enable"] + #[inline(always)] + pub fn seren0(&mut self) -> SEREN0_W { + SEREN0_W { w: self } + } + #[doc = "Bit 5 - Serializer 1 Enable"] + #[inline(always)] + pub fn seren1(&mut self) -> SEREN1_W { + SEREN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/i2s/data.rs b/pac/atsamda1e/src/i2s/data.rs new file mode 100644 index 00000000000..6184a1e36a2 --- /dev/null +++ b/pac/atsamda1e/src/i2s/data.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DATA[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Sample Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Sample Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Sample Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Sample Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA[%s] +to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/i2s/intenclr.rs b/pac/atsamda1e/src/i2s/intenclr.rs new file mode 100644 index 00000000000..8bfa22bba98 --- /dev/null +++ b/pac/atsamda1e/src/i2s/intenclr.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/i2s/intenset.rs b/pac/atsamda1e/src/i2s/intenset.rs new file mode 100644 index 00000000000..45473048a4d --- /dev/null +++ b/pac/atsamda1e/src/i2s/intenset.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/i2s/intflag.rs b/pac/atsamda1e/src/i2s/intflag.rs new file mode 100644 index 00000000000..eaedff6ff40 --- /dev/null +++ b/pac/atsamda1e/src/i2s/intflag.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/i2s/serctrl.rs b/pac/atsamda1e/src/i2s/serctrl.rs new file mode 100644 index 00000000000..1c1ab945454 --- /dev/null +++ b/pac/atsamda1e/src/i2s/serctrl.rs @@ -0,0 +1,1622 @@ +#[doc = "Register `SERCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SERCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Serializer Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERMODE_A { + #[doc = "0: Receive"] + RX = 0, + #[doc = "1: Transmit"] + TX = 1, + #[doc = "2: Receive one PDM data on each serial clock edge"] + PDM2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERMODE` reader - Serializer Mode"] +pub struct SERMODE_R(crate::FieldReader); +impl SERMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERMODE_A::RX), + 1 => Some(SERMODE_A::TX), + 2 => Some(SERMODE_A::PDM2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + **self == SERMODE_A::RX + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + **self == SERMODE_A::TX + } + #[doc = "Checks if the value of the field is `PDM2`"] + #[inline(always)] + pub fn is_pdm2(&self) -> bool { + **self == SERMODE_A::PDM2 + } +} +impl core::ops::Deref for SERMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERMODE` writer - Serializer Mode"] +pub struct SERMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SERMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SERMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Receive"] + #[inline(always)] + pub fn rx(self) -> &'a mut W { + self.variant(SERMODE_A::RX) + } + #[doc = "Transmit"] + #[inline(always)] + pub fn tx(self) -> &'a mut W { + self.variant(SERMODE_A::TX) + } + #[doc = "Receive one PDM data on each serial clock edge"] + #[inline(always)] + pub fn pdm2(self) -> &'a mut W { + self.variant(SERMODE_A::PDM2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Line Default Line when Slot Disabled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXDEFAULT_A { + #[doc = "0: Output Default Value is 0"] + ZERO = 0, + #[doc = "1: Output Default Value is 1"] + ONE = 1, + #[doc = "3: Output Default Value is high impedance"] + HIZ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXDEFAULT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXDEFAULT` reader - Line Default Line when Slot Disabled"] +pub struct TXDEFAULT_R(crate::FieldReader); +impl TXDEFAULT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXDEFAULT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXDEFAULT_A::ZERO), + 1 => Some(TXDEFAULT_A::ONE), + 3 => Some(TXDEFAULT_A::HIZ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TXDEFAULT_A::ZERO + } + #[doc = "Checks if the value of the field is `ONE`"] + #[inline(always)] + pub fn is_one(&self) -> bool { + **self == TXDEFAULT_A::ONE + } + #[doc = "Checks if the value of the field is `HIZ`"] + #[inline(always)] + pub fn is_hiz(&self) -> bool { + **self == TXDEFAULT_A::HIZ + } +} +impl core::ops::Deref for TXDEFAULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXDEFAULT` writer - Line Default Line when Slot Disabled"] +pub struct TXDEFAULT_W<'a> { + w: &'a mut W, +} +impl<'a> TXDEFAULT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXDEFAULT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Output Default Value is 0"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TXDEFAULT_A::ZERO) + } + #[doc = "Output Default Value is 1"] + #[inline(always)] + pub fn one(self) -> &'a mut W { + self.variant(TXDEFAULT_A::ONE) + } + #[doc = "Output Default Value is high impedance"] + #[inline(always)] + pub fn hiz(self) -> &'a mut W { + self.variant(TXDEFAULT_A::HIZ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Transmit Data when Underrun\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSAME_A { + #[doc = "0: Zero data transmitted in case of underrun"] + ZERO = 0, + #[doc = "1: Last data transmitted in case of underrun"] + SAME = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSAME_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSAME` reader - Transmit Data when Underrun"] +pub struct TXSAME_R(crate::FieldReader); +impl TXSAME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSAME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSAME_A { + match self.bits { + false => TXSAME_A::ZERO, + true => TXSAME_A::SAME, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TXSAME_A::ZERO + } + #[doc = "Checks if the value of the field is `SAME`"] + #[inline(always)] + pub fn is_same(&self) -> bool { + **self == TXSAME_A::SAME + } +} +impl core::ops::Deref for TXSAME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSAME` writer - Transmit Data when Underrun"] +pub struct TXSAME_W<'a> { + w: &'a mut W, +} +impl<'a> TXSAME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXSAME_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Zero data transmitted in case of underrun"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TXSAME_A::ZERO) + } + #[doc = "Last data transmitted in case of underrun"] + #[inline(always)] + pub fn same(self) -> &'a mut W { + self.variant(TXSAME_A::SAME) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Clock Unit Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSEL_A { + #[doc = "0: Use Clock Unit 0"] + CLK0 = 0, + #[doc = "1: Use Clock Unit 1"] + CLK1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSEL` reader - Clock Unit Selection"] +pub struct CLKSEL_R(crate::FieldReader); +impl CLKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSEL_A { + match self.bits { + false => CLKSEL_A::CLK0, + true => CLKSEL_A::CLK1, + } + } + #[doc = "Checks if the value of the field is `CLK0`"] + #[inline(always)] + pub fn is_clk0(&self) -> bool { + **self == CLKSEL_A::CLK0 + } + #[doc = "Checks if the value of the field is `CLK1`"] + #[inline(always)] + pub fn is_clk1(&self) -> bool { + **self == CLKSEL_A::CLK1 + } +} +impl core::ops::Deref for CLKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSEL` writer - Clock Unit Selection"] +pub struct CLKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Use Clock Unit 0"] + #[inline(always)] + pub fn clk0(self) -> &'a mut W { + self.variant(CLKSEL_A::CLK0) + } + #[doc = "Use Clock Unit 1"] + #[inline(always)] + pub fn clk1(self) -> &'a mut W { + self.variant(CLKSEL_A::CLK1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Data Slot Formatting Adjust\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLOTADJ_A { + #[doc = "0: Data is right adjusted in slot"] + RIGHT = 0, + #[doc = "1: Data is left adjusted in slot"] + LEFT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLOTADJ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLOTADJ` reader - Data Slot Formatting Adjust"] +pub struct SLOTADJ_R(crate::FieldReader); +impl SLOTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTADJ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLOTADJ_A { + match self.bits { + false => SLOTADJ_A::RIGHT, + true => SLOTADJ_A::LEFT, + } + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + **self == SLOTADJ_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + **self == SLOTADJ_A::LEFT + } +} +impl core::ops::Deref for SLOTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTADJ` writer - Data Slot Formatting Adjust"] +pub struct SLOTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTADJ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLOTADJ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Data is right adjusted in slot"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(SLOTADJ_A::RIGHT) + } + #[doc = "Data is left adjusted in slot"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(SLOTADJ_A::LEFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Data Word Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DATASIZE_A { + #[doc = "0: 32 bits"] + _32 = 0, + #[doc = "1: 24 bits"] + _24 = 1, + #[doc = "2: 20 bits"] + _20 = 2, + #[doc = "3: 18 bits"] + _18 = 3, + #[doc = "4: 16 bits"] + _16 = 4, + #[doc = "5: 16 bits compact stereo"] + _16C = 5, + #[doc = "6: 8 bits"] + _8 = 6, + #[doc = "7: 8 bits compact stereo"] + _8C = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATASIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DATASIZE` reader - Data Word Size"] +pub struct DATASIZE_R(crate::FieldReader); +impl DATASIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATASIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATASIZE_A { + match self.bits { + 0 => DATASIZE_A::_32, + 1 => DATASIZE_A::_24, + 2 => DATASIZE_A::_20, + 3 => DATASIZE_A::_18, + 4 => DATASIZE_A::_16, + 5 => DATASIZE_A::_16C, + 6 => DATASIZE_A::_8, + 7 => DATASIZE_A::_8C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == DATASIZE_A::_32 + } + #[doc = "Checks if the value of the field is `_24`"] + #[inline(always)] + pub fn is_24(&self) -> bool { + **self == DATASIZE_A::_24 + } + #[doc = "Checks if the value of the field is `_20`"] + #[inline(always)] + pub fn is_20(&self) -> bool { + **self == DATASIZE_A::_20 + } + #[doc = "Checks if the value of the field is `_18`"] + #[inline(always)] + pub fn is_18(&self) -> bool { + **self == DATASIZE_A::_18 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == DATASIZE_A::_16 + } + #[doc = "Checks if the value of the field is `_16C`"] + #[inline(always)] + pub fn is_16c(&self) -> bool { + **self == DATASIZE_A::_16C + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == DATASIZE_A::_8 + } + #[doc = "Checks if the value of the field is `_8C`"] + #[inline(always)] + pub fn is_8c(&self) -> bool { + **self == DATASIZE_A::_8C + } +} +impl core::ops::Deref for DATASIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATASIZE` writer - Data Word Size"] +pub struct DATASIZE_W<'a> { + w: &'a mut W, +} +impl<'a> DATASIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATASIZE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(DATASIZE_A::_32) + } + #[doc = "24 bits"] + #[inline(always)] + pub fn _24(self) -> &'a mut W { + self.variant(DATASIZE_A::_24) + } + #[doc = "20 bits"] + #[inline(always)] + pub fn _20(self) -> &'a mut W { + self.variant(DATASIZE_A::_20) + } + #[doc = "18 bits"] + #[inline(always)] + pub fn _18(self) -> &'a mut W { + self.variant(DATASIZE_A::_18) + } + #[doc = "16 bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(DATASIZE_A::_16) + } + #[doc = "16 bits compact stereo"] + #[inline(always)] + pub fn _16c(self) -> &'a mut W { + self.variant(DATASIZE_A::_16C) + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(DATASIZE_A::_8) + } + #[doc = "8 bits compact stereo"] + #[inline(always)] + pub fn _8c(self) -> &'a mut W { + self.variant(DATASIZE_A::_8C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Data Word Formatting Adjust\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WORDADJ_A { + #[doc = "0: Data is right adjusted in word"] + RIGHT = 0, + #[doc = "1: Data is left adjusted in word"] + LEFT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WORDADJ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WORDADJ` reader - Data Word Formatting Adjust"] +pub struct WORDADJ_R(crate::FieldReader); +impl WORDADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WORDADJ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WORDADJ_A { + match self.bits { + false => WORDADJ_A::RIGHT, + true => WORDADJ_A::LEFT, + } + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + **self == WORDADJ_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + **self == WORDADJ_A::LEFT + } +} +impl core::ops::Deref for WORDADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WORDADJ` writer - Data Word Formatting Adjust"] +pub struct WORDADJ_W<'a> { + w: &'a mut W, +} +impl<'a> WORDADJ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WORDADJ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Data is right adjusted in word"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(WORDADJ_A::RIGHT) + } + #[doc = "Data is left adjusted in word"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(WORDADJ_A::LEFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Data Formatting Bit Extension\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EXTEND_A { + #[doc = "0: Extend with zeroes"] + ZERO = 0, + #[doc = "1: Extend with ones"] + ONE = 1, + #[doc = "2: Extend with Most Significant Bit"] + MSBIT = 2, + #[doc = "3: Extend with Least Significant Bit"] + LSBIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EXTEND_A) -> Self { + variant as _ + } +} +#[doc = "Field `EXTEND` reader - Data Formatting Bit Extension"] +pub struct EXTEND_R(crate::FieldReader); +impl EXTEND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EXTEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EXTEND_A { + match self.bits { + 0 => EXTEND_A::ZERO, + 1 => EXTEND_A::ONE, + 2 => EXTEND_A::MSBIT, + 3 => EXTEND_A::LSBIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == EXTEND_A::ZERO + } + #[doc = "Checks if the value of the field is `ONE`"] + #[inline(always)] + pub fn is_one(&self) -> bool { + **self == EXTEND_A::ONE + } + #[doc = "Checks if the value of the field is `MSBIT`"] + #[inline(always)] + pub fn is_msbit(&self) -> bool { + **self == EXTEND_A::MSBIT + } + #[doc = "Checks if the value of the field is `LSBIT`"] + #[inline(always)] + pub fn is_lsbit(&self) -> bool { + **self == EXTEND_A::LSBIT + } +} +impl core::ops::Deref for EXTEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTEND` writer - Data Formatting Bit Extension"] +pub struct EXTEND_W<'a> { + w: &'a mut W, +} +impl<'a> EXTEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EXTEND_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Extend with zeroes"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(EXTEND_A::ZERO) + } + #[doc = "Extend with ones"] + #[inline(always)] + pub fn one(self) -> &'a mut W { + self.variant(EXTEND_A::ONE) + } + #[doc = "Extend with Most Significant Bit"] + #[inline(always)] + pub fn msbit(self) -> &'a mut W { + self.variant(EXTEND_A::MSBIT) + } + #[doc = "Extend with Least Significant Bit"] + #[inline(always)] + pub fn lsbit(self) -> &'a mut W { + self.variant(EXTEND_A::LSBIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Data Formatting Bit Reverse\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BITREV_A { + #[doc = "0: Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)"] + MSBIT = 0, + #[doc = "1: Transfer Data Least Significant Bit (LSB) first"] + LSBIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BITREV_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BITREV` reader - Data Formatting Bit Reverse"] +pub struct BITREV_R(crate::FieldReader); +impl BITREV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BITREV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BITREV_A { + match self.bits { + false => BITREV_A::MSBIT, + true => BITREV_A::LSBIT, + } + } + #[doc = "Checks if the value of the field is `MSBIT`"] + #[inline(always)] + pub fn is_msbit(&self) -> bool { + **self == BITREV_A::MSBIT + } + #[doc = "Checks if the value of the field is `LSBIT`"] + #[inline(always)] + pub fn is_lsbit(&self) -> bool { + **self == BITREV_A::LSBIT + } +} +impl core::ops::Deref for BITREV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITREV` writer - Data Formatting Bit Reverse"] +pub struct BITREV_W<'a> { + w: &'a mut W, +} +impl<'a> BITREV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BITREV_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)"] + #[inline(always)] + pub fn msbit(self) -> &'a mut W { + self.variant(BITREV_A::MSBIT) + } + #[doc = "Transfer Data Least Significant Bit (LSB) first"] + #[inline(always)] + pub fn lsbit(self) -> &'a mut W { + self.variant(BITREV_A::LSBIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `SLOTDIS0` reader - Slot 0 Disabled for this Serializer"] +pub struct SLOTDIS0_R(crate::FieldReader); +impl SLOTDIS0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS0` writer - Slot 0 Disabled for this Serializer"] +pub struct SLOTDIS0_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `SLOTDIS1` reader - Slot 1 Disabled for this Serializer"] +pub struct SLOTDIS1_R(crate::FieldReader); +impl SLOTDIS1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS1` writer - Slot 1 Disabled for this Serializer"] +pub struct SLOTDIS1_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `SLOTDIS2` reader - Slot 2 Disabled for this Serializer"] +pub struct SLOTDIS2_R(crate::FieldReader); +impl SLOTDIS2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS2` writer - Slot 2 Disabled for this Serializer"] +pub struct SLOTDIS2_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SLOTDIS3` reader - Slot 3 Disabled for this Serializer"] +pub struct SLOTDIS3_R(crate::FieldReader); +impl SLOTDIS3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS3` writer - Slot 3 Disabled for this Serializer"] +pub struct SLOTDIS3_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SLOTDIS4` reader - Slot 4 Disabled for this Serializer"] +pub struct SLOTDIS4_R(crate::FieldReader); +impl SLOTDIS4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS4` writer - Slot 4 Disabled for this Serializer"] +pub struct SLOTDIS4_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `SLOTDIS5` reader - Slot 5 Disabled for this Serializer"] +pub struct SLOTDIS5_R(crate::FieldReader); +impl SLOTDIS5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS5` writer - Slot 5 Disabled for this Serializer"] +pub struct SLOTDIS5_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `SLOTDIS6` reader - Slot 6 Disabled for this Serializer"] +pub struct SLOTDIS6_R(crate::FieldReader); +impl SLOTDIS6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS6` writer - Slot 6 Disabled for this Serializer"] +pub struct SLOTDIS6_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SLOTDIS7` reader - Slot 7 Disabled for this Serializer"] +pub struct SLOTDIS7_R(crate::FieldReader); +impl SLOTDIS7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS7` writer - Slot 7 Disabled for this Serializer"] +pub struct SLOTDIS7_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Mono Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MONO_A { + #[doc = "0: Normal mode"] + STEREO = 0, + #[doc = "1: Left channel data is duplicated to right channel"] + MONO = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MONO_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MONO` reader - Mono Mode"] +pub struct MONO_R(crate::FieldReader); +impl MONO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MONO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MONO_A { + match self.bits { + false => MONO_A::STEREO, + true => MONO_A::MONO, + } + } + #[doc = "Checks if the value of the field is `STEREO`"] + #[inline(always)] + pub fn is_stereo(&self) -> bool { + **self == MONO_A::STEREO + } + #[doc = "Checks if the value of the field is `MONO`"] + #[inline(always)] + pub fn is_mono(&self) -> bool { + **self == MONO_A::MONO + } +} +impl core::ops::Deref for MONO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONO` writer - Mono Mode"] +pub struct MONO_W<'a> { + w: &'a mut W, +} +impl<'a> MONO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MONO_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Normal mode"] + #[inline(always)] + pub fn stereo(self) -> &'a mut W { + self.variant(MONO_A::STEREO) + } + #[doc = "Left channel data is duplicated to right channel"] + #[inline(always)] + pub fn mono(self) -> &'a mut W { + self.variant(MONO_A::MONO) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Single or Multiple DMA Channels\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DMA_A { + #[doc = "0: Single DMA channel"] + SINGLE = 0, + #[doc = "1: One DMA channel per data channel"] + MULTIPLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA` reader - Single or Multiple DMA Channels"] +pub struct DMA_R(crate::FieldReader); +impl DMA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_A { + match self.bits { + false => DMA_A::SINGLE, + true => DMA_A::MULTIPLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == DMA_A::SINGLE + } + #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[inline(always)] + pub fn is_multiple(&self) -> bool { + **self == DMA_A::MULTIPLE + } +} +impl core::ops::Deref for DMA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMA` writer - Single or Multiple DMA Channels"] +pub struct DMA_W<'a> { + w: &'a mut W, +} +impl<'a> DMA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Single DMA channel"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(DMA_A::SINGLE) + } + #[doc = "One DMA channel per data channel"] + #[inline(always)] + pub fn multiple(self) -> &'a mut W { + self.variant(DMA_A::MULTIPLE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `RXLOOP` reader - Loop-back Test Mode"] +pub struct RXLOOP_R(crate::FieldReader); +impl RXLOOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXLOOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXLOOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXLOOP` writer - Loop-back Test Mode"] +pub struct RXLOOP_W<'a> { + w: &'a mut W, +} +impl<'a> RXLOOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Serializer Mode"] + #[inline(always)] + pub fn sermode(&self) -> SERMODE_R { + SERMODE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Line Default Line when Slot Disabled"] + #[inline(always)] + pub fn txdefault(&self) -> TXDEFAULT_R { + TXDEFAULT_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - Transmit Data when Underrun"] + #[inline(always)] + pub fn txsame(&self) -> TXSAME_R { + TXSAME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Clock Unit Selection"] + #[inline(always)] + pub fn clksel(&self) -> CLKSEL_R { + CLKSEL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Data Slot Formatting Adjust"] + #[inline(always)] + pub fn slotadj(&self) -> SLOTADJ_R { + SLOTADJ_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Data Word Size"] + #[inline(always)] + pub fn datasize(&self) -> DATASIZE_R { + DATASIZE_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Data Word Formatting Adjust"] + #[inline(always)] + pub fn wordadj(&self) -> WORDADJ_R { + WORDADJ_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:14 - Data Formatting Bit Extension"] + #[inline(always)] + pub fn extend(&self) -> EXTEND_R { + EXTEND_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Data Formatting Bit Reverse"] + #[inline(always)] + pub fn bitrev(&self) -> BITREV_R { + BITREV_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Slot 0 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis0(&self) -> SLOTDIS0_R { + SLOTDIS0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Slot 1 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis1(&self) -> SLOTDIS1_R { + SLOTDIS1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Slot 2 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis2(&self) -> SLOTDIS2_R { + SLOTDIS2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Slot 3 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis3(&self) -> SLOTDIS3_R { + SLOTDIS3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Slot 4 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis4(&self) -> SLOTDIS4_R { + SLOTDIS4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Slot 5 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis5(&self) -> SLOTDIS5_R { + SLOTDIS5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Slot 6 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis6(&self) -> SLOTDIS6_R { + SLOTDIS6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slot 7 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis7(&self) -> SLOTDIS7_R { + SLOTDIS7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Mono Mode"] + #[inline(always)] + pub fn mono(&self) -> MONO_R { + MONO_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Single or Multiple DMA Channels"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Loop-back Test Mode"] + #[inline(always)] + pub fn rxloop(&self) -> RXLOOP_R { + RXLOOP_R::new(((self.bits >> 26) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Serializer Mode"] + #[inline(always)] + pub fn sermode(&mut self) -> SERMODE_W { + SERMODE_W { w: self } + } + #[doc = "Bits 2:3 - Line Default Line when Slot Disabled"] + #[inline(always)] + pub fn txdefault(&mut self) -> TXDEFAULT_W { + TXDEFAULT_W { w: self } + } + #[doc = "Bit 4 - Transmit Data when Underrun"] + #[inline(always)] + pub fn txsame(&mut self) -> TXSAME_W { + TXSAME_W { w: self } + } + #[doc = "Bit 5 - Clock Unit Selection"] + #[inline(always)] + pub fn clksel(&mut self) -> CLKSEL_W { + CLKSEL_W { w: self } + } + #[doc = "Bit 7 - Data Slot Formatting Adjust"] + #[inline(always)] + pub fn slotadj(&mut self) -> SLOTADJ_W { + SLOTADJ_W { w: self } + } + #[doc = "Bits 8:10 - Data Word Size"] + #[inline(always)] + pub fn datasize(&mut self) -> DATASIZE_W { + DATASIZE_W { w: self } + } + #[doc = "Bit 12 - Data Word Formatting Adjust"] + #[inline(always)] + pub fn wordadj(&mut self) -> WORDADJ_W { + WORDADJ_W { w: self } + } + #[doc = "Bits 13:14 - Data Formatting Bit Extension"] + #[inline(always)] + pub fn extend(&mut self) -> EXTEND_W { + EXTEND_W { w: self } + } + #[doc = "Bit 15 - Data Formatting Bit Reverse"] + #[inline(always)] + pub fn bitrev(&mut self) -> BITREV_W { + BITREV_W { w: self } + } + #[doc = "Bit 16 - Slot 0 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis0(&mut self) -> SLOTDIS0_W { + SLOTDIS0_W { w: self } + } + #[doc = "Bit 17 - Slot 1 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis1(&mut self) -> SLOTDIS1_W { + SLOTDIS1_W { w: self } + } + #[doc = "Bit 18 - Slot 2 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis2(&mut self) -> SLOTDIS2_W { + SLOTDIS2_W { w: self } + } + #[doc = "Bit 19 - Slot 3 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis3(&mut self) -> SLOTDIS3_W { + SLOTDIS3_W { w: self } + } + #[doc = "Bit 20 - Slot 4 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis4(&mut self) -> SLOTDIS4_W { + SLOTDIS4_W { w: self } + } + #[doc = "Bit 21 - Slot 5 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis5(&mut self) -> SLOTDIS5_W { + SLOTDIS5_W { w: self } + } + #[doc = "Bit 22 - Slot 6 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis6(&mut self) -> SLOTDIS6_W { + SLOTDIS6_W { w: self } + } + #[doc = "Bit 23 - Slot 7 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis7(&mut self) -> SLOTDIS7_W { + SLOTDIS7_W { w: self } + } + #[doc = "Bit 24 - Mono Mode"] + #[inline(always)] + pub fn mono(&mut self) -> MONO_W { + MONO_W { w: self } + } + #[doc = "Bit 25 - Single or Multiple DMA Channels"] + #[inline(always)] + pub fn dma(&mut self) -> DMA_W { + DMA_W { w: self } + } + #[doc = "Bit 26 - Loop-back Test Mode"] + #[inline(always)] + pub fn rxloop(&mut self) -> RXLOOP_W { + RXLOOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Serializer n Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [serctrl](index.html) module"] +pub struct SERCTRL_SPEC; +impl crate::RegisterSpec for SERCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [serctrl::R](R) reader structure"] +impl crate::Readable for SERCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [serctrl::W](W) writer structure"] +impl crate::Writable for SERCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SERCTRL[%s] +to value 0"] +impl crate::Resettable for SERCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/i2s/syncbusy.rs b/pac/atsamda1e/src/i2s/syncbusy.rs new file mode 100644 index 00000000000..46ae5a0c282 --- /dev/null +++ b/pac/atsamda1e/src/i2s/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Status"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN0` reader - Clock Unit 0 Enable Synchronization Status"] +pub struct CKEN0_R(crate::FieldReader); +impl CKEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN1` reader - Clock Unit 1 Enable Synchronization Status"] +pub struct CKEN1_R(crate::FieldReader); +impl CKEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN0` reader - Serializer 0 Enable Synchronization Status"] +pub struct SEREN0_R(crate::FieldReader); +impl SEREN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN1` reader - Serializer 1 Enable Synchronization Status"] +pub struct SEREN1_R(crate::FieldReader); +impl SEREN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA0` reader - Data 0 Synchronization Status"] +pub struct DATA0_R(crate::FieldReader); +impl DATA0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA1` reader - Data 1 Synchronization Status"] +pub struct DATA1_R(crate::FieldReader); +impl DATA1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Status"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Unit 0 Enable Synchronization Status"] + #[inline(always)] + pub fn cken0(&self) -> CKEN0_R { + CKEN0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Unit 1 Enable Synchronization Status"] + #[inline(always)] + pub fn cken1(&self) -> CKEN1_R { + CKEN1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Serializer 0 Enable Synchronization Status"] + #[inline(always)] + pub fn seren0(&self) -> SEREN0_R { + SEREN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Serializer 1 Enable Synchronization Status"] + #[inline(always)] + pub fn seren1(&self) -> SEREN1_R { + SEREN1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Data 0 Synchronization Status"] + #[inline(always)] + pub fn data0(&self) -> DATA0_R { + DATA0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Data 1 Synchronization Status"] + #[inline(always)] + pub fn data1(&self) -> DATA1_R { + DATA1_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/lib.rs b/pac/atsamda1e/src/lib.rs new file mode 100644 index 00000000000..0b0761cef8f --- /dev/null +++ b/pac/atsamda1e/src/lib.rs @@ -0,0 +1,1452 @@ +#![doc = "Peripheral access API for ATSAMDA1E microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn PM(); + fn SYSCTRL(); + fn WDT(); + fn RTC(); + fn EIC(); + fn NVMCTRL(); + fn DMAC(); + fn USB(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn SERCOM4(); + fn SERCOM5(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC3(); + fn TC4(); + fn TC5(); + fn TC6(); + fn TC7(); + fn ADC(); + fn AC(); + fn DAC(); + fn PTC(); + fn I2S(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 28] = [ + Vector { _handler: PM }, + Vector { _handler: SYSCTRL }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: USB }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _handler: SERCOM4 }, + Vector { _handler: SERCOM5 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: TC5 }, + Vector { _handler: TC6 }, + Vector { _handler: TC7 }, + Vector { _handler: ADC }, + Vector { _handler: AC }, + Vector { _handler: DAC }, + Vector { _handler: PTC }, + Vector { _handler: I2S }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - PM"] + PM = 0, + #[doc = "1 - SYSCTRL"] + SYSCTRL = 1, + #[doc = "2 - WDT"] + WDT = 2, + #[doc = "3 - RTC"] + RTC = 3, + #[doc = "4 - EIC"] + EIC = 4, + #[doc = "5 - NVMCTRL"] + NVMCTRL = 5, + #[doc = "6 - DMAC"] + DMAC = 6, + #[doc = "7 - USB"] + USB = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "13 - SERCOM4"] + SERCOM4 = 13, + #[doc = "14 - SERCOM5"] + SERCOM5 = 14, + #[doc = "15 - TCC0"] + TCC0 = 15, + #[doc = "16 - TCC1"] + TCC1 = 16, + #[doc = "17 - TCC2"] + TCC2 = 17, + #[doc = "18 - TC3"] + TC3 = 18, + #[doc = "19 - TC4"] + TC4 = 19, + #[doc = "20 - TC5"] + TC5 = 20, + #[doc = "21 - TC6"] + TC6 = 21, + #[doc = "22 - TC7"] + TC7 = 22, + #[doc = "23 - ADC"] + ADC = 23, + #[doc = "24 - AC"] + AC = 24, + #[doc = "25 - DAC"] + DAC = 25, + #[doc = "26 - PTC"] + PTC = 26, + #[doc = "27 - I2S"] + I2S = 27, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc; +#[doc = "Digital Analog Converter"] +pub struct DAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC {} +impl DAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC { + type Target = dac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC").finish() + } +} +#[doc = "Digital Analog Converter"] +pub mod dac; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct SBMATRIX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SBMATRIX {} +impl SBMATRIX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sbmatrix::RegisterBlock = 0x4100_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sbmatrix::RegisterBlock { + Self::PTR + } +} +impl Deref for SBMATRIX { + type Target = sbmatrix::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SBMATRIX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SBMATRIX").finish() + } +} +#[doc = "HSB Matrix"] +pub mod sbmatrix; +#[doc = "Inter-IC Sound Interface"] +pub struct I2S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S {} +impl I2S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s::RegisterBlock { + Self::PTR + } +} +impl Deref for I2S { + type Target = i2s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S").finish() + } +} +#[doc = "Inter-IC Sound Interface"] +pub mod i2s; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC0 {} +impl PAC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC0 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC0").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac0; +#[doc = "Peripheral Access Controller"] +pub struct PAC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC1 {} +impl PAC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC1 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC1").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub use pac0 as pac1; +#[doc = "Peripheral Access Controller"] +pub struct PAC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC2 {} +impl PAC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC2 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC2").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub use pac0 as pac2; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Serial Communication Interface"] +pub struct SERCOM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM4 {} +impl SERCOM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM4 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM4").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom4; +#[doc = "Serial Communication Interface"] +pub struct SERCOM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM5 {} +impl SERCOM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM5 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM5").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom5; +#[doc = "System Control"] +pub struct SYSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCTRL {} +impl SYSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysctrl::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSCTRL { + type Target = sysctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSCTRL").finish() + } +} +#[doc = "System Control"] +pub mod sysctrl; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc4; +#[doc = "Basic Timer Counter"] +pub struct TC5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC5 {} +impl TC5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC5 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC5").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc5; +#[doc = "Basic Timer Counter"] +pub struct TC6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC6 {} +impl TC6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC6 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC6").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc6; +#[doc = "Basic Timer Counter"] +pub struct TC7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC7 {} +impl TC7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC7 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC7").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc7; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Universal Serial Bus"] +pub struct USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB {} +impl USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb::RegisterBlock = 0x4100_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb::RegisterBlock { + Self::PTR + } +} +impl Deref for USB { + type Target = usb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB").finish() + } +} +#[doc = "Universal Serial Bus"] +pub mod usb; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "DAC"] + pub DAC: DAC, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "SBMATRIX"] + pub SBMATRIX: SBMATRIX, + #[doc = "I2S"] + pub I2S: I2S, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "PAC0"] + pub PAC0: PAC0, + #[doc = "PAC1"] + pub PAC1: PAC1, + #[doc = "PAC2"] + pub PAC2: PAC2, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SERCOM4"] + pub SERCOM4: SERCOM4, + #[doc = "SERCOM5"] + pub SERCOM5: SERCOM5, + #[doc = "SYSCTRL"] + pub SYSCTRL: SYSCTRL, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TC5"] + pub TC5: TC5, + #[doc = "TC6"] + pub TC6: TC6, + #[doc = "TC7"] + pub TC7: TC7, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "USB"] + pub USB: USB, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC: ADC { + _marker: PhantomData, + }, + DAC: DAC { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + SBMATRIX: SBMATRIX { + _marker: PhantomData, + }, + I2S: I2S { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + PAC0: PAC0 { + _marker: PhantomData, + }, + PAC1: PAC1 { + _marker: PhantomData, + }, + PAC2: PAC2 { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SERCOM4: SERCOM4 { + _marker: PhantomData, + }, + SERCOM5: SERCOM5 { + _marker: PhantomData, + }, + SYSCTRL: SYSCTRL { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TC5: TC5 { + _marker: PhantomData, + }, + TC6: TC6 { + _marker: PhantomData, + }, + TC7: TC7 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + USB: USB { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamda1e/src/mtb.rs b/pac/atsamda1e/src/mtb.rs new file mode 100644 index 00000000000..45d81bbf944 --- /dev/null +++ b/pac/atsamda1e/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - CoreSight"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - CoreSight"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - CoreSight"] + pub pid6: crate::Reg, + #[doc = "0xfdc - CoreSight"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - CoreSight"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - CoreSight"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - CoreSight"] + pub pid2: crate::Reg, + #[doc = "0xfec - CoreSight"] + pub pid3: crate::Reg, + #[doc = "0xff0 - CoreSight"] + pub cid0: crate::Reg, + #[doc = "0xff4 - CoreSight"] + pub cid1: crate::Reg, + #[doc = "0xff8 - CoreSight"] + pub cid2: crate::Reg, + #[doc = "0xffc - CoreSight"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid3; diff --git a/pac/atsamda1e/src/mtb/authstatus.rs b/pac/atsamda1e/src/mtb/authstatus.rs new file mode 100644 index 00000000000..6fe441e0554 --- /dev/null +++ b/pac/atsamda1e/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/base.rs b/pac/atsamda1e/src/mtb/base.rs new file mode 100644 index 00000000000..f59b5a97a39 --- /dev/null +++ b/pac/atsamda1e/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/cid0.rs b/pac/atsamda1e/src/mtb/cid0.rs new file mode 100644 index 00000000000..c4b0c0a2f5e --- /dev/null +++ b/pac/atsamda1e/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/cid1.rs b/pac/atsamda1e/src/mtb/cid1.rs new file mode 100644 index 00000000000..628785fae59 --- /dev/null +++ b/pac/atsamda1e/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/cid2.rs b/pac/atsamda1e/src/mtb/cid2.rs new file mode 100644 index 00000000000..cf5be1dab2f --- /dev/null +++ b/pac/atsamda1e/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/cid3.rs b/pac/atsamda1e/src/mtb/cid3.rs new file mode 100644 index 00000000000..f8d299b02a6 --- /dev/null +++ b/pac/atsamda1e/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/claimclr.rs b/pac/atsamda1e/src/mtb/claimclr.rs new file mode 100644 index 00000000000..7d0fa5d487b --- /dev/null +++ b/pac/atsamda1e/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/claimset.rs b/pac/atsamda1e/src/mtb/claimset.rs new file mode 100644 index 00000000000..d5e8ffaa484 --- /dev/null +++ b/pac/atsamda1e/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/devarch.rs b/pac/atsamda1e/src/mtb/devarch.rs new file mode 100644 index 00000000000..b79480753d5 --- /dev/null +++ b/pac/atsamda1e/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/devid.rs b/pac/atsamda1e/src/mtb/devid.rs new file mode 100644 index 00000000000..21c15d95203 --- /dev/null +++ b/pac/atsamda1e/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/devtype.rs b/pac/atsamda1e/src/mtb/devtype.rs new file mode 100644 index 00000000000..c00d66b98a2 --- /dev/null +++ b/pac/atsamda1e/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/flow.rs b/pac/atsamda1e/src/mtb/flow.rs new file mode 100644 index 00000000000..1b94efdb89b --- /dev/null +++ b/pac/atsamda1e/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/itctrl.rs b/pac/atsamda1e/src/mtb/itctrl.rs new file mode 100644 index 00000000000..a48364e0b06 --- /dev/null +++ b/pac/atsamda1e/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/lockaccess.rs b/pac/atsamda1e/src/mtb/lockaccess.rs new file mode 100644 index 00000000000..0400690bead --- /dev/null +++ b/pac/atsamda1e/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/lockstatus.rs b/pac/atsamda1e/src/mtb/lockstatus.rs new file mode 100644 index 00000000000..0c68410c694 --- /dev/null +++ b/pac/atsamda1e/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/master.rs b/pac/atsamda1e/src/mtb/master.rs new file mode 100644 index 00000000000..0190ca1ce90 --- /dev/null +++ b/pac/atsamda1e/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid0.rs b/pac/atsamda1e/src/mtb/pid0.rs new file mode 100644 index 00000000000..a4daa474849 --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid1.rs b/pac/atsamda1e/src/mtb/pid1.rs new file mode 100644 index 00000000000..37353582c84 --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid2.rs b/pac/atsamda1e/src/mtb/pid2.rs new file mode 100644 index 00000000000..c4e6a4b9c2a --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid3.rs b/pac/atsamda1e/src/mtb/pid3.rs new file mode 100644 index 00000000000..be0caeaeb51 --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid4.rs b/pac/atsamda1e/src/mtb/pid4.rs new file mode 100644 index 00000000000..83e65c1f64f --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid5.rs b/pac/atsamda1e/src/mtb/pid5.rs new file mode 100644 index 00000000000..eeffcc6e22a --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid6.rs b/pac/atsamda1e/src/mtb/pid6.rs new file mode 100644 index 00000000000..c3a4bdcb875 --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/pid7.rs b/pac/atsamda1e/src/mtb/pid7.rs new file mode 100644 index 00000000000..c47e91f7717 --- /dev/null +++ b/pac/atsamda1e/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/mtb/position.rs b/pac/atsamda1e/src/mtb/position.rs new file mode 100644 index 00000000000..4bab0425b14 --- /dev/null +++ b/pac/atsamda1e/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl.rs b/pac/atsamda1e/src/nvmctrl.rs new file mode 100644 index 00000000000..0c4b2717337 --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl.rs @@ -0,0 +1,63 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; diff --git a/pac/atsamda1e/src/nvmctrl/addr.rs b/pac/atsamda1e/src/nvmctrl/addr.rs new file mode 100644 index 00000000000..74ed27736da --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/ctrla.rs b/pac/atsamda1e/src/nvmctrl/ctrla.rs new file mode 100644 index 00000000000..89f175771e4 --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/ctrlb.rs b/pac/atsamda1e/src/nvmctrl/ctrlb.rs new file mode 100644 index 00000000000..169445752da --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/ctrlb.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/intenclr.rs b/pac/atsamda1e/src/nvmctrl/intenclr.rs new file mode 100644 index 00000000000..6e7db4b52c9 --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/intenset.rs b/pac/atsamda1e/src/nvmctrl/intenset.rs new file mode 100644 index 00000000000..ba8698e86c3 --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/intflag.rs b/pac/atsamda1e/src/nvmctrl/intflag.rs new file mode 100644 index 00000000000..1b30cdddf25 --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/lock.rs b/pac/atsamda1e/src/nvmctrl/lock.rs new file mode 100644 index 00000000000..dbcf37a8107 --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/param.rs b/pac/atsamda1e/src/nvmctrl/param.rs new file mode 100644 index 00000000000..d9197cf16de --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/nvmctrl/status.rs b/pac/atsamda1e/src/nvmctrl/status.rs new file mode 100644 index 00000000000..ce849015560 --- /dev/null +++ b/pac/atsamda1e/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pac0.rs b/pac/atsamda1e/src/pac0.rs new file mode 100644 index 00000000000..e6ae6be9ca4 --- /dev/null +++ b/pac/atsamda1e/src/pac0.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write Protection Clear"] + pub wpclr: crate::Reg, + #[doc = "0x04 - Write Protection Set"] + pub wpset: crate::Reg, +} +#[doc = "WPCLR register accessor: an alias for `Reg`"] +pub type WPCLR = crate::Reg; +#[doc = "Write Protection Clear"] +pub mod wpclr; +#[doc = "WPSET register accessor: an alias for `Reg`"] +pub type WPSET = crate::Reg; +#[doc = "Write Protection Set"] +pub mod wpset; diff --git a/pac/atsamda1e/src/pac0/wpclr.rs b/pac/atsamda1e/src/pac0/wpclr.rs new file mode 100644 index 00000000000..e6bb7309f42 --- /dev/null +++ b/pac/atsamda1e/src/pac0/wpclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WPCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WPCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WP` reader - Write Protection Clear"] +pub struct WP_R(crate::FieldReader); +impl WP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WP` writer - Write Protection Clear"] +pub struct WP_W<'a> { + w: &'a mut W, +} +impl<'a> WP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff_ffff << 1)) | ((value as u32 & 0x7fff_ffff) << 1); + self.w + } +} +impl R { + #[doc = "Bits 1:31 - Write Protection Clear"] + #[inline(always)] + pub fn wp(&self) -> WP_R { + WP_R::new(((self.bits >> 1) & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 1:31 - Write Protection Clear"] + #[inline(always)] + pub fn wp(&mut self) -> WP_W { + WP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Protection Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpclr](index.html) module"] +pub struct WPCLR_SPEC; +impl crate::RegisterSpec for WPCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wpclr::R](R) reader structure"] +impl crate::Readable for WPCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wpclr::W](W) writer structure"] +impl crate::Writable for WPCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WPCLR to value 0"] +impl crate::Resettable for WPCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pac0/wpset.rs b/pac/atsamda1e/src/pac0/wpset.rs new file mode 100644 index 00000000000..5a85aae2aad --- /dev/null +++ b/pac/atsamda1e/src/pac0/wpset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WPSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WPSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WP` reader - Write Protection Set"] +pub struct WP_R(crate::FieldReader); +impl WP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WP` writer - Write Protection Set"] +pub struct WP_W<'a> { + w: &'a mut W, +} +impl<'a> WP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff_ffff << 1)) | ((value as u32 & 0x7fff_ffff) << 1); + self.w + } +} +impl R { + #[doc = "Bits 1:31 - Write Protection Set"] + #[inline(always)] + pub fn wp(&self) -> WP_R { + WP_R::new(((self.bits >> 1) & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 1:31 - Write Protection Set"] + #[inline(always)] + pub fn wp(&mut self) -> WP_W { + WP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Protection Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpset](index.html) module"] +pub struct WPSET_SPEC; +impl crate::RegisterSpec for WPSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wpset::R](R) reader structure"] +impl crate::Readable for WPSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wpset::W](W) writer structure"] +impl crate::Writable for WPSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WPSET to value 0"] +impl crate::Resettable for WPSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm.rs b/pac/atsamda1e/src/pm.rs new file mode 100644 index 00000000000..2a5e9b74e89 --- /dev/null +++ b/pac/atsamda1e/src/pm.rs @@ -0,0 +1,98 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Sleep Mode"] + pub sleep: crate::Reg, + #[doc = "0x02 - External Reset Controller"] + pub extctrl: crate::Reg, + _reserved3: [u8; 0x05], + #[doc = "0x08 - CPU Clock Select"] + pub cpusel: crate::Reg, + #[doc = "0x09 - APBA Clock Select"] + pub apbasel: crate::Reg, + #[doc = "0x0a - APBB Clock Select"] + pub apbbsel: crate::Reg, + #[doc = "0x0b - APBC Clock Select"] + pub apbcsel: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0x14 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x18 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x1c - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x20 - APBC Mask"] + pub apbcmask: crate::Reg, + _reserved11: [u8; 0x10], + #[doc = "0x34 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x35 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x36 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved14: [u8; 0x01], + #[doc = "0x38 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SLEEP register accessor: an alias for `Reg`"] +pub type SLEEP = crate::Reg; +#[doc = "Sleep Mode"] +pub mod sleep; +#[doc = "EXTCTRL register accessor: an alias for `Reg`"] +pub type EXTCTRL = crate::Reg; +#[doc = "External Reset Controller"] +pub mod extctrl; +#[doc = "CPUSEL register accessor: an alias for `Reg`"] +pub type CPUSEL = crate::Reg; +#[doc = "CPU Clock Select"] +pub mod cpusel; +#[doc = "APBASEL register accessor: an alias for `Reg`"] +pub type APBASEL = crate::Reg; +#[doc = "APBA Clock Select"] +pub mod apbasel; +#[doc = "APBBSEL register accessor: an alias for `Reg`"] +pub type APBBSEL = crate::Reg; +#[doc = "APBB Clock Select"] +pub mod apbbsel; +#[doc = "APBCSEL register accessor: an alias for `Reg`"] +pub type APBCSEL = crate::Reg; +#[doc = "APBC Clock Select"] +pub mod apbcsel; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamda1e/src/pm/ahbmask.rs b/pac/atsamda1e/src/pm/ahbmask.rs new file mode 100644 index 00000000000..4a45a8dcdd6 --- /dev/null +++ b/pac/atsamda1e/src/pm/ahbmask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `USB_` reader - USB AHB Clock Mask"] +pub struct USB__R(crate::FieldReader); +impl USB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USB_` writer - USB AHB Clock Mask"] +pub struct USB__W<'a> { + w: &'a mut W, +} +impl<'a> USB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - USB AHB Clock Mask"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 6 - USB AHB Clock Mask"] + #[inline(always)] + pub fn usb_(&mut self) -> USB__W { + USB__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x7f"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1e/src/pm/apbamask.rs b/pac/atsamda1e/src/pm/apbamask.rs new file mode 100644 index 00000000000..857ab4989c6 --- /dev/null +++ b/pac/atsamda1e/src/pm/apbamask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC0_` reader - PAC0 APB Clock Enable"] +pub struct PAC0__R(crate::FieldReader); +impl PAC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC0_` writer - PAC0 APB Clock Enable"] +pub struct PAC0__W<'a> { + w: &'a mut W, +} +impl<'a> PAC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYSCTRL_` reader - SYSCTRL APB Clock Enable"] +pub struct SYSCTRL__R(crate::FieldReader); +impl SYSCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSCTRL_` writer - SYSCTRL APB Clock Enable"] +pub struct SYSCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> SYSCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC0 APB Clock Enable"] + #[inline(always)] + pub fn pac0_(&self) -> PAC0__R { + PAC0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SYSCTRL APB Clock Enable"] + #[inline(always)] + pub fn sysctrl_(&self) -> SYSCTRL__R { + SYSCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC0 APB Clock Enable"] + #[inline(always)] + pub fn pac0_(&mut self) -> PAC0__W { + PAC0__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - SYSCTRL APB Clock Enable"] + #[inline(always)] + pub fn sysctrl_(&mut self) -> SYSCTRL__W { + SYSCTRL__W { w: self } + } + #[doc = "Bit 3 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 4 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 5 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 6 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x7f"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1e/src/pm/apbasel.rs b/pac/atsamda1e/src/pm/apbasel.rs new file mode 100644 index 00000000000..494b59e7e3a --- /dev/null +++ b/pac/atsamda1e/src/pm/apbasel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBASEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBASEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBA Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBADIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBADIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBADIV` reader - APBA Prescaler Selection"] +pub struct APBADIV_R(crate::FieldReader); +impl APBADIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBADIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBADIV_A { + match self.bits { + 0 => APBADIV_A::DIV1, + 1 => APBADIV_A::DIV2, + 2 => APBADIV_A::DIV4, + 3 => APBADIV_A::DIV8, + 4 => APBADIV_A::DIV16, + 5 => APBADIV_A::DIV32, + 6 => APBADIV_A::DIV64, + 7 => APBADIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBADIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBADIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBADIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBADIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBADIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBADIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBADIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBADIV_A::DIV128 + } +} +impl core::ops::Deref for APBADIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBADIV` writer - APBA Prescaler Selection"] +pub struct APBADIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBADIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBADIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBADIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBADIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBADIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBADIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBADIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBADIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBADIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBADIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBA Prescaler Selection"] + #[inline(always)] + pub fn apbadiv(&self) -> APBADIV_R { + APBADIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBA Prescaler Selection"] + #[inline(always)] + pub fn apbadiv(&mut self) -> APBADIV_W { + APBADIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbasel](index.html) module"] +pub struct APBASEL_SPEC; +impl crate::RegisterSpec for APBASEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbasel::R](R) reader structure"] +impl crate::Readable for APBASEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbasel::W](W) writer structure"] +impl crate::Writable for APBASEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBASEL to value 0"] +impl crate::Resettable for APBASEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/apbbmask.rs b/pac/atsamda1e/src/pm/apbbmask.rs new file mode 100644 index 00000000000..92e2c404c22 --- /dev/null +++ b/pac/atsamda1e/src/pm/apbbmask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC1_` reader - PAC1 APB Clock Enable"] +pub struct PAC1__R(crate::FieldReader); +impl PAC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC1_` writer - PAC1 APB Clock Enable"] +pub struct PAC1__W<'a> { + w: &'a mut W, +} +impl<'a> PAC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Clock Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC APB Clock Enable"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `USB_` reader - USB APB Clock Enable"] +pub struct USB__R(crate::FieldReader); +impl USB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USB_` writer - USB APB Clock Enable"] +pub struct USB__W<'a> { + w: &'a mut W, +} +impl<'a> USB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HMATRIX_` reader - HMATRIX APB Clock Enable"] +pub struct HMATRIX__R(crate::FieldReader); +impl HMATRIX__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIX__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIX__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIX_` writer - HMATRIX APB Clock Enable"] +pub struct HMATRIX__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIX__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC1 APB Clock Enable"] + #[inline(always)] + pub fn pac1_(&self) -> PAC1__R { + PAC1__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DMAC APB Clock Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - USB APB Clock Enable"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HMATRIX APB Clock Enable"] + #[inline(always)] + pub fn hmatrix_(&self) -> HMATRIX__R { + HMATRIX__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC1 APB Clock Enable"] + #[inline(always)] + pub fn pac1_(&mut self) -> PAC1__W { + PAC1__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 4 - DMAC APB Clock Enable"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 5 - USB APB Clock Enable"] + #[inline(always)] + pub fn usb_(&mut self) -> USB__W { + USB__W { w: self } + } + #[doc = "Bit 6 - HMATRIX APB Clock Enable"] + #[inline(always)] + pub fn hmatrix_(&mut self) -> HMATRIX__W { + HMATRIX__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x7f"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1e/src/pm/apbbsel.rs b/pac/atsamda1e/src/pm/apbbsel.rs new file mode 100644 index 00000000000..a935873b629 --- /dev/null +++ b/pac/atsamda1e/src/pm/apbbsel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBBSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBB Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBBDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBBDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBBDIV` reader - APBB Prescaler Selection"] +pub struct APBBDIV_R(crate::FieldReader); +impl APBBDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBBDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBBDIV_A { + match self.bits { + 0 => APBBDIV_A::DIV1, + 1 => APBBDIV_A::DIV2, + 2 => APBBDIV_A::DIV4, + 3 => APBBDIV_A::DIV8, + 4 => APBBDIV_A::DIV16, + 5 => APBBDIV_A::DIV32, + 6 => APBBDIV_A::DIV64, + 7 => APBBDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBBDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBBDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBBDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBBDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBBDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBBDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBBDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBBDIV_A::DIV128 + } +} +impl core::ops::Deref for APBBDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBBDIV` writer - APBB Prescaler Selection"] +pub struct APBBDIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBBDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBBDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBB Prescaler Selection"] + #[inline(always)] + pub fn apbbdiv(&self) -> APBBDIV_R { + APBBDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBB Prescaler Selection"] + #[inline(always)] + pub fn apbbdiv(&mut self) -> APBBDIV_W { + APBBDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbsel](index.html) module"] +pub struct APBBSEL_SPEC; +impl crate::RegisterSpec for APBBSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbbsel::R](R) reader structure"] +impl crate::Readable for APBBSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbsel::W](W) writer structure"] +impl crate::Writable for APBBSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBSEL to value 0"] +impl crate::Resettable for APBBSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/apbcmask.rs b/pac/atsamda1e/src/pm/apbcmask.rs new file mode 100644 index 00000000000..78a1439181f --- /dev/null +++ b/pac/atsamda1e/src/pm/apbcmask.rs @@ -0,0 +1,1053 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC2_` reader - PAC2 APB Clock Enable"] +pub struct PAC2__R(crate::FieldReader); +impl PAC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC2_` writer - PAC2 APB Clock Enable"] +pub struct PAC2__W<'a> { + w: &'a mut W, +} +impl<'a> PAC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5 APB Clock Enable"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5 APB Clock Enable"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6 APB Clock Enable"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6 APB Clock Enable"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7 APB Clock Enable"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7 APB Clock Enable"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADC_` reader - ADC APB Clock Enable"] +pub struct ADC__R(crate::FieldReader); +impl ADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_` writer - ADC APB Clock Enable"] +pub struct ADC__W<'a> { + w: &'a mut W, +} +impl<'a> ADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `I2S_` reader - I2S APB Clock Enable"] +pub struct I2S__R(crate::FieldReader); +impl I2S__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2S__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2S__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2S_` writer - I2S APB Clock Enable"] +pub struct I2S__W<'a> { + w: &'a mut W, +} +impl<'a> I2S__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC2 APB Clock Enable"] + #[inline(always)] + pub fn pac2_(&self) -> PAC2__R { + PAC2__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - ADC APB Clock Enable"] + #[inline(always)] + pub fn adc_(&self) -> ADC__R { + ADC__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - I2S APB Clock Enable"] + #[inline(always)] + pub fn i2s_(&self) -> I2S__R { + I2S__R::new(((self.bits >> 20) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC2 APB Clock Enable"] + #[inline(always)] + pub fn pac2_(&mut self) -> PAC2__W { + PAC2__W { w: self } + } + #[doc = "Bit 1 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 2 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 3 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 4 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 5 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 6 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 7 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 8 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 9 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 10 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 12 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 13 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 14 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 15 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Bit 16 - ADC APB Clock Enable"] + #[inline(always)] + pub fn adc_(&mut self) -> ADC__W { + ADC__W { w: self } + } + #[doc = "Bit 17 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 18 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 19 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 20 - I2S APB Clock Enable"] + #[inline(always)] + pub fn i2s_(&mut self) -> I2S__W { + I2S__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0x0001_0000"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0001_0000 + } +} diff --git a/pac/atsamda1e/src/pm/apbcsel.rs b/pac/atsamda1e/src/pm/apbcsel.rs new file mode 100644 index 00000000000..7669148bc17 --- /dev/null +++ b/pac/atsamda1e/src/pm/apbcsel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBCSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBC Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBCDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBCDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBCDIV` reader - APBC Prescaler Selection"] +pub struct APBCDIV_R(crate::FieldReader); +impl APBCDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBCDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBCDIV_A { + match self.bits { + 0 => APBCDIV_A::DIV1, + 1 => APBCDIV_A::DIV2, + 2 => APBCDIV_A::DIV4, + 3 => APBCDIV_A::DIV8, + 4 => APBCDIV_A::DIV16, + 5 => APBCDIV_A::DIV32, + 6 => APBCDIV_A::DIV64, + 7 => APBCDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBCDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBCDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBCDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBCDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBCDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBCDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBCDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBCDIV_A::DIV128 + } +} +impl core::ops::Deref for APBCDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBCDIV` writer - APBC Prescaler Selection"] +pub struct APBCDIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBCDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBCDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBC Prescaler Selection"] + #[inline(always)] + pub fn apbcdiv(&self) -> APBCDIV_R { + APBCDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBC Prescaler Selection"] + #[inline(always)] + pub fn apbcdiv(&mut self) -> APBCDIV_W { + APBCDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcsel](index.html) module"] +pub struct APBCSEL_SPEC; +impl crate::RegisterSpec for APBCSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbcsel::R](R) reader structure"] +impl crate::Readable for APBCSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcsel::W](W) writer structure"] +impl crate::Writable for APBCSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCSEL to value 0"] +impl crate::Resettable for APBCSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/cpusel.rs b/pac/atsamda1e/src/pm/cpusel.rs new file mode 100644 index 00000000000..5637b22ba7a --- /dev/null +++ b/pac/atsamda1e/src/pm/cpusel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Prescaler Selection"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPUDIV_A { + match self.bits { + 0 => CPUDIV_A::DIV1, + 1 => CPUDIV_A::DIV2, + 2 => CPUDIV_A::DIV4, + 3 => CPUDIV_A::DIV8, + 4 => CPUDIV_A::DIV16, + 5 => CPUDIV_A::DIV32, + 6 => CPUDIV_A::DIV64, + 7 => CPUDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Prescaler Selection"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - CPU Prescaler Selection"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - CPU Prescaler Selection"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpusel](index.html) module"] +pub struct CPUSEL_SPEC; +impl crate::RegisterSpec for CPUSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpusel::R](R) reader structure"] +impl crate::Readable for CPUSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpusel::W](W) writer structure"] +impl crate::Writable for CPUSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUSEL to value 0"] +impl crate::Resettable for CPUSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/ctrl.rs b/pac/atsamda1e/src/pm/ctrl.rs new file mode 100644 index 00000000000..bde0e70a237 --- /dev/null +++ b/pac/atsamda1e/src/pm/ctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/extctrl.rs b/pac/atsamda1e/src/pm/extctrl.rs new file mode 100644 index 00000000000..c4f97eedac5 --- /dev/null +++ b/pac/atsamda1e/src/pm/extctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EXTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SETDIS` reader - External Reset Disable"] +pub struct SETDIS_R(crate::FieldReader); +impl SETDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SETDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SETDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SETDIS` writer - External Reset Disable"] +pub struct SETDIS_W<'a> { + w: &'a mut W, +} +impl<'a> SETDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Reset Disable"] + #[inline(always)] + pub fn setdis(&self) -> SETDIS_R { + SETDIS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Reset Disable"] + #[inline(always)] + pub fn setdis(&mut self) -> SETDIS_W { + SETDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Reset Controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extctrl](index.html) module"] +pub struct EXTCTRL_SPEC; +impl crate::RegisterSpec for EXTCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [extctrl::R](R) reader structure"] +impl crate::Readable for EXTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [extctrl::W](W) writer structure"] +impl crate::Writable for EXTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EXTCTRL to value 0"] +impl crate::Resettable for EXTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/intenclr.rs b/pac/atsamda1e/src/pm/intenclr.rs new file mode 100644 index 00000000000..14feb632dbb --- /dev/null +++ b/pac/atsamda1e/src/pm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/intenset.rs b/pac/atsamda1e/src/pm/intenset.rs new file mode 100644 index 00000000000..f01fcc316d9 --- /dev/null +++ b/pac/atsamda1e/src/pm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/intflag.rs b/pac/atsamda1e/src/pm/intflag.rs new file mode 100644 index 00000000000..b5294af3d9d --- /dev/null +++ b/pac/atsamda1e/src/pm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/pm/rcause.rs b/pac/atsamda1e/src/pm/rcause.rs new file mode 100644 index 00000000000..dd192bbc19a --- /dev/null +++ b/pac/atsamda1e/src/pm/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD12` reader - Brown Out 12 Detector Reset"] +pub struct BOD12_R(crate::FieldReader); +impl BOD12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33` reader - Brown Out 33 Detector Reset"] +pub struct BOD33_R(crate::FieldReader); +impl BOD33_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out 12 Detector Reset"] + #[inline(always)] + pub fn bod12(&self) -> BOD12_R { + BOD12_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out 33 Detector Reset"] + #[inline(always)] + pub fn bod33(&self) -> BOD33_R { + BOD33_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0x01"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1e/src/pm/sleep.rs b/pac/atsamda1e/src/pm/sleep.rs new file mode 100644 index 00000000000..c30b443bde1 --- /dev/null +++ b/pac/atsamda1e/src/pm/sleep.rs @@ -0,0 +1,165 @@ +#[doc = "Register `SLEEP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Idle Mode Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDLE_A { + #[doc = "0: The CPU clock domain is stopped"] + CPU = 0, + #[doc = "1: The CPU and AHB clock domains are stopped"] + AHB = 1, + #[doc = "2: The CPU, AHB and APB clock domains are stopped"] + APB = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDLE_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDLE` reader - Idle Mode Configuration"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(IDLE_A::CPU), + 1 => Some(IDLE_A::AHB), + 2 => Some(IDLE_A::APB), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CPU`"] + #[inline(always)] + pub fn is_cpu(&self) -> bool { + **self == IDLE_A::CPU + } + #[doc = "Checks if the value of the field is `AHB`"] + #[inline(always)] + pub fn is_ahb(&self) -> bool { + **self == IDLE_A::AHB + } + #[doc = "Checks if the value of the field is `APB`"] + #[inline(always)] + pub fn is_apb(&self) -> bool { + **self == IDLE_A::APB + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` writer - Idle Mode Configuration"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDLE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The CPU clock domain is stopped"] + #[inline(always)] + pub fn cpu(self) -> &'a mut W { + self.variant(IDLE_A::CPU) + } + #[doc = "The CPU and AHB clock domains are stopped"] + #[inline(always)] + pub fn ahb(self) -> &'a mut W { + self.variant(IDLE_A::AHB) + } + #[doc = "The CPU, AHB and APB clock domains are stopped"] + #[inline(always)] + pub fn apb(self) -> &'a mut W { + self.variant(IDLE_A::APB) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Idle Mode Configuration"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Idle Mode Configuration"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleep](index.html) module"] +pub struct SLEEP_SPEC; +impl crate::RegisterSpec for SLEEP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleep::R](R) reader structure"] +impl crate::Readable for SLEEP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleep::W](W) writer structure"] +impl crate::Writable for SLEEP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEP to value 0"] +impl crate::Resettable for SLEEP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port.rs b/pac/atsamda1e/src/port.rs new file mode 100644 index 00000000000..08e94026e13 --- /dev/null +++ b/pac/atsamda1e/src/port.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + _reserved11: [u8; 0x04], + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamda1e/src/port/group.rs b/pac/atsamda1e/src/port/group.rs new file mode 100644 index 00000000000..42529765a8d --- /dev/null +++ b/pac/atsamda1e/src/port/group.rs @@ -0,0 +1,52 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamda1e/src/port/group/ctrl.rs b/pac/atsamda1e/src/port/group/ctrl.rs new file mode 100644 index 00000000000..4b57cd6fcd2 --- /dev/null +++ b/pac/atsamda1e/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/dir.rs b/pac/atsamda1e/src/port/group/dir.rs new file mode 100644 index 00000000000..36f642e3c16 --- /dev/null +++ b/pac/atsamda1e/src/port/group/dir.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Port Data Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Port Data Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/dirclr.rs b/pac/atsamda1e/src/port/group/dirclr.rs new file mode 100644 index 00000000000..9d125c964aa --- /dev/null +++ b/pac/atsamda1e/src/port/group/dirclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRCLR` reader - Port Data Direction Clear"] +pub struct DIRCLR_R(crate::FieldReader); +impl DIRCLR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRCLR` writer - Port Data Direction Clear"] +pub struct DIRCLR_W<'a> { + w: &'a mut W, +} +impl<'a> DIRCLR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Clear"] + #[inline(always)] + pub fn dirclr(&self) -> DIRCLR_R { + DIRCLR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Clear"] + #[inline(always)] + pub fn dirclr(&mut self) -> DIRCLR_W { + DIRCLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/dirset.rs b/pac/atsamda1e/src/port/group/dirset.rs new file mode 100644 index 00000000000..f0a4679db6b --- /dev/null +++ b/pac/atsamda1e/src/port/group/dirset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRSET` reader - Port Data Direction Set"] +pub struct DIRSET_R(crate::FieldReader); +impl DIRSET_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRSET` writer - Port Data Direction Set"] +pub struct DIRSET_W<'a> { + w: &'a mut W, +} +impl<'a> DIRSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Set"] + #[inline(always)] + pub fn dirset(&self) -> DIRSET_R { + DIRSET_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Set"] + #[inline(always)] + pub fn dirset(&mut self) -> DIRSET_W { + DIRSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/dirtgl.rs b/pac/atsamda1e/src/port/group/dirtgl.rs new file mode 100644 index 00000000000..37339d76c54 --- /dev/null +++ b/pac/atsamda1e/src/port/group/dirtgl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRTGL` reader - Port Data Direction Toggle"] +pub struct DIRTGL_R(crate::FieldReader); +impl DIRTGL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRTGL` writer - Port Data Direction Toggle"] +pub struct DIRTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DIRTGL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Toggle"] + #[inline(always)] + pub fn dirtgl(&self) -> DIRTGL_R { + DIRTGL_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Toggle"] + #[inline(always)] + pub fn dirtgl(&mut self) -> DIRTGL_W { + DIRTGL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/in_.rs b/pac/atsamda1e/src/port/group/in_.rs new file mode 100644 index 00000000000..1e84f070091 --- /dev/null +++ b/pac/atsamda1e/src/port/group/in_.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IN` reader - Port Data Input Value"] +pub struct IN_R(crate::FieldReader); +impl IN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Input Value"] + #[inline(always)] + pub fn in_(&self) -> IN_R { + IN_R::new(self.bits as u32) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/out.rs b/pac/atsamda1e/src/port/group/out.rs new file mode 100644 index 00000000000..48ecaa2358e --- /dev/null +++ b/pac/atsamda1e/src/port/group/out.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUT` reader - Port Data Output Value"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Port Data Output Value"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/outclr.rs b/pac/atsamda1e/src/port/group/outclr.rs new file mode 100644 index 00000000000..3ea8c378ed4 --- /dev/null +++ b/pac/atsamda1e/src/port/group/outclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTCLR` reader - Port Data Output Value Clear"] +pub struct OUTCLR_R(crate::FieldReader); +impl OUTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTCLR` writer - Port Data Output Value Clear"] +pub struct OUTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> OUTCLR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Clear"] + #[inline(always)] + pub fn outclr(&self) -> OUTCLR_R { + OUTCLR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Clear"] + #[inline(always)] + pub fn outclr(&mut self) -> OUTCLR_W { + OUTCLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/outset.rs b/pac/atsamda1e/src/port/group/outset.rs new file mode 100644 index 00000000000..e905e4508b2 --- /dev/null +++ b/pac/atsamda1e/src/port/group/outset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTSET` reader - Port Data Output Value Set"] +pub struct OUTSET_R(crate::FieldReader); +impl OUTSET_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTSET` writer - Port Data Output Value Set"] +pub struct OUTSET_W<'a> { + w: &'a mut W, +} +impl<'a> OUTSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Set"] + #[inline(always)] + pub fn outset(&self) -> OUTSET_R { + OUTSET_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Set"] + #[inline(always)] + pub fn outset(&mut self) -> OUTSET_W { + OUTSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/outtgl.rs b/pac/atsamda1e/src/port/group/outtgl.rs new file mode 100644 index 00000000000..437b7f6681d --- /dev/null +++ b/pac/atsamda1e/src/port/group/outtgl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTTGL` reader - Port Data Output Value Toggle"] +pub struct OUTTGL_R(crate::FieldReader); +impl OUTTGL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTTGL` writer - Port Data Output Value Toggle"] +pub struct OUTTGL_W<'a> { + w: &'a mut W, +} +impl<'a> OUTTGL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Toggle"] + #[inline(always)] + pub fn outtgl(&self) -> OUTTGL_R { + OUTTGL_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Toggle"] + #[inline(always)] + pub fn outtgl(&mut self) -> OUTTGL_W { + OUTTGL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/pincfg.rs b/pac/atsamda1e/src/port/group/pincfg.rs new file mode 100644 index 00000000000..215e64ba226 --- /dev/null +++ b/pac/atsamda1e/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Peripheral Multiplexer Enable"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Peripheral Multiplexer Enable"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/pmux.rs b/pac/atsamda1e/src/port/group/pmux.rs new file mode 100644 index 00000000000..98cf2bbec5b --- /dev/null +++ b/pac/atsamda1e/src/port/group/pmux.rs @@ -0,0 +1,395 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Peripheral Multiplexing Even\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PMUXE_A { + #[doc = "0: Peripheral function A selected"] + A = 0, + #[doc = "1: Peripheral function B selected"] + B = 1, + #[doc = "2: Peripheral function C selected"] + C = 2, + #[doc = "3: Peripheral function D selected"] + D = 3, + #[doc = "4: Peripheral function E selected"] + E = 4, + #[doc = "5: Peripheral function F selected"] + F = 5, + #[doc = "6: Peripheral function G selected"] + G = 6, + #[doc = "7: Peripheral function H selected"] + H = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PMUXE_A) -> Self { + variant as _ + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing Even"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PMUXE_A::A), + 1 => Some(PMUXE_A::B), + 2 => Some(PMUXE_A::C), + 3 => Some(PMUXE_A::D), + 4 => Some(PMUXE_A::E), + 5 => Some(PMUXE_A::F), + 6 => Some(PMUXE_A::G), + 7 => Some(PMUXE_A::H), + _ => None, + } + } + #[doc = "Checks if the value of the field is `A`"] + #[inline(always)] + pub fn is_a(&self) -> bool { + **self == PMUXE_A::A + } + #[doc = "Checks if the value of the field is `B`"] + #[inline(always)] + pub fn is_b(&self) -> bool { + **self == PMUXE_A::B + } + #[doc = "Checks if the value of the field is `C`"] + #[inline(always)] + pub fn is_c(&self) -> bool { + **self == PMUXE_A::C + } + #[doc = "Checks if the value of the field is `D`"] + #[inline(always)] + pub fn is_d(&self) -> bool { + **self == PMUXE_A::D + } + #[doc = "Checks if the value of the field is `E`"] + #[inline(always)] + pub fn is_e(&self) -> bool { + **self == PMUXE_A::E + } + #[doc = "Checks if the value of the field is `F`"] + #[inline(always)] + pub fn is_f(&self) -> bool { + **self == PMUXE_A::F + } + #[doc = "Checks if the value of the field is `G`"] + #[inline(always)] + pub fn is_g(&self) -> bool { + **self == PMUXE_A::G + } + #[doc = "Checks if the value of the field is `H`"] + #[inline(always)] + pub fn is_h(&self) -> bool { + **self == PMUXE_A::H + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing Even"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMUXE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral function A selected"] + #[inline(always)] + pub fn a(self) -> &'a mut W { + self.variant(PMUXE_A::A) + } + #[doc = "Peripheral function B selected"] + #[inline(always)] + pub fn b(self) -> &'a mut W { + self.variant(PMUXE_A::B) + } + #[doc = "Peripheral function C selected"] + #[inline(always)] + pub fn c(self) -> &'a mut W { + self.variant(PMUXE_A::C) + } + #[doc = "Peripheral function D selected"] + #[inline(always)] + pub fn d(self) -> &'a mut W { + self.variant(PMUXE_A::D) + } + #[doc = "Peripheral function E selected"] + #[inline(always)] + pub fn e(self) -> &'a mut W { + self.variant(PMUXE_A::E) + } + #[doc = "Peripheral function F selected"] + #[inline(always)] + pub fn f(self) -> &'a mut W { + self.variant(PMUXE_A::F) + } + #[doc = "Peripheral function G selected"] + #[inline(always)] + pub fn g(self) -> &'a mut W { + self.variant(PMUXE_A::G) + } + #[doc = "Peripheral function H selected"] + #[inline(always)] + pub fn h(self) -> &'a mut W { + self.variant(PMUXE_A::H) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Peripheral Multiplexing Odd\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PMUXO_A { + #[doc = "0: Peripheral function A selected"] + A = 0, + #[doc = "1: Peripheral function B selected"] + B = 1, + #[doc = "2: Peripheral function C selected"] + C = 2, + #[doc = "3: Peripheral function D selected"] + D = 3, + #[doc = "4: Peripheral function E selected"] + E = 4, + #[doc = "5: Peripheral function F selected"] + F = 5, + #[doc = "6: Peripheral function G selected"] + G = 6, + #[doc = "7: Peripheral function H selected"] + H = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PMUXO_A) -> Self { + variant as _ + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing Odd"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PMUXO_A::A), + 1 => Some(PMUXO_A::B), + 2 => Some(PMUXO_A::C), + 3 => Some(PMUXO_A::D), + 4 => Some(PMUXO_A::E), + 5 => Some(PMUXO_A::F), + 6 => Some(PMUXO_A::G), + 7 => Some(PMUXO_A::H), + _ => None, + } + } + #[doc = "Checks if the value of the field is `A`"] + #[inline(always)] + pub fn is_a(&self) -> bool { + **self == PMUXO_A::A + } + #[doc = "Checks if the value of the field is `B`"] + #[inline(always)] + pub fn is_b(&self) -> bool { + **self == PMUXO_A::B + } + #[doc = "Checks if the value of the field is `C`"] + #[inline(always)] + pub fn is_c(&self) -> bool { + **self == PMUXO_A::C + } + #[doc = "Checks if the value of the field is `D`"] + #[inline(always)] + pub fn is_d(&self) -> bool { + **self == PMUXO_A::D + } + #[doc = "Checks if the value of the field is `E`"] + #[inline(always)] + pub fn is_e(&self) -> bool { + **self == PMUXO_A::E + } + #[doc = "Checks if the value of the field is `F`"] + #[inline(always)] + pub fn is_f(&self) -> bool { + **self == PMUXO_A::F + } + #[doc = "Checks if the value of the field is `G`"] + #[inline(always)] + pub fn is_g(&self) -> bool { + **self == PMUXO_A::G + } + #[doc = "Checks if the value of the field is `H`"] + #[inline(always)] + pub fn is_h(&self) -> bool { + **self == PMUXO_A::H + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing Odd"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMUXO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral function A selected"] + #[inline(always)] + pub fn a(self) -> &'a mut W { + self.variant(PMUXO_A::A) + } + #[doc = "Peripheral function B selected"] + #[inline(always)] + pub fn b(self) -> &'a mut W { + self.variant(PMUXO_A::B) + } + #[doc = "Peripheral function C selected"] + #[inline(always)] + pub fn c(self) -> &'a mut W { + self.variant(PMUXO_A::C) + } + #[doc = "Peripheral function D selected"] + #[inline(always)] + pub fn d(self) -> &'a mut W { + self.variant(PMUXO_A::D) + } + #[doc = "Peripheral function E selected"] + #[inline(always)] + pub fn e(self) -> &'a mut W { + self.variant(PMUXO_A::E) + } + #[doc = "Peripheral function F selected"] + #[inline(always)] + pub fn f(self) -> &'a mut W { + self.variant(PMUXO_A::F) + } + #[doc = "Peripheral function G selected"] + #[inline(always)] + pub fn g(self) -> &'a mut W { + self.variant(PMUXO_A::G) + } + #[doc = "Peripheral function H selected"] + #[inline(always)] + pub fn h(self) -> &'a mut W { + self.variant(PMUXO_A::H) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing Even"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing Odd"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing Even"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing Odd"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/port/group/wrconfig.rs b/pac/atsamda1e/src/port/group/wrconfig.rs new file mode 100644 index 00000000000..67177b9fa53 --- /dev/null +++ b/pac/atsamda1e/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Peripheral Multiplexer Enable"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc.rs b/pac/atsamda1e/src/rtc.rs new file mode 100644 index 00000000000..47c627343b6 --- /dev/null +++ b/pac/atsamda1e/src/rtc.rs @@ -0,0 +1,123 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x1d], +} +impl RegisterBlock { + #[doc = "0x00..0x1d - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x1c - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x1c - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x18 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x14 - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x18 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x18 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x1c - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamda1e/src/rtc/mode0.rs b/pac/atsamda1e/src/rtc/mode0.rs new file mode 100644 index 00000000000..8dc0e3eea44 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0.rs @@ -0,0 +1,44 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE0 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamda1e/src/rtc/mode0/comp.rs b/pac/atsamda1e/src/rtc/mode0/comp.rs new file mode 100644 index 00000000000..a909d3cea2d --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/count.rs b/pac/atsamda1e/src/rtc/mode0/count.rs new file mode 100644 index 00000000000..cf880b5e77a --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/ctrl.rs b/pac/atsamda1e/src/rtc/mode0/ctrl.rs new file mode 100644 index 00000000000..e32ff1ab1dc --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/ctrl.rs @@ -0,0 +1,509 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/dbgctrl.rs b/pac/atsamda1e/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/evctrl.rs b/pac/atsamda1e/src/rtc/mode0/evctrl.rs new file mode 100644 index 00000000000..e06b491ad66 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/freqcorr.rs b/pac/atsamda1e/src/rtc/mode0/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/intenclr.rs b/pac/atsamda1e/src/rtc/mode0/intenclr.rs new file mode 100644 index 00000000000..3b44cce826b --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/intenset.rs b/pac/atsamda1e/src/rtc/mode0/intenset.rs new file mode 100644 index 00000000000..46c47783336 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/intflag.rs b/pac/atsamda1e/src/rtc/mode0/intflag.rs new file mode 100644 index 00000000000..991f5424f3f --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/readreq.rs b/pac/atsamda1e/src/rtc/mode0/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1e/src/rtc/mode0/status.rs b/pac/atsamda1e/src/rtc/mode0/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode0/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1.rs b/pac/atsamda1e/src/rtc/mode1.rs new file mode 100644 index 00000000000..4582204fc4a --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1.rs @@ -0,0 +1,48 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE1 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamda1e/src/rtc/mode1/comp.rs b/pac/atsamda1e/src/rtc/mode1/comp.rs new file mode 100644 index 00000000000..6935385840f --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/count.rs b/pac/atsamda1e/src/rtc/mode1/count.rs new file mode 100644 index 00000000000..2c41937b189 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/ctrl.rs b/pac/atsamda1e/src/rtc/mode1/ctrl.rs new file mode 100644 index 00000000000..6d513fa447d --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/ctrl.rs @@ -0,0 +1,462 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/dbgctrl.rs b/pac/atsamda1e/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/evctrl.rs b/pac/atsamda1e/src/rtc/mode1/evctrl.rs new file mode 100644 index 00000000000..28fad144acf --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/freqcorr.rs b/pac/atsamda1e/src/rtc/mode1/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/intenclr.rs b/pac/atsamda1e/src/rtc/mode1/intenclr.rs new file mode 100644 index 00000000000..69074385c72 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/intenset.rs b/pac/atsamda1e/src/rtc/mode1/intenset.rs new file mode 100644 index 00000000000..c3751bcd1c5 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/intflag.rs b/pac/atsamda1e/src/rtc/mode1/intflag.rs new file mode 100644 index 00000000000..f138167c02f --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/per.rs b/pac/atsamda1e/src/rtc/mode1/per.rs new file mode 100644 index 00000000000..c09b31fa30d --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/readreq.rs b/pac/atsamda1e/src/rtc/mode1/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1e/src/rtc/mode1/status.rs b/pac/atsamda1e/src/rtc/mode1/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode1/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2.rs b/pac/atsamda1e/src/rtc/mode2.rs new file mode 100644 index 00000000000..1d505a71021 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2.rs @@ -0,0 +1,48 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE2 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamda1e/src/rtc/mode2/alarm.rs b/pac/atsamda1e/src/rtc/mode2/alarm.rs new file mode 100644 index 00000000000..1242477ea69 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/clock.rs b/pac/atsamda1e/src/rtc/mode2/clock.rs new file mode 100644 index 00000000000..3f364ff8e57 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/ctrl.rs b/pac/atsamda1e/src/rtc/mode2/ctrl.rs new file mode 100644 index 00000000000..a66d90c2afa --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/ctrl.rs @@ -0,0 +1,556 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/dbgctrl.rs b/pac/atsamda1e/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/evctrl.rs b/pac/atsamda1e/src/rtc/mode2/evctrl.rs new file mode 100644 index 00000000000..1d66be29f63 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/freqcorr.rs b/pac/atsamda1e/src/rtc/mode2/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/intenclr.rs b/pac/atsamda1e/src/rtc/mode2/intenclr.rs new file mode 100644 index 00000000000..b7fc6efcaeb --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/intenset.rs b/pac/atsamda1e/src/rtc/mode2/intenset.rs new file mode 100644 index 00000000000..c21bec8514d --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/intflag.rs b/pac/atsamda1e/src/rtc/mode2/intflag.rs new file mode 100644 index 00000000000..651fb283181 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/mask.rs b/pac/atsamda1e/src/rtc/mode2/mask.rs new file mode 100644 index 00000000000..53e0bb491a6 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/readreq.rs b/pac/atsamda1e/src/rtc/mode2/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1e/src/rtc/mode2/status.rs b/pac/atsamda1e/src/rtc/mode2/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1e/src/rtc/mode2/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sbmatrix.rs b/pac/atsamda1e/src/sbmatrix.rs new file mode 100644 index 00000000000..460bbc3fab0 --- /dev/null +++ b/pac/atsamda1e/src/sbmatrix.rs @@ -0,0 +1,25 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x80], + #[doc = "0x80..0x100 - PRS\\[%s\\]"] + pub prs: [PRS; 16], + _reserved1: [u8; 0x10], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamda1e/src/sbmatrix/prs.rs b/pac/atsamda1e/src/sbmatrix/prs.rs new file mode 100644 index 00000000000..0313f3c4fc2 --- /dev/null +++ b/pac/atsamda1e/src/sbmatrix/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamda1e/src/sbmatrix/prs/pras.rs b/pac/atsamda1e/src/sbmatrix/prs/pras.rs new file mode 100644 index 00000000000..9c009454899 --- /dev/null +++ b/pac/atsamda1e/src/sbmatrix/prs/pras.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sbmatrix/prs/prbs.rs b/pac/atsamda1e/src/sbmatrix/prs/prbs.rs new file mode 100644 index 00000000000..b92922b5d85 --- /dev/null +++ b/pac/atsamda1e/src/sbmatrix/prs/prbs.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sbmatrix/sfr.rs b/pac/atsamda1e/src/sbmatrix/sfr.rs new file mode 100644 index 00000000000..0a7e024f73c --- /dev/null +++ b/pac/atsamda1e/src/sbmatrix/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0.rs b/pac/atsamda1e/src/sercom0.rs new file mode 100644 index 00000000000..41bcdc65741 --- /dev/null +++ b/pac/atsamda1e/src/sercom0.rs @@ -0,0 +1,325 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + _reserved_2_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved4: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + _reserved_2_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved4: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamda1e/src/sercom0/i2cm.rs b/pac/atsamda1e/src/sercom0/i2cm.rs new file mode 100644 index 00000000000..8aa217da8b1 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1e/src/sercom0/i2cm/addr.rs b/pac/atsamda1e/src/sercom0/i2cm/addr.rs new file mode 100644 index 00000000000..4efd19e824c --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/baud.rs b/pac/atsamda1e/src/sercom0/i2cm/baud.rs new file mode 100644 index 00000000000..7c98d3b5b0d --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/ctrla.rs b/pac/atsamda1e/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 00000000000..34fa668b796 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/ctrlb.rs b/pac/atsamda1e/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 00000000000..ce534463c0d --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/data.rs b/pac/atsamda1e/src/sercom0/i2cm/data.rs new file mode 100644 index 00000000000..cf204596d3a --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamda1e/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 00000000000..0fffdb4c6e3 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/intenclr.rs b/pac/atsamda1e/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 00000000000..17f067a5565 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/intenset.rs b/pac/atsamda1e/src/sercom0/i2cm/intenset.rs new file mode 100644 index 00000000000..a0cbf96b3aa --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/intflag.rs b/pac/atsamda1e/src/sercom0/i2cm/intflag.rs new file mode 100644 index 00000000000..0fb0d2b9060 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/status.rs b/pac/atsamda1e/src/sercom0/i2cm/status.rs new file mode 100644 index 00000000000..95af23673ec --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cm/syncbusy.rs b/pac/atsamda1e/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 00000000000..87dd418d1cd --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs.rs b/pac/atsamda1e/src/sercom0/i2cs.rs new file mode 100644 index 00000000000..baf9513c6cc --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamda1e/src/sercom0/i2cs/addr.rs b/pac/atsamda1e/src/sercom0/i2cs/addr.rs new file mode 100644 index 00000000000..c1b69ee2289 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/ctrla.rs b/pac/atsamda1e/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 00000000000..ec93812b004 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/ctrlb.rs b/pac/atsamda1e/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 00000000000..b20f48581ed --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/data.rs b/pac/atsamda1e/src/sercom0/i2cs/data.rs new file mode 100644 index 00000000000..d8bfe070431 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/intenclr.rs b/pac/atsamda1e/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 00000000000..49f5191c8d6 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/intenset.rs b/pac/atsamda1e/src/sercom0/i2cs/intenset.rs new file mode 100644 index 00000000000..97ea784d747 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/intflag.rs b/pac/atsamda1e/src/sercom0/i2cs/intflag.rs new file mode 100644 index 00000000000..2eee333e4e5 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/status.rs b/pac/atsamda1e/src/sercom0/i2cs/status.rs new file mode 100644 index 00000000000..b3f6d218fa6 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/i2cs/syncbusy.rs b/pac/atsamda1e/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 00000000000..38e2509d966 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim.rs b/pac/atsamda1e/src/sercom0/spim.rs new file mode 100644 index 00000000000..528e38e1b81 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1e/src/sercom0/spim/addr.rs b/pac/atsamda1e/src/sercom0/spim/addr.rs new file mode 100644 index 00000000000..7c25cd522ea --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/baud.rs b/pac/atsamda1e/src/sercom0/spim/baud.rs new file mode 100644 index 00000000000..6bec9ca7435 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/ctrla.rs b/pac/atsamda1e/src/sercom0/spim/ctrla.rs new file mode 100644 index 00000000000..44028f8cbdd --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/ctrlb.rs b/pac/atsamda1e/src/sercom0/spim/ctrlb.rs new file mode 100644 index 00000000000..3d94f824ce8 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/data.rs b/pac/atsamda1e/src/sercom0/spim/data.rs new file mode 100644 index 00000000000..dc9cd020d2a --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/dbgctrl.rs b/pac/atsamda1e/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 00000000000..d9aa7495940 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/intenclr.rs b/pac/atsamda1e/src/sercom0/spim/intenclr.rs new file mode 100644 index 00000000000..ccab3de4348 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/intenset.rs b/pac/atsamda1e/src/sercom0/spim/intenset.rs new file mode 100644 index 00000000000..d9779cf897c --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/intflag.rs b/pac/atsamda1e/src/sercom0/spim/intflag.rs new file mode 100644 index 00000000000..e9bc10c271b --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/status.rs b/pac/atsamda1e/src/sercom0/spim/status.rs new file mode 100644 index 00000000000..9919460bf0e --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spim/syncbusy.rs b/pac/atsamda1e/src/sercom0/spim/syncbusy.rs new file mode 100644 index 00000000000..bee13adf708 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis.rs b/pac/atsamda1e/src/sercom0/spis.rs new file mode 100644 index 00000000000..eed10c90c46 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1e/src/sercom0/spis/addr.rs b/pac/atsamda1e/src/sercom0/spis/addr.rs new file mode 100644 index 00000000000..5fca0a698bf --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/baud.rs b/pac/atsamda1e/src/sercom0/spis/baud.rs new file mode 100644 index 00000000000..eeee4cf633e --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/ctrla.rs b/pac/atsamda1e/src/sercom0/spis/ctrla.rs new file mode 100644 index 00000000000..6151433a852 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/ctrlb.rs b/pac/atsamda1e/src/sercom0/spis/ctrlb.rs new file mode 100644 index 00000000000..ccb70582cf3 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/data.rs b/pac/atsamda1e/src/sercom0/spis/data.rs new file mode 100644 index 00000000000..4edf8089b29 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/dbgctrl.rs b/pac/atsamda1e/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 00000000000..ec36bbd2605 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/intenclr.rs b/pac/atsamda1e/src/sercom0/spis/intenclr.rs new file mode 100644 index 00000000000..e4c9ee0d506 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/intenset.rs b/pac/atsamda1e/src/sercom0/spis/intenset.rs new file mode 100644 index 00000000000..99582a624eb --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/intflag.rs b/pac/atsamda1e/src/sercom0/spis/intflag.rs new file mode 100644 index 00000000000..589e73c2329 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/status.rs b/pac/atsamda1e/src/sercom0/spis/status.rs new file mode 100644 index 00000000000..55c39c1a709 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/spis/syncbusy.rs b/pac/atsamda1e/src/sercom0/spis/syncbusy.rs new file mode 100644 index 00000000000..ac2f2e2c27e --- /dev/null +++ b/pac/atsamda1e/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext.rs b/pac/atsamda1e/src/sercom0/usart_ext.rs new file mode 100644 index 00000000000..09204a683ce --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1e/src/sercom0/usart_ext/baud.rs b/pac/atsamda1e/src/sercom0/usart_ext/baud.rs new file mode 100644 index 00000000000..9558a8e1a52 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamda1e/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 00000000000..d7cdd4570e2 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamda1e/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 00000000000..c1dc5080767 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamda1e/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 00000000000..8d4db16e024 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/ctrla.rs b/pac/atsamda1e/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 00000000000..bb4db0ad4db --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1256 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + PAD0 = 0, + #[doc = "1: PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + PAD1 = 1, + #[doc = "2: PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + PAD2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD1), + 2 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == TXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(TXPO_A::PAD1) + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Sample Adjustment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPA_A { + #[doc = "0: 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + ADJ0 = 0, + #[doc = "1: 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + ADJ1 = 1, + #[doc = "2: 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + ADJ2 = 2, + #[doc = "3: 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + ADJ3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPA_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SAMPA_A { + match self.bits { + 0 => SAMPA_A::ADJ0, + 1 => SAMPA_A::ADJ1, + 2 => SAMPA_A::ADJ2, + 3 => SAMPA_A::ADJ3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ADJ0`"] + #[inline(always)] + pub fn is_adj0(&self) -> bool { + **self == SAMPA_A::ADJ0 + } + #[doc = "Checks if the value of the field is `ADJ1`"] + #[inline(always)] + pub fn is_adj1(&self) -> bool { + **self == SAMPA_A::ADJ1 + } + #[doc = "Checks if the value of the field is `ADJ2`"] + #[inline(always)] + pub fn is_adj2(&self) -> bool { + **self == SAMPA_A::ADJ2 + } + #[doc = "Checks if the value of the field is `ADJ3`"] + #[inline(always)] + pub fn is_adj3(&self) -> bool { + **self == SAMPA_A::ADJ3 + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPA_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + #[inline(always)] + pub fn adj0(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ0) + } + #[doc = "16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + #[inline(always)] + pub fn adj1(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ1) + } + #[doc = "16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + #[inline(always)] + pub fn adj2(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ2) + } + #[doc = "16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + #[inline(always)] + pub fn adj3(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamda1e/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 00000000000..b821c8eb783 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,614 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/data.rs b/pac/atsamda1e/src/sercom0/usart_ext/data.rs new file mode 100644 index 00000000000..a54152c9571 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamda1e/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 00000000000..6c844f3fe40 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/intenclr.rs b/pac/atsamda1e/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 00000000000..a815553ce66 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/intenset.rs b/pac/atsamda1e/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 00000000000..e800681cf42 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/intflag.rs b/pac/atsamda1e/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 00000000000..4b0be279a9a --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/rxpl.rs b/pac/atsamda1e/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 00000000000..174464dc16b --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/status.rs b/pac/atsamda1e/src/sercom0/usart_ext/status.rs new file mode 100644 index 00000000000..a0c50c1bc2c --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamda1e/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 00000000000..7c3b817bbb0 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int.rs b/pac/atsamda1e/src/sercom0/usart_int.rs new file mode 100644 index 00000000000..d19ecaceea5 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1e/src/sercom0/usart_int/baud.rs b/pac/atsamda1e/src/sercom0/usart_int/baud.rs new file mode 100644 index 00000000000..a82df20712b --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamda1e/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 00000000000..b9c7fa4c4b2 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamda1e/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 00000000000..0671db99cc9 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamda1e/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 00000000000..b49a7ef5b84 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/ctrla.rs b/pac/atsamda1e/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 00000000000..76aed2866aa --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1256 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + PAD0 = 0, + #[doc = "1: PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + PAD1 = 1, + #[doc = "2: PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + PAD2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD1), + 2 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == TXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(TXPO_A::PAD1) + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Sample Adjustment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPA_A { + #[doc = "0: 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + ADJ0 = 0, + #[doc = "1: 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + ADJ1 = 1, + #[doc = "2: 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + ADJ2 = 2, + #[doc = "3: 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + ADJ3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPA_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SAMPA_A { + match self.bits { + 0 => SAMPA_A::ADJ0, + 1 => SAMPA_A::ADJ1, + 2 => SAMPA_A::ADJ2, + 3 => SAMPA_A::ADJ3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ADJ0`"] + #[inline(always)] + pub fn is_adj0(&self) -> bool { + **self == SAMPA_A::ADJ0 + } + #[doc = "Checks if the value of the field is `ADJ1`"] + #[inline(always)] + pub fn is_adj1(&self) -> bool { + **self == SAMPA_A::ADJ1 + } + #[doc = "Checks if the value of the field is `ADJ2`"] + #[inline(always)] + pub fn is_adj2(&self) -> bool { + **self == SAMPA_A::ADJ2 + } + #[doc = "Checks if the value of the field is `ADJ3`"] + #[inline(always)] + pub fn is_adj3(&self) -> bool { + **self == SAMPA_A::ADJ3 + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPA_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + #[inline(always)] + pub fn adj0(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ0) + } + #[doc = "16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + #[inline(always)] + pub fn adj1(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ1) + } + #[doc = "16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + #[inline(always)] + pub fn adj2(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ2) + } + #[doc = "16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + #[inline(always)] + pub fn adj3(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/ctrlb.rs b/pac/atsamda1e/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 00000000000..5c6cc4e67ee --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,614 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/data.rs b/pac/atsamda1e/src/sercom0/usart_int/data.rs new file mode 100644 index 00000000000..19d74c337d4 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamda1e/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 00000000000..0ac5b9c7b90 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/intenclr.rs b/pac/atsamda1e/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 00000000000..5ad23ad1563 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/intenset.rs b/pac/atsamda1e/src/sercom0/usart_int/intenset.rs new file mode 100644 index 00000000000..457f440e13e --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/intflag.rs b/pac/atsamda1e/src/sercom0/usart_int/intflag.rs new file mode 100644 index 00000000000..a6a26321b8c --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/rxpl.rs b/pac/atsamda1e/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 00000000000..324cbac371c --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/status.rs b/pac/atsamda1e/src/sercom0/usart_int/status.rs new file mode 100644 index 00000000000..1a92018a359 --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sercom0/usart_int/syncbusy.rs b/pac/atsamda1e/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 00000000000..5dea9a5a7ba --- /dev/null +++ b/pac/atsamda1e/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sys_tick.rs b/pac/atsamda1e/src/sys_tick.rs new file mode 100644 index 00000000000..b0fe7a59e5e --- /dev/null +++ b/pac/atsamda1e/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamda1e/src/sys_tick/calib.rs b/pac/atsamda1e/src/sys_tick/calib.rs new file mode 100644 index 00000000000..df7fd80f773 --- /dev/null +++ b/pac/atsamda1e/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sys_tick/csr.rs b/pac/atsamda1e/src/sys_tick/csr.rs new file mode 100644 index 00000000000..872d637f5a8 --- /dev/null +++ b/pac/atsamda1e/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamda1e/src/sys_tick/cvr.rs b/pac/atsamda1e/src/sys_tick/cvr.rs new file mode 100644 index 00000000000..8a40b5f43b3 --- /dev/null +++ b/pac/atsamda1e/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sys_tick/rvr.rs b/pac/atsamda1e/src/sys_tick/rvr.rs new file mode 100644 index 00000000000..ac023ff75f3 --- /dev/null +++ b/pac/atsamda1e/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl.rs b/pac/atsamda1e/src/sysctrl.rs new file mode 100644 index 00000000000..91255f3491a --- /dev/null +++ b/pac/atsamda1e/src/sysctrl.rs @@ -0,0 +1,132 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub pclksr: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xosc: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + _reserved6: [u8; 0x02], + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x20 - 8MHz Internal Oscillator (OSC8M) Control"] + pub osc8m: crate::Reg, + #[doc = "0x24 - DFLL48M Control"] + pub dfllctrl: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x28 - DFLL48M Value"] + pub dfllval: crate::Reg, + #[doc = "0x2c - DFLL48M Multiplier"] + pub dfllmul: crate::Reg, + #[doc = "0x30 - DFLL48M Synchronization"] + pub dfllsync: crate::Reg, + _reserved13: [u8; 0x03], + #[doc = "0x34 - 3.3V Brown-Out Detector (BOD33) Control"] + pub bod33: crate::Reg, + _reserved14: [u8; 0x04], + #[doc = "0x3c - Voltage Regulator System (VREG) Control"] + pub vreg: crate::Reg, + _reserved15: [u8; 0x02], + #[doc = "0x40 - Voltage References System (VREF) Control"] + pub vref: crate::Reg, + #[doc = "0x44 - DPLL Control A"] + pub dpllctrla: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x48 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x4c - DPLL Control B"] + pub dpllctrlb: crate::Reg, + #[doc = "0x50 - DPLL Status"] + pub dpllstatus: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "PCLKSR register accessor: an alias for `Reg`"] +pub type PCLKSR = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod pclksr; +#[doc = "XOSC register accessor: an alias for `Reg`"] +pub type XOSC = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xosc; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; +#[doc = "OSC8M register accessor: an alias for `Reg`"] +pub type OSC8M = crate::Reg; +#[doc = "8MHz Internal Oscillator (OSC8M) Control"] +pub mod osc8m; +#[doc = "DFLLCTRL register accessor: an alias for `Reg`"] +pub type DFLLCTRL = crate::Reg; +#[doc = "DFLL48M Control"] +pub mod dfllctrl; +#[doc = "DFLLVAL register accessor: an alias for `Reg`"] +pub type DFLLVAL = crate::Reg; +#[doc = "DFLL48M Value"] +pub mod dfllval; +#[doc = "DFLLMUL register accessor: an alias for `Reg`"] +pub type DFLLMUL = crate::Reg; +#[doc = "DFLL48M Multiplier"] +pub mod dfllmul; +#[doc = "DFLLSYNC register accessor: an alias for `Reg`"] +pub type DFLLSYNC = crate::Reg; +#[doc = "DFLL48M Synchronization"] +pub mod dfllsync; +#[doc = "BOD33 register accessor: an alias for `Reg`"] +pub type BOD33 = crate::Reg; +#[doc = "3.3V Brown-Out Detector (BOD33) Control"] +pub mod bod33; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "Voltage Regulator System (VREG) Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "Voltage References System (VREF) Control"] +pub mod vref; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control A"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "DPLL Control B"] +pub mod dpllctrlb; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; diff --git a/pac/atsamda1e/src/sysctrl/bod33.rs b/pac/atsamda1e/src/sysctrl/bod33.rs new file mode 100644 index 00000000000..f4678865a1f --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/bod33.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BOD33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOD33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "BOD33 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BOD33 generates a reset"] + RESET = 1, + #[doc = "2: The BOD33 generates an interrupt"] + INTERRUPT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - BOD33 Action"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INTERRUPT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INTERRUPT`"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + **self == ACTION_A::INTERRUPT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - BOD33 Action"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BOD33 generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BOD33 generates an interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut W { + self.variant(ACTION_A::INTERRUPT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MODE` reader - Operation Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operation Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CEN` reader - Clock Enable"] +pub struct CEN_R(crate::FieldReader); +impl CEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CEN` writer - Clock Enable"] +pub struct CEN_W<'a> { + w: &'a mut W, +} +impl<'a> CEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1K = 9, + #[doc = "10: Divide clock by 2048"] + DIV2K = 10, + #[doc = "11: Divide clock by 4096"] + DIV4K = 11, + #[doc = "12: Divide clock by 8192"] + DIV8K = 12, + #[doc = "13: Divide clock by 16384"] + DIV16K = 13, + #[doc = "14: Divide clock by 32768"] + DIV32K = 14, + #[doc = "15: Divide clock by 65536"] + DIV64K = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1K, + 10 => PSEL_A::DIV2K, + 11 => PSEL_A::DIV4K, + 12 => PSEL_A::DIV8K, + 13 => PSEL_A::DIV16K, + 14 => PSEL_A::DIV32K, + 15 => PSEL_A::DIV64K, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1K`"] + #[inline(always)] + pub fn is_div1k(&self) -> bool { + **self == PSEL_A::DIV1K + } + #[doc = "Checks if the value of the field is `DIV2K`"] + #[inline(always)] + pub fn is_div2k(&self) -> bool { + **self == PSEL_A::DIV2K + } + #[doc = "Checks if the value of the field is `DIV4K`"] + #[inline(always)] + pub fn is_div4k(&self) -> bool { + **self == PSEL_A::DIV4K + } + #[doc = "Checks if the value of the field is `DIV8K`"] + #[inline(always)] + pub fn is_div8k(&self) -> bool { + **self == PSEL_A::DIV8K + } + #[doc = "Checks if the value of the field is `DIV16K`"] + #[inline(always)] + pub fn is_div16k(&self) -> bool { + **self == PSEL_A::DIV16K + } + #[doc = "Checks if the value of the field is `DIV32K`"] + #[inline(always)] + pub fn is_div32k(&self) -> bool { + **self == PSEL_A::DIV32K + } + #[doc = "Checks if the value of the field is `DIV64K`"] + #[inline(always)] + pub fn is_div64k(&self) -> bool { + **self == PSEL_A::DIV64K + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1k(self) -> &'a mut W { + self.variant(PSEL_A::DIV1K) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2k(self) -> &'a mut W { + self.variant(PSEL_A::DIV2K) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4k(self) -> &'a mut W { + self.variant(PSEL_A::DIV4K) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8k(self) -> &'a mut W { + self.variant(PSEL_A::DIV8K) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16k(self) -> &'a mut W { + self.variant(PSEL_A::DIV16K) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32k(self) -> &'a mut W { + self.variant(PSEL_A::DIV32K) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div64k(self) -> &'a mut W { + self.variant(PSEL_A::DIV64K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - BOD33 Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - BOD33 Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - BOD33 Action"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Operation Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Clock Enable"] + #[inline(always)] + pub fn cen(&self) -> CEN_R { + CEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - BOD33 Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - BOD33 Action"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Operation Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 9 - Clock Enable"] + #[inline(always)] + pub fn cen(&mut self) -> CEN_W { + CEN_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - BOD33 Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "3.3V Brown-Out Detector (BOD33) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bod33](index.html) module"] +pub struct BOD33_SPEC; +impl crate::RegisterSpec for BOD33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bod33::R](R) reader structure"] +impl crate::Readable for BOD33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bod33::W](W) writer structure"] +impl crate::Writable for BOD33_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BOD33 to value 0"] +impl crate::Resettable for BOD33_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dfllctrl.rs b/pac/atsamda1e/src/sysctrl/dfllctrl.rs new file mode 100644 index 00000000000..0e0c6d5be2b --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dfllctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `DFLLCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - DFLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - DFLL Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MODE` reader - Operating Mode Selection"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode Selection"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STABLE` reader - Stable DFLL Frequency"] +pub struct STABLE_R(crate::FieldReader); +impl STABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STABLE` writer - Stable DFLL Frequency"] +pub struct STABLE_W<'a> { + w: &'a mut W, +} +impl<'a> STABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `LLAW` reader - Lose Lock After Wake"] +pub struct LLAW_R(crate::FieldReader); +impl LLAW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LLAW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LLAW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LLAW` writer - Lose Lock After Wake"] +pub struct LLAW_W<'a> { + w: &'a mut W, +} +impl<'a> LLAW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `USBCRM` reader - USB Clock Recovery Mode"] +pub struct USBCRM_R(crate::FieldReader); +impl USBCRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USBCRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USBCRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USBCRM` writer - USB Clock Recovery Mode"] +pub struct USBCRM_W<'a> { + w: &'a mut W, +} +impl<'a> USBCRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CCDIS` reader - Chill Cycle Disable"] +pub struct CCDIS_R(crate::FieldReader); +impl CCDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCDIS` writer - Chill Cycle Disable"] +pub struct CCDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CCDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QLDIS` reader - Quick Lock Disable"] +pub struct QLDIS_R(crate::FieldReader); +impl QLDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QLDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QLDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QLDIS` writer - Quick Lock Disable"] +pub struct QLDIS_W<'a> { + w: &'a mut W, +} +impl<'a> QLDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BPLCKC` reader - Bypass Coarse Lock"] +pub struct BPLCKC_R(crate::FieldReader); +impl BPLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BPLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BPLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BPLCKC` writer - Bypass Coarse Lock"] +pub struct BPLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> BPLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `WAITLOCK` reader - Wait Lock"] +pub struct WAITLOCK_R(crate::FieldReader); +impl WAITLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITLOCK` writer - Wait Lock"] +pub struct WAITLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WAITLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + pub fn stable(&self) -> STABLE_R { + STABLE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + pub fn llaw(&self) -> LLAW_R { + LLAW_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + pub fn usbcrm(&self) -> USBCRM_R { + USBCRM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + pub fn ccdis(&self) -> CCDIS_R { + CCDIS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + pub fn qldis(&self) -> QLDIS_R { + QLDIS_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + pub fn bplckc(&self) -> BPLCKC_R { + BPLCKC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + pub fn waitlock(&self) -> WAITLOCK_R { + WAITLOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + pub fn stable(&mut self) -> STABLE_W { + STABLE_W { w: self } + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + pub fn llaw(&mut self) -> LLAW_W { + LLAW_W { w: self } + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + pub fn usbcrm(&mut self) -> USBCRM_W { + USBCRM_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + pub fn ccdis(&mut self) -> CCDIS_W { + CCDIS_W { w: self } + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + pub fn qldis(&mut self) -> QLDIS_W { + QLDIS_W { w: self } + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + pub fn bplckc(&mut self) -> BPLCKC_W { + BPLCKC_W { w: self } + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + pub fn waitlock(&mut self) -> WAITLOCK_W { + WAITLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllctrl](index.html) module"] +pub struct DFLLCTRL_SPEC; +impl crate::RegisterSpec for DFLLCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [dfllctrl::R](R) reader structure"] +impl crate::Readable for DFLLCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllctrl::W](W) writer structure"] +impl crate::Writable for DFLLCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLCTRL to value 0x80"] +impl crate::Resettable for DFLLCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dfllmul.rs b/pac/atsamda1e/src/sysctrl/dfllmul.rs new file mode 100644 index 00000000000..a7f8b3e47ed --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dfllmul.rs @@ -0,0 +1,177 @@ +#[doc = "Register `DFLLMUL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLMUL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MUL` reader - DFLL Multiply Factor"] +pub struct MUL_R(crate::FieldReader); +impl MUL_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MUL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MUL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUL` writer - DFLL Multiply Factor"] +pub struct MUL_W<'a> { + w: &'a mut W, +} +impl<'a> MUL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `FSTEP` reader - Fine Maximum Step"] +pub struct FSTEP_R(crate::FieldReader); +impl FSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSTEP` writer - Fine Maximum Step"] +pub struct FSTEP_W<'a> { + w: &'a mut W, +} +impl<'a> FSTEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 16)) | ((value as u32 & 0x03ff) << 16); + self.w + } +} +#[doc = "Field `CSTEP` reader - Coarse Maximum Step"] +pub struct CSTEP_R(crate::FieldReader); +impl CSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSTEP` writer - Coarse Maximum Step"] +pub struct CSTEP_W<'a> { + w: &'a mut W, +} +impl<'a> CSTEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + pub fn mul(&self) -> MUL_R { + MUL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + pub fn fstep(&self) -> FSTEP_R { + FSTEP_R::new(((self.bits >> 16) & 0x03ff) as u16) + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + pub fn cstep(&self) -> CSTEP_R { + CSTEP_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + pub fn mul(&mut self) -> MUL_W { + MUL_W { w: self } + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + pub fn fstep(&mut self) -> FSTEP_W { + FSTEP_W { w: self } + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + pub fn cstep(&mut self) -> CSTEP_W { + CSTEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Multiplier\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllmul](index.html) module"] +pub struct DFLLMUL_SPEC; +impl crate::RegisterSpec for DFLLMUL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllmul::R](R) reader structure"] +impl crate::Readable for DFLLMUL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllmul::W](W) writer structure"] +impl crate::Writable for DFLLMUL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLMUL to value 0"] +impl crate::Resettable for DFLLMUL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dfllsync.rs b/pac/atsamda1e/src/sysctrl/dfllsync.rs new file mode 100644 index 00000000000..ab2d44b3a57 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dfllsync.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DFLLSYNC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLSYNC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READREQ` reader - Read Request"] +pub struct READREQ_R(crate::FieldReader); +impl READREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READREQ` writer - Read Request"] +pub struct READREQ_W<'a> { + w: &'a mut W, +} +impl<'a> READREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Read Request"] + #[inline(always)] + pub fn readreq(&self) -> READREQ_R { + READREQ_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Read Request"] + #[inline(always)] + pub fn readreq(&mut self) -> READREQ_W { + READREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Synchronization\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllsync](index.html) module"] +pub struct DFLLSYNC_SPEC; +impl crate::RegisterSpec for DFLLSYNC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dfllsync::R](R) reader structure"] +impl crate::Readable for DFLLSYNC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllsync::W](W) writer structure"] +impl crate::Writable for DFLLSYNC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLSYNC to value 0"] +impl crate::Resettable for DFLLSYNC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dfllval.rs b/pac/atsamda1e/src/sysctrl/dfllval.rs new file mode 100644 index 00000000000..9098c660072 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dfllval.rs @@ -0,0 +1,177 @@ +#[doc = "Register `DFLLVAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLVAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FINE` reader - Fine Value"] +pub struct FINE_R(crate::FieldReader); +impl FINE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FINE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FINE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FINE` writer - Fine Value"] +pub struct FINE_W<'a> { + w: &'a mut W, +} +impl<'a> FINE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03ff) | (value as u32 & 0x03ff); + self.w + } +} +#[doc = "Field `COARSE` reader - Coarse Value"] +pub struct COARSE_R(crate::FieldReader); +impl COARSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COARSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COARSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COARSE` writer - Coarse Value"] +pub struct COARSE_W<'a> { + w: &'a mut W, +} +impl<'a> COARSE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 10)) | ((value as u32 & 0x3f) << 10); + self.w + } +} +#[doc = "Field `DIFF` reader - Multiplication Ratio Difference"] +pub struct DIFF_R(crate::FieldReader); +impl DIFF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFF` writer - Multiplication Ratio Difference"] +pub struct DIFF_W<'a> { + w: &'a mut W, +} +impl<'a> DIFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + pub fn fine(&self) -> FINE_R { + FINE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + pub fn coarse(&self) -> COARSE_R { + COARSE_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:31 - Multiplication Ratio Difference"] + #[inline(always)] + pub fn diff(&self) -> DIFF_R { + DIFF_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + pub fn fine(&mut self) -> FINE_W { + FINE_W { w: self } + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + pub fn coarse(&mut self) -> COARSE_W { + COARSE_W { w: self } + } + #[doc = "Bits 16:31 - Multiplication Ratio Difference"] + #[inline(always)] + pub fn diff(&mut self) -> DIFF_W { + DIFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllval](index.html) module"] +pub struct DFLLVAL_SPEC; +impl crate::RegisterSpec for DFLLVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllval::R](R) reader structure"] +impl crate::Readable for DFLLVAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllval::W](W) writer structure"] +impl crate::Writable for DFLLVAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLVAL to value 0"] +impl crate::Resettable for DFLLVAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dpllctrla.rs b/pac/atsamda1e/src/sysctrl/dpllctrla.rs new file mode 100644 index 00000000000..c0600c21f16 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - DPLL Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Clock Activation"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Clock Activation"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Clock Activation"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - DPLL Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Clock Activation"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dpllctrlb.rs b/pac/atsamda1e/src/sysctrl/dpllctrlb.rs new file mode 100644 index 00000000000..968579fc693 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: CLK_DPLL_REF0 clock reference"] + REF0 = 0, + #[doc = "1: CLK_DPLL_REF1 clock reference"] + REF1 = 1, + #[doc = "2: GCLK_DPLL clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::REF0), + 1 => Some(REFCLK_A::REF1), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `REF0`"] + #[inline(always)] + pub fn is_ref0(&self) -> bool { + **self == REFCLK_A::REF0 + } + #[doc = "Checks if the value of the field is `REF1`"] + #[inline(always)] + pub fn is_ref1(&self) -> bool { + **self == REFCLK_A::REF1 + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_DPLL_REF0 clock reference"] + #[inline(always)] + pub fn ref0(self) -> &'a mut W { + self.variant(REFCLK_A::REF0) + } + #[doc = "CLK_DPLL_REF1 clock reference"] + #[inline(always)] + pub fn ref1(self) -> &'a mut W { + self.variant(REFCLK_A::REF1) + } + #[doc = "GCLK_DPLL clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out"] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8 ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9 ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10 ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11 ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8 ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9 ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10 ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11 ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dpllratio.rs b/pac/atsamda1e/src/sysctrl/dpllratio.rs new file mode 100644 index 00000000000..93b39e30f1a --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/dpllstatus.rs b/pac/atsamda1e/src/sysctrl/dpllstatus.rs new file mode 100644 index 00000000000..70499131cff --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/dpllstatus.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - Output Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` reader - Divider Enable"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Divider Enable"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/intenclr.rs b/pac/atsamda1e/src/sysctrl/intenclr.rs new file mode 100644 index 00000000000..bf0a746e23a --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/intenclr.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/intenset.rs b/pac/atsamda1e/src/sysctrl/intenset.rs new file mode 100644 index 00000000000..39276ad4015 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/intenset.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/intflag.rs b/pac/atsamda1e/src/sysctrl/intflag.rs new file mode 100644 index 00000000000..0902e3120a1 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/intflag.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/osc32k.rs b/pac/atsamda1e/src/sysctrl/osc32k.rs new file mode 100644 index 00000000000..aa32cb287aa --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamda1e/src/sysctrl/osc8m.rs b/pac/atsamda1e/src/sysctrl/osc8m.rs new file mode 100644 index 00000000000..24f058d3ed1 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/osc8m.rs @@ -0,0 +1,468 @@ +#[doc = "Register `OSC8M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC8M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Prescaler\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: `0`"] + _0 = 0, + #[doc = "1: `1`"] + _1 = 1, + #[doc = "2: `10`"] + _2 = 2, + #[doc = "3: `11`"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Oscillator Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESC_A { + match self.bits { + 0 => PRESC_A::_0, + 1 => PRESC_A::_1, + 2 => PRESC_A::_2, + 3 => PRESC_A::_3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PRESC_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PRESC_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PRESC_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PRESC_A::_3 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Oscillator Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(PRESC_A::_0) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(PRESC_A::_1) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(PRESC_A::_2) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(PRESC_A::_3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 16)) | ((value as u32 & 0x0fff) << 16); + self.w + } +} +#[doc = "Oscillator Frequency Range\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FRANGE_A { + #[doc = "0: 4 to 6MHz"] + _0 = 0, + #[doc = "1: 6 to 8MHz"] + _1 = 1, + #[doc = "2: 8 to 11MHz"] + _2 = 2, + #[doc = "3: 11 to 15MHz"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FRANGE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FRANGE` reader - Oscillator Frequency Range"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRANGE_A { + match self.bits { + 0 => FRANGE_A::_0, + 1 => FRANGE_A::_1, + 2 => FRANGE_A::_2, + 3 => FRANGE_A::_3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FRANGE_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FRANGE_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FRANGE_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == FRANGE_A::_3 + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Oscillator Frequency Range"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FRANGE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "4 to 6MHz"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(FRANGE_A::_0) + } + #[doc = "6 to 8MHz"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(FRANGE_A::_1) + } + #[doc = "8 to 11MHz"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(FRANGE_A::_2) + } + #[doc = "11 to 15MHz"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(FRANGE_A::_3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Oscillator Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:27 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x0fff) as u16) + } + #[doc = "Bits 30:31 - Oscillator Frequency Range"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:9 - Oscillator Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Bits 16:27 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bits 30:31 - Oscillator Frequency Range"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "8MHz Internal Oscillator (OSC8M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc8m](index.html) module"] +pub struct OSC8M_SPEC; +impl crate::RegisterSpec for OSC8M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc8m::R](R) reader structure"] +impl crate::Readable for OSC8M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc8m::W](W) writer structure"] +impl crate::Writable for OSC8M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC8M to value 0x8707_0382"] +impl crate::Resettable for OSC8M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8707_0382 + } +} diff --git a/pac/atsamda1e/src/sysctrl/osculp32k.rs b/pac/atsamda1e/src/sysctrl/osculp32k.rs new file mode 100644 index 00000000000..b7baa4236c5 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u8 & 0x1f); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0x1f"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1f + } +} diff --git a/pac/atsamda1e/src/sysctrl/pclksr.rs b/pac/atsamda1e/src/sysctrl/pclksr.rs new file mode 100644 index 00000000000..0298891e5f6 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/pclksr.rs @@ -0,0 +1,333 @@ +#[doc = "Register `PCLKSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pclksr](index.html) module"] +pub struct PCLKSR_SPEC; +impl crate::RegisterSpec for PCLKSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pclksr::R](R) reader structure"] +impl crate::Readable for PCLKSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PCLKSR to value 0"] +impl crate::Resettable for PCLKSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/vref.rs b/pac/atsamda1e/src/sysctrl/vref.rs new file mode 100644 index 00000000000..ecdfa1cc05a --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/vref.rs @@ -0,0 +1,197 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BGOUTEN` reader - Bandgap Output Enable"] +pub struct BGOUTEN_R(crate::FieldReader); +impl BGOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BGOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BGOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BGOUTEN` writer - Bandgap Output Enable"] +pub struct BGOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> BGOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CALIB` reader - Bandgap Voltage Generator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Bandgap Voltage Generator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bandgap Output Enable"] + #[inline(always)] + pub fn bgouten(&self) -> BGOUTEN_R { + BGOUTEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Bandgap Voltage Generator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Bandgap Output Enable"] + #[inline(always)] + pub fn bgouten(&mut self) -> BGOUTEN_W { + BGOUTEN_W { w: self } + } + #[doc = "Bits 16:26 - Bandgap Voltage Generator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Voltage References System (VREF) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/vreg.rs b/pac/atsamda1e/src/sysctrl/vreg.rs new file mode 100644 index 00000000000..42de242a11c --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `FORCELDO` reader - Force LDO Voltage Regulator"] +pub struct FORCELDO_R(crate::FieldReader); +impl FORCELDO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FORCELDO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FORCELDO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORCELDO` writer - Force LDO Voltage Regulator"] +pub struct FORCELDO_W<'a> { + w: &'a mut W, +} +impl<'a> FORCELDO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 13 - Force LDO Voltage Regulator"] + #[inline(always)] + pub fn forceldo(&self) -> FORCELDO_R { + FORCELDO_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 13 - Force LDO Voltage Regulator"] + #[inline(always)] + pub fn forceldo(&mut self) -> FORCELDO_W { + FORCELDO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Voltage Regulator System (VREG) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/sysctrl/xosc.rs b/pac/atsamda1e/src/sysctrl/xosc.rs new file mode 100644 index 00000000000..d1237a54e28 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/xosc.rs @@ -0,0 +1,694 @@ +#[doc = "Register `XOSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2MHz"] + _0 = 0, + #[doc = "1: 4MHz"] + _1 = 1, + #[doc = "2: 8MHz"] + _2 = 2, + #[doc = "3: 16MHz"] + _3 = 3, + #[doc = "4: 30MHz"] + _4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::_0), + 1 => Some(GAIN_A::_1), + 2 => Some(GAIN_A::_2), + 3 => Some(GAIN_A::_3), + 4 => Some(GAIN_A::_4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == GAIN_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == GAIN_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == GAIN_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == GAIN_A::_3 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == GAIN_A::_4 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2MHz"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(GAIN_A::_0) + } + #[doc = "4MHz"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(GAIN_A::_1) + } + #[doc = "8MHz"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(GAIN_A::_2) + } + #[doc = "16MHz"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(GAIN_A::_3) + } + #[doc = "30MHz"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(GAIN_A::_4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc](index.html) module"] +pub struct XOSC_SPEC; +impl crate::RegisterSpec for XOSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc::R](R) reader structure"] +impl crate::Readable for XOSC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc::W](W) writer structure"] +impl crate::Writable for XOSC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC to value 0x80"] +impl crate::Resettable for XOSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1e/src/sysctrl/xosc32k.rs b/pac/atsamda1e/src/sysctrl/xosc32k.rs new file mode 100644 index 00000000000..6a13602dfc9 --- /dev/null +++ b/pac/atsamda1e/src/sysctrl/xosc32k.rs @@ -0,0 +1,606 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `AAMPEN` reader - Automatic Amplitude Control Enable"] +pub struct AAMPEN_R(crate::FieldReader); +impl AAMPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AAMPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AAMPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AAMPEN` writer - Automatic Amplitude Control Enable"] +pub struct AAMPEN_W<'a> { + w: &'a mut W, +} +impl<'a> AAMPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.592 ms"] + CYCLE2048 = 2, + #[doc = "3: 125.092 ms"] + CYCLE4096 = 3, + #[doc = "4: 500.092 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000.092 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000.092 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000.092 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.592 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125.092 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500.092 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000.092 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000.092 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000.092 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Automatic Amplitude Control Enable"] + #[inline(always)] + pub fn aampen(&self) -> AAMPEN_R { + AAMPEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 5 - Automatic Amplitude Control Enable"] + #[inline(always)] + pub fn aampen(&mut self) -> AAMPEN_W { + AAMPEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1e/src/system_control.rs b/pac/atsamda1e/src/system_control.rs new file mode 100644 index 00000000000..4894b22b258 --- /dev/null +++ b/pac/atsamda1e/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamda1e/src/system_control/aircr.rs b/pac/atsamda1e/src/system_control/aircr.rs new file mode 100644 index 00000000000..9453cc6f30b --- /dev/null +++ b/pac/atsamda1e/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/system_control/ccr.rs b/pac/atsamda1e/src/system_control/ccr.rs new file mode 100644 index 00000000000..62516a7b60c --- /dev/null +++ b/pac/atsamda1e/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamda1e/src/system_control/cpuid.rs b/pac/atsamda1e/src/system_control/cpuid.rs new file mode 100644 index 00000000000..4157d7a94e9 --- /dev/null +++ b/pac/atsamda1e/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamda1e/src/system_control/dfsr.rs b/pac/atsamda1e/src/system_control/dfsr.rs new file mode 100644 index 00000000000..948899af090 --- /dev/null +++ b/pac/atsamda1e/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/system_control/icsr.rs b/pac/atsamda1e/src/system_control/icsr.rs new file mode 100644 index 00000000000..7fe5fd41211 --- /dev/null +++ b/pac/atsamda1e/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/system_control/scr.rs b/pac/atsamda1e/src/system_control/scr.rs new file mode 100644 index 00000000000..db9c54fe6f6 --- /dev/null +++ b/pac/atsamda1e/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/system_control/shcsr.rs b/pac/atsamda1e/src/system_control/shcsr.rs new file mode 100644 index 00000000000..bfba26ac06a --- /dev/null +++ b/pac/atsamda1e/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/system_control/shpr2.rs b/pac/atsamda1e/src/system_control/shpr2.rs new file mode 100644 index 00000000000..5665d6a5e8a --- /dev/null +++ b/pac/atsamda1e/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/system_control/shpr3.rs b/pac/atsamda1e/src/system_control/shpr3.rs new file mode 100644 index 00000000000..cb5a92c5350 --- /dev/null +++ b/pac/atsamda1e/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/system_control/vtor.rs b/pac/atsamda1e/src/system_control/vtor.rs new file mode 100644 index 00000000000..0ee4c781781 --- /dev/null +++ b/pac/atsamda1e/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3.rs b/pac/atsamda1e/src/tc3.rs new file mode 100644 index 00000000000..6465deb3413 --- /dev/null +++ b/pac/atsamda1e/src/tc3.rs @@ -0,0 +1,133 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x20], +} +impl RegisterBlock { + #[doc = "0x00..0x20 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x1c - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x1a - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT8 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x14 - COUNT8 Period Value"] + pub per: crate::Reg, + _reserved13: [u8; 0x03], + #[doc = "0x18 - COUNT8 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT16 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x06], + #[doc = "0x18 - COUNT16 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT32 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x04], + #[doc = "0x18..0x20 - COUNT32 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamda1e/src/tc3/count16.rs b/pac/atsamda1e/src/tc3/count16.rs new file mode 100644 index 00000000000..c184879d148 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16.rs @@ -0,0 +1,52 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Counter Value"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1e/src/tc3/count16/cc.rs b/pac/atsamda1e/src/tc3/count16/cc.rs new file mode 100644 index 00000000000..ca78398c970 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/count.rs b/pac/atsamda1e/src/tc3/count16/count.rs new file mode 100644 index 00000000000..421dff4311a --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Count Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Count Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Count Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Count Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/ctrla.rs b/pac/atsamda1e/src/tc3/count16/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/ctrlbclr.rs b/pac/atsamda1e/src/tc3/count16/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/ctrlbset.rs b/pac/atsamda1e/src/tc3/count16/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/ctrlc.rs b/pac/atsamda1e/src/tc3/count16/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/dbgctrl.rs b/pac/atsamda1e/src/tc3/count16/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/evctrl.rs b/pac/atsamda1e/src/tc3/count16/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/intenclr.rs b/pac/atsamda1e/src/tc3/count16/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/intenset.rs b/pac/atsamda1e/src/tc3/count16/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/intflag.rs b/pac/atsamda1e/src/tc3/count16/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/readreq.rs b/pac/atsamda1e/src/tc3/count16/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count16/status.rs b/pac/atsamda1e/src/tc3/count16/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count16/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1e/src/tc3/count32.rs b/pac/atsamda1e/src/tc3/count32.rs new file mode 100644 index 00000000000..aeb206f527b --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32.rs @@ -0,0 +1,52 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Counter Value"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1e/src/tc3/count32/cc.rs b/pac/atsamda1e/src/tc3/count32/cc.rs new file mode 100644 index 00000000000..d9cafa8cf2a --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/count.rs b/pac/atsamda1e/src/tc3/count32/count.rs new file mode 100644 index 00000000000..80e47741321 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Count Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Count Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Count Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Count Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/ctrla.rs b/pac/atsamda1e/src/tc3/count32/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/ctrlbclr.rs b/pac/atsamda1e/src/tc3/count32/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/ctrlbset.rs b/pac/atsamda1e/src/tc3/count32/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/ctrlc.rs b/pac/atsamda1e/src/tc3/count32/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/dbgctrl.rs b/pac/atsamda1e/src/tc3/count32/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/evctrl.rs b/pac/atsamda1e/src/tc3/count32/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/intenclr.rs b/pac/atsamda1e/src/tc3/count32/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/intenset.rs b/pac/atsamda1e/src/tc3/count32/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/intflag.rs b/pac/atsamda1e/src/tc3/count32/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/readreq.rs b/pac/atsamda1e/src/tc3/count32/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count32/status.rs b/pac/atsamda1e/src/tc3/count32/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count32/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1e/src/tc3/count8.rs b/pac/atsamda1e/src/tc3/count8.rs new file mode 100644 index 00000000000..c25911542ec --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period Value"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1e/src/tc3/count8/cc.rs b/pac/atsamda1e/src/tc3/count8/cc.rs new file mode 100644 index 00000000000..02ab7eb2bf7 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/count.rs b/pac/atsamda1e/src/tc3/count8/count.rs new file mode 100644 index 00000000000..203d066a2e2 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/ctrla.rs b/pac/atsamda1e/src/tc3/count8/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/ctrlbclr.rs b/pac/atsamda1e/src/tc3/count8/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/ctrlbset.rs b/pac/atsamda1e/src/tc3/count8/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/ctrlc.rs b/pac/atsamda1e/src/tc3/count8/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/dbgctrl.rs b/pac/atsamda1e/src/tc3/count8/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/evctrl.rs b/pac/atsamda1e/src/tc3/count8/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/intenclr.rs b/pac/atsamda1e/src/tc3/count8/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/intenset.rs b/pac/atsamda1e/src/tc3/count8/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/intflag.rs b/pac/atsamda1e/src/tc3/count8/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/per.rs b/pac/atsamda1e/src/tc3/count8/per.rs new file mode 100644 index 00000000000..27a157b4646 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamda1e/src/tc3/count8/readreq.rs b/pac/atsamda1e/src/tc3/count8/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tc3/count8/status.rs b/pac/atsamda1e/src/tc3/count8/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1e/src/tc3/count8/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1e/src/tcc0.rs b/pac/atsamda1e/src/tcc0.rs new file mode 100644 index 00000000000..32249343331 --- /dev/null +++ b/pac/atsamda1e/src/tcc0.rs @@ -0,0 +1,365 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattb: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x68 - Waveform Control Buffer"] + pub waveb: crate::Reg, + _reserved_21_perb: [u8; 0x04], + _reserved_22_ccb: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTB register accessor: an alias for `Reg`"] +pub type PATTB = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattb; +#[doc = "WAVEB register accessor: an alias for `Reg`"] +pub type WAVEB = crate::Reg; +#[doc = "Waveform Control Buffer"] +pub mod waveb; +#[doc = "PERB register accessor: an alias for `Reg`"] +pub type PERB = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb; +#[doc = "PERB_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith4_mode; +#[doc = "PERB_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith5_mode; +#[doc = "PERB_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith6_mode; +#[doc = "CCB register accessor: an alias for `Reg`"] +pub type CCB = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb; +#[doc = "CCB_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith4_mode; +#[doc = "CCB_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith5_mode; +#[doc = "CCB_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith6_mode; diff --git a/pac/atsamda1e/src/tcc0/cc.rs b/pac/atsamda1e/src/tcc0/cc.rs new file mode 100644 index 00000000000..c4d6df7a9a2 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/cc_dith4_mode.rs b/pac/atsamda1e/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 00000000000..f386ab1bdd8 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/cc_dith5_mode.rs b/pac/atsamda1e/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 00000000000..88749a75cb3 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/cc_dith6_mode.rs b/pac/atsamda1e/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 00000000000..a315f193152 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/ccb.rs b/pac/atsamda1e/src/tcc0/ccb.rs new file mode 100644 index 00000000000..3ccab84b34c --- /dev/null +++ b/pac/atsamda1e/src/tcc0/ccb.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCB[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb](index.html) module"] +pub struct CCB_SPEC; +impl crate::RegisterSpec for CCB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb::R](R) reader structure"] +impl crate::Readable for CCB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb::W](W) writer structure"] +impl crate::Writable for CCB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB[%s] +to value 0"] +impl crate::Resettable for CCB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/ccb_dith4_mode.rs b/pac/atsamda1e/src/tcc0/ccb_dith4_mode.rs new file mode 100644 index 00000000000..bece549a8d7 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/ccb_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith4_mode](index.html) module"] +pub struct CCB_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/ccb_dith5_mode.rs b/pac/atsamda1e/src/tcc0/ccb_dith5_mode.rs new file mode 100644 index 00000000000..71235fa105b --- /dev/null +++ b/pac/atsamda1e/src/tcc0/ccb_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith5_mode](index.html) module"] +pub struct CCB_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/ccb_dith6_mode.rs b/pac/atsamda1e/src/tcc0/ccb_dith6_mode.rs new file mode 100644 index 00000000000..f7aa63650de --- /dev/null +++ b/pac/atsamda1e/src/tcc0/ccb_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith6_mode](index.html) module"] +pub struct CCB_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/count.rs b/pac/atsamda1e/src/tcc0/count.rs new file mode 100644 index 00000000000..7628f2c0d5e --- /dev/null +++ b/pac/atsamda1e/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/count_dith4_mode.rs b/pac/atsamda1e/src/tcc0/count_dith4_mode.rs new file mode 100644 index 00000000000..fc058ae5efd --- /dev/null +++ b/pac/atsamda1e/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/count_dith5_mode.rs b/pac/atsamda1e/src/tcc0/count_dith5_mode.rs new file mode 100644 index 00000000000..e66e2031072 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/count_dith6_mode.rs b/pac/atsamda1e/src/tcc0/count_dith6_mode.rs new file mode 100644 index 00000000000..5410fc6c945 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/ctrla.rs b/pac/atsamda1e/src/tcc0/ctrla.rs new file mode 100644 index 00000000000..ce94f627db2 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/ctrla.rs @@ -0,0 +1,817 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/ctrlbclr.rs b/pac/atsamda1e/src/tcc0/ctrlbclr.rs new file mode 100644 index 00000000000..39a196da677 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/ctrlbclr.rs @@ -0,0 +1,444 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update of double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/ctrlbset.rs b/pac/atsamda1e/src/tcc0/ctrlbset.rs new file mode 100644 index 00000000000..a02c4d5e1ee --- /dev/null +++ b/pac/atsamda1e/src/tcc0/ctrlbset.rs @@ -0,0 +1,444 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update of double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/dbgctrl.rs b/pac/atsamda1e/src/tcc0/dbgctrl.rs new file mode 100644 index 00000000000..313ebe3f5c1 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/drvctrl.rs b/pac/atsamda1e/src/tcc0/drvctrl.rs new file mode 100644 index 00000000000..316041e1e3b --- /dev/null +++ b/pac/atsamda1e/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/evctrl.rs b/pac/atsamda1e/src/tcc0/evctrl.rs new file mode 100644 index 00000000000..5eaba702e34 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/evctrl.rs @@ -0,0 +1,1198 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT0_A::OFF), + 1 => Some(EVACT0_A::RETRIGGER), + 2 => Some(EVACT0_A::COUNTEV), + 3 => Some(EVACT0_A::START), + 4 => Some(EVACT0_A::INC), + 5 => Some(EVACT0_A::COUNT), + 7 => Some(EVACT0_A::FAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/fctrla.rs b/pac/atsamda1e/src/tcc0/fctrla.rs new file mode 100644 index 00000000000..e55d54575a4 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/fctrla.rs @@ -0,0 +1,880 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: No blanking applied"] + NONE = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::NONE, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == BLANK_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No blanking applied"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BLANK_A::NONE) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTURE_A::DISABLE), + 1 => Some(CAPTURE_A::CAPT), + 2 => Some(CAPTURE_A::CAPTMIN), + 3 => Some(CAPTURE_A::CAPTMAX), + 4 => Some(CAPTURE_A::LOCMIN), + 5 => Some(CAPTURE_A::LOCMAX), + 6 => Some(CAPTURE_A::DERIV0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/fctrlb.rs b/pac/atsamda1e/src/tcc0/fctrlb.rs new file mode 100644 index 00000000000..2dd88cc1904 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/fctrlb.rs @@ -0,0 +1,880 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: No blanking applied"] + NONE = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::NONE, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == BLANK_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No blanking applied"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BLANK_A::NONE) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTURE_A::DISABLE), + 1 => Some(CAPTURE_A::CAPT), + 2 => Some(CAPTURE_A::CAPTMIN), + 3 => Some(CAPTURE_A::CAPTMAX), + 4 => Some(CAPTURE_A::LOCMIN), + 5 => Some(CAPTURE_A::LOCMAX), + 6 => Some(CAPTURE_A::DERIV0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/intenclr.rs b/pac/atsamda1e/src/tcc0/intenclr.rs new file mode 100644 index 00000000000..bd054b6cbbd --- /dev/null +++ b/pac/atsamda1e/src/tcc0/intenclr.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/intenset.rs b/pac/atsamda1e/src/tcc0/intenset.rs new file mode 100644 index 00000000000..1be03869328 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/intenset.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/intflag.rs b/pac/atsamda1e/src/tcc0/intflag.rs new file mode 100644 index 00000000000..7106718fd29 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/intflag.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/patt.rs b/pac/atsamda1e/src/tcc0/patt.rs new file mode 100644 index 00000000000..ea458642b18 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/pattb.rs b/pac/atsamda1e/src/tcc0/pattb.rs new file mode 100644 index 00000000000..04190b1d35d --- /dev/null +++ b/pac/atsamda1e/src/tcc0/pattb.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattb](index.html) module"] +pub struct PATTB_SPEC; +impl crate::RegisterSpec for PATTB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattb::R](R) reader structure"] +impl crate::Readable for PATTB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattb::W](W) writer structure"] +impl crate::Writable for PATTB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTB to value 0"] +impl crate::Resettable for PATTB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/per.rs b/pac/atsamda1e/src/tcc0/per.rs new file mode 100644 index 00000000000..9d861863165 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/per_dith4_mode.rs b/pac/atsamda1e/src/tcc0/per_dith4_mode.rs new file mode 100644 index 00000000000..6e8d857e483 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/per_dith5_mode.rs b/pac/atsamda1e/src/tcc0/per_dith5_mode.rs new file mode 100644 index 00000000000..06337b7b91c --- /dev/null +++ b/pac/atsamda1e/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/per_dith6_mode.rs b/pac/atsamda1e/src/tcc0/per_dith6_mode.rs new file mode 100644 index 00000000000..fcbe0f6e31c --- /dev/null +++ b/pac/atsamda1e/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/perb.rs b/pac/atsamda1e/src/tcc0/perb.rs new file mode 100644 index 00000000000..6d3eb30c82d --- /dev/null +++ b/pac/atsamda1e/src/tcc0/perb.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb](index.html) module"] +pub struct PERB_SPEC; +impl crate::RegisterSpec for PERB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb::R](R) reader structure"] +impl crate::Readable for PERB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb::W](W) writer structure"] +impl crate::Writable for PERB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB to value 0xffff_ffff"] +impl crate::Resettable for PERB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/perb_dith4_mode.rs b/pac/atsamda1e/src/tcc0/perb_dith4_mode.rs new file mode 100644 index 00000000000..7781d12d911 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/perb_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith4_mode](index.html) module"] +pub struct PERB_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/perb_dith5_mode.rs b/pac/atsamda1e/src/tcc0/perb_dith5_mode.rs new file mode 100644 index 00000000000..e7364029ce2 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/perb_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith5_mode](index.html) module"] +pub struct PERB_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/perb_dith6_mode.rs b/pac/atsamda1e/src/tcc0/perb_dith6_mode.rs new file mode 100644 index 00000000000..0a780ae5f55 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/perb_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith6_mode](index.html) module"] +pub struct PERB_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1e/src/tcc0/status.rs b/pac/atsamda1e/src/tcc0/status.rs new file mode 100644 index 00000000000..15ea2088d08 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBV` reader - Pattern Buffer Valid"] +pub struct PATTBV_R(crate::FieldReader); +impl PATTBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBV` writer - Pattern Buffer Valid"] +pub struct PATTBV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `WAVEBV` reader - Wave Buffer Valid"] +pub struct WAVEBV_R(crate::FieldReader); +impl WAVEBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVEBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVEBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEBV` writer - Wave Buffer Valid"] +pub struct WAVEBV_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PERBV` reader - Period Buffer Valid"] +pub struct PERBV_R(crate::FieldReader); +impl PERBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBV` writer - Period Buffer Valid"] +pub struct PERBV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBV0_R(crate::FieldReader); +impl CCBV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBV1_R(crate::FieldReader); +impl CCBV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBV2_R(crate::FieldReader); +impl CCBV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBV3_R(crate::FieldReader); +impl CCBV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbv(&self) -> PATTBV_R { + PATTBV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Buffer Valid"] + #[inline(always)] + pub fn wavebv(&self) -> WAVEBV_R { + WAVEBV_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbv(&self) -> PERBV_R { + PERBV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbv0(&self) -> CCBV0_R { + CCBV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbv1(&self) -> CCBV1_R { + CCBV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbv2(&self) -> CCBV2_R { + CCBV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbv3(&self) -> CCBV3_R { + CCBV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbv(&mut self) -> PATTBV_W { + PATTBV_W { w: self } + } + #[doc = "Bit 6 - Wave Buffer Valid"] + #[inline(always)] + pub fn wavebv(&mut self) -> WAVEBV_W { + WAVEBV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbv(&mut self) -> PERBV_W { + PERBV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbv0(&mut self) -> CCBV0_W { + CCBV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbv1(&mut self) -> CCBV1_W { + CCBV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbv2(&mut self) -> CCBV2_W { + CCBV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbv3(&mut self) -> CCBV3_W { + CCBV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1e/src/tcc0/syncbusy.rs b/pac/atsamda1e/src/tcc0/syncbusy.rs new file mode 100644 index 00000000000..92f751789fd --- /dev/null +++ b/pac/atsamda1e/src/tcc0/syncbusy.rs @@ -0,0 +1,413 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTB` reader - Pattern Buffer Busy"] +pub struct PATTB_R(crate::FieldReader); +impl PATTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEB` reader - Wave Buffer Busy"] +pub struct WAVEB_R(crate::FieldReader); +impl WAVEB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVEB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVEB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` reader - Period Buffer Busy"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB0` reader - Compare Channel Buffer 0 Busy"] +pub struct CCB0_R(crate::FieldReader); +impl CCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB1` reader - Compare Channel Buffer 1 Busy"] +pub struct CCB1_R(crate::FieldReader); +impl CCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB2` reader - Compare Channel Buffer 2 Busy"] +pub struct CCB2_R(crate::FieldReader); +impl CCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB3` reader - Compare Channel Buffer 3 Busy"] +pub struct CCB3_R(crate::FieldReader); +impl CCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Pattern Buffer Busy"] + #[inline(always)] + pub fn pattb(&self) -> PATTB_R { + PATTB_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Wave Buffer Busy"] + #[inline(always)] + pub fn waveb(&self) -> WAVEB_R { + WAVEB_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Period Buffer Busy"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel Buffer 0 Busy"] + #[inline(always)] + pub fn ccb0(&self) -> CCB0_R { + CCB0_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Compare Channel Buffer 1 Busy"] + #[inline(always)] + pub fn ccb1(&self) -> CCB1_R { + CCB1_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Compare Channel Buffer 2 Busy"] + #[inline(always)] + pub fn ccb2(&self) -> CCB2_R { + CCB2_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Compare Channel Buffer 3 Busy"] + #[inline(always)] + pub fn ccb3(&self) -> CCB3_R { + CCB3_R::new(((self.bits >> 22) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/wave.rs b/pac/atsamda1e/src/tcc0/wave.rs new file mode 100644 index 00000000000..30602a3a4c6 --- /dev/null +++ b/pac/atsamda1e/src/tcc0/wave.rs @@ -0,0 +1,927 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RAMP_A::RAMP1), + 1 => Some(RAMP_A::RAMP2A), + 2 => Some(RAMP_A::RAMP2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/waveb.rs b/pac/atsamda1e/src/tcc0/waveb.rs new file mode 100644 index 00000000000..bfad858fc8f --- /dev/null +++ b/pac/atsamda1e/src/tcc0/waveb.rs @@ -0,0 +1,927 @@ +#[doc = "Register `WAVEB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVEB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGENB_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGENB_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGENB` reader - Waveform Generation Buffer"] +pub struct WAVEGENB_R(crate::FieldReader); +impl WAVEGENB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGENB_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGENB_A::NFRQ), + 1 => Some(WAVEGENB_A::MFRQ), + 2 => Some(WAVEGENB_A::NPWM), + 4 => Some(WAVEGENB_A::DSCRITICAL), + 5 => Some(WAVEGENB_A::DSBOTTOM), + 6 => Some(WAVEGENB_A::DSBOTH), + 7 => Some(WAVEGENB_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGENB_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGENB_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGENB_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGENB_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGENB_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGENB_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGENB_A::DSTOP + } +} +impl core::ops::Deref for WAVEGENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGENB` writer - Waveform Generation Buffer"] +pub struct WAVEGENB_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGENB_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGENB_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGENB_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGENB_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGENB_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode Buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMPB_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMPB_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMPB` reader - Ramp Mode Buffer"] +pub struct RAMPB_R(crate::FieldReader); +impl RAMPB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMPB_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RAMPB_A::RAMP1), + 1 => Some(RAMPB_A::RAMP2A), + 2 => Some(RAMPB_A::RAMP2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMPB_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMPB_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMPB_A::RAMP2 + } +} +impl core::ops::Deref for RAMPB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPB` writer - Ramp Mode Buffer"] +pub struct RAMPB_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPB_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMPB_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPERENB` reader - Circular Period Enable Buffer"] +pub struct CIPERENB_R(crate::FieldReader); +impl CIPERENB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPERENB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPERENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPERENB` writer - Circular Period Enable Buffer"] +pub struct CIPERENB_W<'a> { + w: &'a mut W, +} +impl<'a> CIPERENB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCENB0` reader - Circular Channel 0 Enable Buffer"] +pub struct CICCENB0_R(crate::FieldReader); +impl CICCENB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB0` writer - Circular Channel 0 Enable Buffer"] +pub struct CICCENB0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCENB1` reader - Circular Channel 1 Enable Buffer"] +pub struct CICCENB1_R(crate::FieldReader); +impl CICCENB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB1` writer - Circular Channel 1 Enable Buffer"] +pub struct CICCENB1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCENB2` reader - Circular Channel 2 Enable Buffer"] +pub struct CICCENB2_R(crate::FieldReader); +impl CICCENB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB2` writer - Circular Channel 2 Enable Buffer"] +pub struct CICCENB2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCENB3` reader - Circular Channel 3 Enable Buffer"] +pub struct CICCENB3_R(crate::FieldReader); +impl CICCENB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB3` writer - Circular Channel 3 Enable Buffer"] +pub struct CICCENB3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POLB0` reader - Channel 0 Polarity Buffer"] +pub struct POLB0_R(crate::FieldReader); +impl POLB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB0` writer - Channel 0 Polarity Buffer"] +pub struct POLB0_W<'a> { + w: &'a mut W, +} +impl<'a> POLB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POLB1` reader - Channel 1 Polarity Buffer"] +pub struct POLB1_R(crate::FieldReader); +impl POLB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB1` writer - Channel 1 Polarity Buffer"] +pub struct POLB1_W<'a> { + w: &'a mut W, +} +impl<'a> POLB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POLB2` reader - Channel 2 Polarity Buffer"] +pub struct POLB2_R(crate::FieldReader); +impl POLB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB2` writer - Channel 2 Polarity Buffer"] +pub struct POLB2_W<'a> { + w: &'a mut W, +} +impl<'a> POLB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POLB3` reader - Channel 3 Polarity Buffer"] +pub struct POLB3_R(crate::FieldReader); +impl POLB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB3` writer - Channel 3 Polarity Buffer"] +pub struct POLB3_W<'a> { + w: &'a mut W, +} +impl<'a> POLB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAPB0` reader - Swap DTI Output Pair 0 Buffer"] +pub struct SWAPB0_R(crate::FieldReader); +impl SWAPB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB0` writer - Swap DTI Output Pair 0 Buffer"] +pub struct SWAPB0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAPB1` reader - Swap DTI Output Pair 1 Buffer"] +pub struct SWAPB1_R(crate::FieldReader); +impl SWAPB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB1` writer - Swap DTI Output Pair 1 Buffer"] +pub struct SWAPB1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAPB2` reader - Swap DTI Output Pair 2 Buffer"] +pub struct SWAPB2_R(crate::FieldReader); +impl SWAPB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB2` writer - Swap DTI Output Pair 2 Buffer"] +pub struct SWAPB2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAPB3` reader - Swap DTI Output Pair 3 Buffer"] +pub struct SWAPB3_R(crate::FieldReader); +impl SWAPB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB3` writer - Swap DTI Output Pair 3 Buffer"] +pub struct SWAPB3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation Buffer"] + #[inline(always)] + pub fn wavegenb(&self) -> WAVEGENB_R { + WAVEGENB_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode Buffer"] + #[inline(always)] + pub fn rampb(&self) -> RAMPB_R { + RAMPB_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular Period Enable Buffer"] + #[inline(always)] + pub fn ciperenb(&self) -> CIPERENB_R { + CIPERENB_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable Buffer"] + #[inline(always)] + pub fn ciccenb0(&self) -> CICCENB0_R { + CICCENB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable Buffer"] + #[inline(always)] + pub fn ciccenb1(&self) -> CICCENB1_R { + CICCENB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable Buffer"] + #[inline(always)] + pub fn ciccenb2(&self) -> CICCENB2_R { + CICCENB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable Buffer"] + #[inline(always)] + pub fn ciccenb3(&self) -> CICCENB3_R { + CICCENB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity Buffer"] + #[inline(always)] + pub fn polb0(&self) -> POLB0_R { + POLB0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity Buffer"] + #[inline(always)] + pub fn polb1(&self) -> POLB1_R { + POLB1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity Buffer"] + #[inline(always)] + pub fn polb2(&self) -> POLB2_R { + POLB2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity Buffer"] + #[inline(always)] + pub fn polb3(&self) -> POLB3_R { + POLB3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0 Buffer"] + #[inline(always)] + pub fn swapb0(&self) -> SWAPB0_R { + SWAPB0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1 Buffer"] + #[inline(always)] + pub fn swapb1(&self) -> SWAPB1_R { + SWAPB1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2 Buffer"] + #[inline(always)] + pub fn swapb2(&self) -> SWAPB2_R { + SWAPB2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3 Buffer"] + #[inline(always)] + pub fn swapb3(&self) -> SWAPB3_R { + SWAPB3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation Buffer"] + #[inline(always)] + pub fn wavegenb(&mut self) -> WAVEGENB_W { + WAVEGENB_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode Buffer"] + #[inline(always)] + pub fn rampb(&mut self) -> RAMPB_W { + RAMPB_W { w: self } + } + #[doc = "Bit 7 - Circular Period Enable Buffer"] + #[inline(always)] + pub fn ciperenb(&mut self) -> CIPERENB_W { + CIPERENB_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable Buffer"] + #[inline(always)] + pub fn ciccenb0(&mut self) -> CICCENB0_W { + CICCENB0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable Buffer"] + #[inline(always)] + pub fn ciccenb1(&mut self) -> CICCENB1_W { + CICCENB1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable Buffer"] + #[inline(always)] + pub fn ciccenb2(&mut self) -> CICCENB2_W { + CICCENB2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable Buffer"] + #[inline(always)] + pub fn ciccenb3(&mut self) -> CICCENB3_W { + CICCENB3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity Buffer"] + #[inline(always)] + pub fn polb0(&mut self) -> POLB0_W { + POLB0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity Buffer"] + #[inline(always)] + pub fn polb1(&mut self) -> POLB1_W { + POLB1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity Buffer"] + #[inline(always)] + pub fn polb2(&mut self) -> POLB2_W { + POLB2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity Buffer"] + #[inline(always)] + pub fn polb3(&mut self) -> POLB3_W { + POLB3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0 Buffer"] + #[inline(always)] + pub fn swapb0(&mut self) -> SWAPB0_W { + SWAPB0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1 Buffer"] + #[inline(always)] + pub fn swapb1(&mut self) -> SWAPB1_W { + SWAPB1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2 Buffer"] + #[inline(always)] + pub fn swapb2(&mut self) -> SWAPB2_W { + SWAPB2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3 Buffer"] + #[inline(always)] + pub fn swapb3(&mut self) -> SWAPB3_W { + SWAPB3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [waveb](index.html) module"] +pub struct WAVEB_SPEC; +impl crate::RegisterSpec for WAVEB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [waveb::R](R) reader structure"] +impl crate::Readable for WAVEB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [waveb::W](W) writer structure"] +impl crate::Writable for WAVEB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVEB to value 0"] +impl crate::Resettable for WAVEB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/tcc0/wexctrl.rs b/pac/atsamda1e/src/tcc0/wexctrl.rs new file mode 100644 index 00000000000..8eb0d29cbee --- /dev/null +++ b/pac/atsamda1e/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb.rs b/pac/atsamda1e/src/usb.rs new file mode 100644 index 00000000000..22f33e47394 --- /dev/null +++ b/pac/atsamda1e/src/usb.rs @@ -0,0 +1,155 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_host: [u8; 0x01ea], +} +impl RegisterBlock { + #[doc = "0x00..0x1ea - USB is Host"] + #[inline(always)] + pub fn host(&self) -> &HOST { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const HOST) } + } + #[doc = "0x00..0x1ea - USB is Device"] + #[inline(always)] + pub fn device(&self) -> &DEVICE { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const DEVICE) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct DEVICE { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x03 - USB Quality Of Service"] + pub qosctrl: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - DEVICE Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x0a - DEVICE Device Address"] + pub dadd: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x0c - DEVICE Status"] + pub status: crate::Reg, + #[doc = "0x0d - Finite State Machine Status"] + pub fsmstatus: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x10 - DEVICE Device Frame Number"] + pub fnum: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x14 - DEVICE Device Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x18 - DEVICE Device Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x1c - DEVICE Device Interrupt Flag"] + pub intflag: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x20 - DEVICE End Point Interrupt Summary"] + pub epintsmry: crate::Reg, + _reserved12: [u8; 0x02], + #[doc = "0x24 - Descriptor Address"] + pub descadd: crate::Reg, + #[doc = "0x28 - USB PAD Calibration"] + pub padcal: crate::Reg, + _reserved14: [u8; 0xd6], + #[doc = "0x100..0x10a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint0: self::device::DEVICE_ENDPOINT, + _reserved15: [u8; 0x16], + #[doc = "0x120..0x12a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint1: self::device::DEVICE_ENDPOINT, + _reserved16: [u8; 0x16], + #[doc = "0x140..0x14a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint2: self::device::DEVICE_ENDPOINT, + _reserved17: [u8; 0x16], + #[doc = "0x160..0x16a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint3: self::device::DEVICE_ENDPOINT, + _reserved18: [u8; 0x16], + #[doc = "0x180..0x18a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint4: self::device::DEVICE_ENDPOINT, + _reserved19: [u8; 0x16], + #[doc = "0x1a0..0x1aa - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint5: self::device::DEVICE_ENDPOINT, + _reserved20: [u8; 0x16], + #[doc = "0x1c0..0x1ca - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint6: self::device::DEVICE_ENDPOINT, + _reserved21: [u8; 0x16], + #[doc = "0x1e0..0x1ea - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint7: self::device::DEVICE_ENDPOINT, +} +#[doc = r"Register block"] +#[doc = "USB is Device"] +pub mod device; +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x03 - USB Quality Of Service"] + pub qosctrl: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - HOST Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x0a - HOST Host Start Of Frame Control"] + pub hsofc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x0c - HOST Status"] + pub status: crate::Reg, + #[doc = "0x0d - Finite State Machine Status"] + pub fsmstatus: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x10 - HOST Host Frame Number"] + pub fnum: crate::Reg, + #[doc = "0x12 - HOST Host Frame Length"] + pub flenhigh: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x14 - HOST Host Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x18 - HOST Host Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x1c - HOST Host Interrupt Flag"] + pub intflag: crate::Reg, + _reserved12: [u8; 0x02], + #[doc = "0x20 - HOST Pipe Interrupt Summary"] + pub pintsmry: crate::Reg, + _reserved13: [u8; 0x02], + #[doc = "0x24 - Descriptor Address"] + pub descadd: crate::Reg, + #[doc = "0x28 - USB PAD Calibration"] + pub padcal: crate::Reg, + _reserved15: [u8; 0xd6], + #[doc = "0x100..0x10a - HOST_PIPE\\[%s\\]"] + pub host_pipe0: self::host::HOST_PIPE, + _reserved16: [u8; 0x16], + #[doc = "0x120..0x12a - HOST_PIPE\\[%s\\]"] + pub host_pipe1: self::host::HOST_PIPE, + _reserved17: [u8; 0x16], + #[doc = "0x140..0x14a - HOST_PIPE\\[%s\\]"] + pub host_pipe2: self::host::HOST_PIPE, + _reserved18: [u8; 0x16], + #[doc = "0x160..0x16a - HOST_PIPE\\[%s\\]"] + pub host_pipe3: self::host::HOST_PIPE, + _reserved19: [u8; 0x16], + #[doc = "0x180..0x18a - HOST_PIPE\\[%s\\]"] + pub host_pipe4: self::host::HOST_PIPE, + _reserved20: [u8; 0x16], + #[doc = "0x1a0..0x1aa - HOST_PIPE\\[%s\\]"] + pub host_pipe5: self::host::HOST_PIPE, + _reserved21: [u8; 0x16], + #[doc = "0x1c0..0x1ca - HOST_PIPE\\[%s\\]"] + pub host_pipe6: self::host::HOST_PIPE, + _reserved22: [u8; 0x16], + #[doc = "0x1e0..0x1ea - HOST_PIPE\\[%s\\]"] + pub host_pipe7: self::host::HOST_PIPE, +} +#[doc = r"Register block"] +#[doc = "USB is Host"] +pub mod host; diff --git a/pac/atsamda1e/src/usb/device.rs b/pac/atsamda1e/src/usb/device.rs new file mode 100644 index 00000000000..e5bbbadc1ca --- /dev/null +++ b/pac/atsamda1e/src/usb/device.rs @@ -0,0 +1,78 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "USB Quality Of Service"] +pub mod qosctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "DEVICE Control B"] +pub mod ctrlb; +#[doc = "DADD register accessor: an alias for `Reg`"] +pub type DADD = crate::Reg; +#[doc = "DEVICE Device Address"] +pub mod dadd; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "DEVICE Status"] +pub mod status; +#[doc = "FSMSTATUS register accessor: an alias for `Reg`"] +pub type FSMSTATUS = crate::Reg; +#[doc = "Finite State Machine Status"] +pub mod fsmstatus; +#[doc = "FNUM register accessor: an alias for `Reg`"] +pub type FNUM = crate::Reg; +#[doc = "DEVICE Device Frame Number"] +pub mod fnum; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "DEVICE Device Interrupt Flag"] +pub mod intflag; +#[doc = "EPINTSMRY register accessor: an alias for `Reg`"] +pub type EPINTSMRY = crate::Reg; +#[doc = "DEVICE End Point Interrupt Summary"] +pub mod epintsmry; +#[doc = "DESCADD register accessor: an alias for `Reg`"] +pub type DESCADD = crate::Reg; +#[doc = "Descriptor Address"] +pub mod descadd; +#[doc = "PADCAL register accessor: an alias for `Reg`"] +pub type PADCAL = crate::Reg; +#[doc = "USB PAD Calibration"] +pub mod padcal; +#[doc = r"Register block"] +#[repr(C)] +pub struct DEVICE_ENDPOINT { + #[doc = "0x00 - DEVICE_ENDPOINT End Point Configuration"] + pub epcfg: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - DEVICE_ENDPOINT End Point Pipe Status Clear"] + pub epstatusclr: crate::Reg, + #[doc = "0x05 - DEVICE_ENDPOINT End Point Pipe Status Set"] + pub epstatusset: crate::Reg, + #[doc = "0x06 - DEVICE_ENDPOINT End Point Pipe Status"] + pub epstatus: crate::Reg, + #[doc = "0x07 - DEVICE_ENDPOINT End Point Interrupt Flag"] + pub epintflag: crate::Reg, + #[doc = "0x08 - DEVICE_ENDPOINT End Point Interrupt Clear Flag"] + pub epintenclr: crate::Reg, + #[doc = "0x09 - DEVICE_ENDPOINT End Point Interrupt Set Flag"] + pub epintenset: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "DEVICE_ENDPOINT\\[%s\\]"] +pub mod device_endpoint; diff --git a/pac/atsamda1e/src/usb/device/ctrla.rs b/pac/atsamda1e/src/usb/device/ctrla.rs new file mode 100644 index 00000000000..f29253092ce --- /dev/null +++ b/pac/atsamda1e/src/usb/device/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby Mode"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby Mode"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Device Mode"] + DEVICE = 0, + #[doc = "1: Host Mode"] + HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::DEVICE, + true => MODE_A::HOST, + } + } + #[doc = "Checks if the value of the field is `DEVICE`"] + #[inline(always)] + pub fn is_device(&self) -> bool { + **self == MODE_A::DEVICE + } + #[doc = "Checks if the value of the field is `HOST`"] + #[inline(always)] + pub fn is_host(&self) -> bool { + **self == MODE_A::HOST + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Device Mode"] + #[inline(always)] + pub fn device(self) -> &'a mut W { + self.variant(MODE_A::DEVICE) + } + #[doc = "Host Mode"] + #[inline(always)] + pub fn host(self) -> &'a mut W { + self.variant(MODE_A::HOST) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/ctrlb.rs b/pac/atsamda1e/src/usb/device/ctrlb.rs new file mode 100644 index 00000000000..8c076e89255 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/ctrlb.rs @@ -0,0 +1,666 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DETACH` reader - Detach"] +pub struct DETACH_R(crate::FieldReader); +impl DETACH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DETACH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DETACH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DETACH` writer - Detach"] +pub struct DETACH_W<'a> { + w: &'a mut W, +} +impl<'a> DETACH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPDCONF_A { + #[doc = "0: FS : Full Speed"] + FS = 0, + #[doc = "1: LS : Low Speed"] + LS = 1, + #[doc = "2: HS : High Speed capable"] + HS = 2, + #[doc = "3: HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + HSTM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPDCONF_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPDCONF` reader - Speed Configuration"] +pub struct SPDCONF_R(crate::FieldReader); +impl SPDCONF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPDCONF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SPDCONF_A { + match self.bits { + 0 => SPDCONF_A::FS, + 1 => SPDCONF_A::LS, + 2 => SPDCONF_A::HS, + 3 => SPDCONF_A::HSTM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPDCONF_A::FS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + **self == SPDCONF_A::LS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + **self == SPDCONF_A::HS + } + #[doc = "Checks if the value of the field is `HSTM`"] + #[inline(always)] + pub fn is_hstm(&self) -> bool { + **self == SPDCONF_A::HSTM + } +} +impl core::ops::Deref for SPDCONF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPDCONF` writer - Speed Configuration"] +pub struct SPDCONF_W<'a> { + w: &'a mut W, +} +impl<'a> SPDCONF_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPDCONF_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "FS : Full Speed"] + #[inline(always)] + pub fn fs(self) -> &'a mut W { + self.variant(SPDCONF_A::FS) + } + #[doc = "LS : Low Speed"] + #[inline(always)] + pub fn ls(self) -> &'a mut W { + self.variant(SPDCONF_A::LS) + } + #[doc = "HS : High Speed capable"] + #[inline(always)] + pub fn hs(self) -> &'a mut W { + self.variant(SPDCONF_A::HS) + } + #[doc = "HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + #[inline(always)] + pub fn hstm(self) -> &'a mut W { + self.variant(SPDCONF_A::HSTM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `NREPLY` reader - No Reply"] +pub struct NREPLY_R(crate::FieldReader); +impl NREPLY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NREPLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NREPLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NREPLY` writer - No Reply"] +pub struct NREPLY_W<'a> { + w: &'a mut W, +} +impl<'a> NREPLY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TSTJ` reader - Test mode J"] +pub struct TSTJ_R(crate::FieldReader); +impl TSTJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTJ` writer - Test mode J"] +pub struct TSTJ_W<'a> { + w: &'a mut W, +} +impl<'a> TSTJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTK` reader - Test mode K"] +pub struct TSTK_R(crate::FieldReader); +impl TSTK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTK` writer - Test mode K"] +pub struct TSTK_W<'a> { + w: &'a mut W, +} +impl<'a> TSTK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TSTPCKT` reader - Test packet mode"] +pub struct TSTPCKT_R(crate::FieldReader); +impl TSTPCKT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTPCKT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTPCKT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTPCKT` writer - Test packet mode"] +pub struct TSTPCKT_W<'a> { + w: &'a mut W, +} +impl<'a> TSTPCKT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPMODE2` reader - Specific Operational Mode"] +pub struct OPMODE2_R(crate::FieldReader); +impl OPMODE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPMODE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPMODE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPMODE2` writer - Specific Operational Mode"] +pub struct OPMODE2_W<'a> { + w: &'a mut W, +} +impl<'a> OPMODE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GNAK` reader - Global NAK"] +pub struct GNAK_R(crate::FieldReader); +impl GNAK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GNAK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GNAK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GNAK` writer - Global NAK"] +pub struct GNAK_W<'a> { + w: &'a mut W, +} +impl<'a> GNAK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Link Power Management Handshake\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LPMHDSK_A { + #[doc = "0: No handshake. LPM is not supported"] + NO = 0, + #[doc = "1: ACK"] + ACK = 1, + #[doc = "2: NYET"] + NYET = 2, + #[doc = "3: STALL"] + STALL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LPMHDSK_A) -> Self { + variant as _ + } +} +#[doc = "Field `LPMHDSK` reader - Link Power Management Handshake"] +pub struct LPMHDSK_R(crate::FieldReader); +impl LPMHDSK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LPMHDSK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LPMHDSK_A { + match self.bits { + 0 => LPMHDSK_A::NO, + 1 => LPMHDSK_A::ACK, + 2 => LPMHDSK_A::NYET, + 3 => LPMHDSK_A::STALL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO`"] + #[inline(always)] + pub fn is_no(&self) -> bool { + **self == LPMHDSK_A::NO + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == LPMHDSK_A::ACK + } + #[doc = "Checks if the value of the field is `NYET`"] + #[inline(always)] + pub fn is_nyet(&self) -> bool { + **self == LPMHDSK_A::NYET + } + #[doc = "Checks if the value of the field is `STALL`"] + #[inline(always)] + pub fn is_stall(&self) -> bool { + **self == LPMHDSK_A::STALL + } +} +impl core::ops::Deref for LPMHDSK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMHDSK` writer - Link Power Management Handshake"] +pub struct LPMHDSK_W<'a> { + w: &'a mut W, +} +impl<'a> LPMHDSK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LPMHDSK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No handshake. LPM is not supported"] + #[inline(always)] + pub fn no(self) -> &'a mut W { + self.variant(LPMHDSK_A::NO) + } + #[doc = "ACK"] + #[inline(always)] + pub fn ack(self) -> &'a mut W { + self.variant(LPMHDSK_A::ACK) + } + #[doc = "NYET"] + #[inline(always)] + pub fn nyet(self) -> &'a mut W { + self.variant(LPMHDSK_A::NYET) + } + #[doc = "STALL"] + #[inline(always)] + pub fn stall(self) -> &'a mut W { + self.variant(LPMHDSK_A::STALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u16 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + pub fn detach(&self) -> DETACH_R { + DETACH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + pub fn spdconf(&self) -> SPDCONF_R { + SPDCONF_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + pub fn nreply(&self) -> NREPLY_R { + NREPLY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&self) -> TSTJ_R { + TSTJ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&self) -> TSTK_R { + TSTK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + pub fn tstpckt(&self) -> TSTPCKT_R { + TSTPCKT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + pub fn opmode2(&self) -> OPMODE2_R { + OPMODE2_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + pub fn gnak(&self) -> GNAK_R { + GNAK_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + pub fn lpmhdsk(&self) -> LPMHDSK_R { + LPMHDSK_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + pub fn detach(&mut self) -> DETACH_W { + DETACH_W { w: self } + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + pub fn spdconf(&mut self) -> SPDCONF_W { + SPDCONF_W { w: self } + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + pub fn nreply(&mut self) -> NREPLY_W { + NREPLY_W { w: self } + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&mut self) -> TSTJ_W { + TSTJ_W { w: self } + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&mut self) -> TSTK_W { + TSTK_W { w: self } + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + pub fn tstpckt(&mut self) -> TSTPCKT_W { + TSTPCKT_W { w: self } + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + pub fn opmode2(&mut self) -> OPMODE2_W { + OPMODE2_W { w: self } + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + pub fn gnak(&mut self) -> GNAK_W { + GNAK_W { w: self } + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + pub fn lpmhdsk(&mut self) -> LPMHDSK_W { + LPMHDSK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x01"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1e/src/usb/device/dadd.rs b/pac/atsamda1e/src/usb/device/dadd.rs new file mode 100644 index 00000000000..36cc57b728b --- /dev/null +++ b/pac/atsamda1e/src/usb/device/dadd.rs @@ -0,0 +1,150 @@ +#[doc = "Register `DADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DADD` reader - Device Address"] +pub struct DADD_R(crate::FieldReader); +impl DADD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DADD` writer - Device Address"] +pub struct DADD_W<'a> { + w: &'a mut W, +} +impl<'a> DADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `ADDEN` reader - Device Address Enable"] +pub struct ADDEN_R(crate::FieldReader); +impl ADDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDEN` writer - Device Address Enable"] +pub struct ADDEN_W<'a> { + w: &'a mut W, +} +impl<'a> ADDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + pub fn dadd(&self) -> DADD_R { + DADD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + pub fn adden(&self) -> ADDEN_R { + ADDEN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + pub fn dadd(&mut self) -> DADD_W { + DADD_W { w: self } + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + pub fn adden(&mut self) -> ADDEN_W { + ADDEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dadd](index.html) module"] +pub struct DADD_SPEC; +impl crate::RegisterSpec for DADD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dadd::R](R) reader structure"] +impl crate::Readable for DADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dadd::W](W) writer structure"] +impl crate::Writable for DADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DADD to value 0"] +impl crate::Resettable for DADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/descadd.rs b/pac/atsamda1e/src/usb/device/descadd.rs new file mode 100644 index 00000000000..9fe18a8dcb2 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/descadd.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DESCADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DESCADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCADD` reader - Descriptor Address Value"] +pub struct DESCADD_R(crate::FieldReader); +impl DESCADD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCADD` writer - Descriptor Address Value"] +pub struct DESCADD_W<'a> { + w: &'a mut W, +} +impl<'a> DESCADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&self) -> DESCADD_R { + DESCADD_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&mut self) -> DESCADD_W { + DESCADD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [descadd](index.html) module"] +pub struct DESCADD_SPEC; +impl crate::RegisterSpec for DESCADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [descadd::R](R) reader structure"] +impl crate::Readable for DESCADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [descadd::W](W) writer structure"] +impl crate::Writable for DESCADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DESCADD to value 0"] +impl crate::Resettable for DESCADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/device_endpoint.rs b/pac/atsamda1e/src/usb/device/device_endpoint.rs new file mode 100644 index 00000000000..b0722149fb9 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint.rs @@ -0,0 +1,28 @@ +#[doc = "EPCFG register accessor: an alias for `Reg`"] +pub type EPCFG = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Configuration"] +pub mod epcfg; +#[doc = "EPSTATUSCLR register accessor: an alias for `Reg`"] +pub type EPSTATUSCLR = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Clear"] +pub mod epstatusclr; +#[doc = "EPSTATUSSET register accessor: an alias for `Reg`"] +pub type EPSTATUSSET = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Set"] +pub mod epstatusset; +#[doc = "EPSTATUS register accessor: an alias for `Reg`"] +pub type EPSTATUS = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status"] +pub mod epstatus; +#[doc = "EPINTFLAG register accessor: an alias for `Reg`"] +pub type EPINTFLAG = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Flag"] +pub mod epintflag; +#[doc = "EPINTENCLR register accessor: an alias for `Reg`"] +pub type EPINTENCLR = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Clear Flag"] +pub mod epintenclr; +#[doc = "EPINTENSET register accessor: an alias for `Reg`"] +pub type EPINTENSET = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Set Flag"] +pub mod epintenset; diff --git a/pac/atsamda1e/src/usb/device/device_endpoint/epcfg.rs b/pac/atsamda1e/src/usb/device/device_endpoint/epcfg.rs new file mode 100644 index 00000000000..08d635693e7 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint/epcfg.rs @@ -0,0 +1,187 @@ +#[doc = "Register `EPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EPTYPE0` reader - End Point Type0"] +pub struct EPTYPE0_R(crate::FieldReader); +impl EPTYPE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EPTYPE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPTYPE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPTYPE0` writer - End Point Type0"] +pub struct EPTYPE0_W<'a> { + w: &'a mut W, +} +impl<'a> EPTYPE0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `EPTYPE1` reader - End Point Type1"] +pub struct EPTYPE1_R(crate::FieldReader); +impl EPTYPE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EPTYPE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPTYPE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPTYPE1` writer - End Point Type1"] +pub struct EPTYPE1_W<'a> { + w: &'a mut W, +} +impl<'a> EPTYPE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +#[doc = "Field `NYETDIS` reader - NYET Token Disable"] +pub struct NYETDIS_R(crate::FieldReader); +impl NYETDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NYETDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NYETDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NYETDIS` writer - NYET Token Disable"] +pub struct NYETDIS_W<'a> { + w: &'a mut W, +} +impl<'a> NYETDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + pub fn eptype0(&self) -> EPTYPE0_R { + EPTYPE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + pub fn eptype1(&self) -> EPTYPE1_R { + EPTYPE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + pub fn nyetdis(&self) -> NYETDIS_R { + NYETDIS_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + pub fn eptype0(&mut self) -> EPTYPE0_W { + EPTYPE0_W { w: self } + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + pub fn eptype1(&mut self) -> EPTYPE1_W { + EPTYPE1_W { w: self } + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + pub fn nyetdis(&mut self) -> NYETDIS_W { + NYETDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epcfg](index.html) module"] +pub struct EPCFG_SPEC; +impl crate::RegisterSpec for EPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epcfg::R](R) reader structure"] +impl crate::Readable for EPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epcfg::W](W) writer structure"] +impl crate::Writable for EPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPCFG to value 0"] +impl crate::Resettable for EPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/device_endpoint/epintenclr.rs b/pac/atsamda1e/src/usb/device/device_endpoint/epintenclr.rs new file mode 100644 index 00000000000..50e8a9188e4 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint/epintenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Disable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Disable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Disable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Disable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Disable"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Disable"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Disable"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Disable"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Disable"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Disable"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/Out Interrupt Disable"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/Out Interrupt Disable"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/Out Interrupt Disable"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/Out Interrupt Disable"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Clear Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenclr](index.html) module"] +pub struct EPINTENCLR_SPEC; +impl crate::RegisterSpec for EPINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenclr::R](R) reader structure"] +impl crate::Readable for EPINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenclr::W](W) writer structure"] +impl crate::Writable for EPINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTENCLR to value 0"] +impl crate::Resettable for EPINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/device_endpoint/epintenset.rs b/pac/atsamda1e/src/usb/device/device_endpoint/epintenset.rs new file mode 100644 index 00000000000..1df6b33a143 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint/epintenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Enable"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Enable"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Enable"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Enable"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Enable"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Enable"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/out Interrupt enable"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/out Interrupt enable"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/out Interrupt enable"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/out Interrupt enable"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Set Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenset](index.html) module"] +pub struct EPINTENSET_SPEC; +impl crate::RegisterSpec for EPINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenset::R](R) reader structure"] +impl crate::Readable for EPINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenset::W](W) writer structure"] +impl crate::Writable for EPINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTENSET to value 0"] +impl crate::Resettable for EPINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/device_endpoint/epintflag.rs b/pac/atsamda1e/src/usb/device/device_endpoint/epintflag.rs new file mode 100644 index 00000000000..8af2f8266fd --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint/epintflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/out"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/out"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/out"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/out"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintflag](index.html) module"] +pub struct EPINTFLAG_SPEC; +impl crate::RegisterSpec for EPINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintflag::R](R) reader structure"] +impl crate::Readable for EPINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintflag::W](W) writer structure"] +impl crate::Writable for EPINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTFLAG to value 0"] +impl crate::Resettable for EPINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/device_endpoint/epstatus.rs b/pac/atsamda1e/src/usb/device/device_endpoint/epstatus.rs new file mode 100644 index 00000000000..e5c544090f1 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint/epstatus.rs @@ -0,0 +1,173 @@ +#[doc = "Register `EPSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DTGLOUT` reader - Data Toggle Out"] +pub struct DTGLOUT_R(crate::FieldReader); +impl DTGLOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGLOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGLOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTGLIN` reader - Data Toggle In"] +pub struct DTGLIN_R(crate::FieldReader); +impl DTGLIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGLIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGLIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURBK` reader - Current Bank"] +pub struct CURBK_R(crate::FieldReader); +impl CURBK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CURBK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURBK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLRQ0` reader - Stall 0 Request"] +pub struct STALLRQ0_R(crate::FieldReader); +impl STALLRQ0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLRQ0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLRQ0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLRQ1` reader - Stall 1 Request"] +pub struct STALLRQ1_R(crate::FieldReader); +impl STALLRQ1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLRQ1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLRQ1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK0RDY` reader - Bank 0 ready"] +pub struct BK0RDY_R(crate::FieldReader); +impl BK0RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK0RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK0RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK1RDY` reader - Bank 1 ready"] +pub struct BK1RDY_R(crate::FieldReader); +impl BK1RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK1RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK1RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Data Toggle Out"] + #[inline(always)] + pub fn dtglout(&self) -> DTGLOUT_R { + DTGLOUT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Toggle In"] + #[inline(always)] + pub fn dtglin(&self) -> DTGLIN_R { + DTGLIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Current Bank"] + #[inline(always)] + pub fn curbk(&self) -> CURBK_R { + CURBK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Stall 0 Request"] + #[inline(always)] + pub fn stallrq0(&self) -> STALLRQ0_R { + STALLRQ0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 1 Request"] + #[inline(always)] + pub fn stallrq1(&self) -> STALLRQ1_R { + STALLRQ1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Bank 0 ready"] + #[inline(always)] + pub fn bk0rdy(&self) -> BK0RDY_R { + BK0RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bank 1 ready"] + #[inline(always)] + pub fn bk1rdy(&self) -> BK1RDY_R { + BK1RDY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatus](index.html) module"] +pub struct EPSTATUS_SPEC; +impl crate::RegisterSpec for EPSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epstatus::R](R) reader structure"] +impl crate::Readable for EPSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPSTATUS to value 0"] +impl crate::Resettable for EPSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/device_endpoint/epstatusclr.rs b/pac/atsamda1e/src/usb/device/device_endpoint/epstatusclr.rs new file mode 100644 index 00000000000..1c6a8b11556 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint/epstatusclr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `EPSTATUSCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Clear"] +pub struct DTGLOUT_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DTGLIN` writer - Data Toggle IN Clear"] +pub struct DTGLIN_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CURBK` writer - Curren Bank Clear"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Clear"] +pub struct STALLRQ0_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Clear"] +pub struct STALLRQ1_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Clear"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Clear"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle OUT Clear"] + #[inline(always)] + pub fn dtglout(&mut self) -> DTGLOUT_W { + DTGLOUT_W { w: self } + } + #[doc = "Bit 1 - Data Toggle IN Clear"] + #[inline(always)] + pub fn dtglin(&mut self) -> DTGLIN_W { + DTGLIN_W { w: self } + } + #[doc = "Bit 2 - Curren Bank Clear"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Stall 0 Request Clear"] + #[inline(always)] + pub fn stallrq0(&mut self) -> STALLRQ0_W { + STALLRQ0_W { w: self } + } + #[doc = "Bit 5 - Stall 1 Request Clear"] + #[inline(always)] + pub fn stallrq1(&mut self) -> STALLRQ1_W { + STALLRQ1_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Clear"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Clear"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusclr](index.html) module"] +pub struct EPSTATUSCLR_SPEC; +impl crate::RegisterSpec for EPSTATUSCLR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusclr::W](W) writer structure"] +impl crate::Writable for EPSTATUSCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPSTATUSCLR to value 0"] +impl crate::Resettable for EPSTATUSCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/device_endpoint/epstatusset.rs b/pac/atsamda1e/src/usb/device/device_endpoint/epstatusset.rs new file mode 100644 index 00000000000..a5bfce5a635 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/device_endpoint/epstatusset.rs @@ -0,0 +1,234 @@ +#[doc = "Register `EPSTATUSSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Set"] +pub struct DTGLOUT_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DTGLIN` writer - Data Toggle IN Set"] +pub struct DTGLIN_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CURBK` writer - Current Bank Set"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Set"] +pub struct STALLRQ0_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Set"] +pub struct STALLRQ1_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Set"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Set"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle OUT Set"] + #[inline(always)] + pub fn dtglout(&mut self) -> DTGLOUT_W { + DTGLOUT_W { w: self } + } + #[doc = "Bit 1 - Data Toggle IN Set"] + #[inline(always)] + pub fn dtglin(&mut self) -> DTGLIN_W { + DTGLIN_W { w: self } + } + #[doc = "Bit 2 - Current Bank Set"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Stall 0 Request Set"] + #[inline(always)] + pub fn stallrq0(&mut self) -> STALLRQ0_W { + STALLRQ0_W { w: self } + } + #[doc = "Bit 5 - Stall 1 Request Set"] + #[inline(always)] + pub fn stallrq1(&mut self) -> STALLRQ1_W { + STALLRQ1_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Set"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Set"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusset](index.html) module"] +pub struct EPSTATUSSET_SPEC; +impl crate::RegisterSpec for EPSTATUSSET_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusset::W](W) writer structure"] +impl crate::Writable for EPSTATUSSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPSTATUSSET to value 0"] +impl crate::Resettable for EPSTATUSSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/epintsmry.rs b/pac/atsamda1e/src/usb/device/epintsmry.rs new file mode 100644 index 00000000000..9b62c194598 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/epintsmry.rs @@ -0,0 +1,193 @@ +#[doc = "Register `EPINTSMRY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPINT0` reader - End Point 0 Interrupt"] +pub struct EPINT0_R(crate::FieldReader); +impl EPINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT1` reader - End Point 1 Interrupt"] +pub struct EPINT1_R(crate::FieldReader); +impl EPINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT2` reader - End Point 2 Interrupt"] +pub struct EPINT2_R(crate::FieldReader); +impl EPINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT3` reader - End Point 3 Interrupt"] +pub struct EPINT3_R(crate::FieldReader); +impl EPINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT4` reader - End Point 4 Interrupt"] +pub struct EPINT4_R(crate::FieldReader); +impl EPINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT5` reader - End Point 5 Interrupt"] +pub struct EPINT5_R(crate::FieldReader); +impl EPINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT6` reader - End Point 6 Interrupt"] +pub struct EPINT6_R(crate::FieldReader); +impl EPINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT7` reader - End Point 7 Interrupt"] +pub struct EPINT7_R(crate::FieldReader); +impl EPINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - End Point 0 Interrupt"] + #[inline(always)] + pub fn epint0(&self) -> EPINT0_R { + EPINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - End Point 1 Interrupt"] + #[inline(always)] + pub fn epint1(&self) -> EPINT1_R { + EPINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - End Point 2 Interrupt"] + #[inline(always)] + pub fn epint2(&self) -> EPINT2_R { + EPINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End Point 3 Interrupt"] + #[inline(always)] + pub fn epint3(&self) -> EPINT3_R { + EPINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - End Point 4 Interrupt"] + #[inline(always)] + pub fn epint4(&self) -> EPINT4_R { + EPINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Point 5 Interrupt"] + #[inline(always)] + pub fn epint5(&self) -> EPINT5_R { + EPINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - End Point 6 Interrupt"] + #[inline(always)] + pub fn epint6(&self) -> EPINT6_R { + EPINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - End Point 7 Interrupt"] + #[inline(always)] + pub fn epint7(&self) -> EPINT7_R { + EPINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "DEVICE End Point Interrupt Summary\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintsmry](index.html) module"] +pub struct EPINTSMRY_SPEC; +impl crate::RegisterSpec for EPINTSMRY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [epintsmry::R](R) reader structure"] +impl crate::Readable for EPINTSMRY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPINTSMRY to value 0"] +impl crate::Resettable for EPINTSMRY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/fnum.rs b/pac/atsamda1e/src/usb/device/fnum.rs new file mode 100644 index 00000000000..761148868fc --- /dev/null +++ b/pac/atsamda1e/src/usb/device/fnum.rs @@ -0,0 +1,93 @@ +#[doc = "Register `FNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MFNUM` reader - Micro Frame Number"] +pub struct MFNUM_R(crate::FieldReader); +impl MFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNUM` reader - Frame Number"] +pub struct FNUM_R(crate::FieldReader); +impl FNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNCERR` reader - Frame Number CRC Error"] +pub struct FNCERR_R(crate::FieldReader); +impl FNCERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FNCERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNCERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&self) -> MFNUM_R { + MFNUM_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&self) -> FNUM_R { + FNUM_R::new(((self.bits >> 3) & 0x07ff) as u16) + } + #[doc = "Bit 15 - Frame Number CRC Error"] + #[inline(always)] + pub fn fncerr(&self) -> FNCERR_R { + FNCERR_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "DEVICE Device Frame Number\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fnum](index.html) module"] +pub struct FNUM_SPEC; +impl crate::RegisterSpec for FNUM_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [fnum::R](R) reader structure"] +impl crate::Readable for FNUM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FNUM to value 0"] +impl crate::Resettable for FNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/fsmstatus.rs b/pac/atsamda1e/src/usb/device/fsmstatus.rs new file mode 100644 index 00000000000..a89e8172c39 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/fsmstatus.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FSMSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Fine State Machine Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSMSTATE_A { + #[doc = "1: OFF (L3). It corresponds to the powered-off, disconnected, and disabled state"] + OFF = 1, + #[doc = "2: ON (L0). It corresponds to the Idle and Active states"] + ON = 2, + #[doc = "4: SUSPEND (L2)"] + SUSPEND = 4, + #[doc = "8: SLEEP (L1)"] + SLEEP = 8, + #[doc = "16: DNRESUME. Down Stream Resume."] + DNRESUME = 16, + #[doc = "32: UPRESUME. Up Stream Resume."] + UPRESUME = 32, + #[doc = "64: RESET. USB lines Reset."] + RESET = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSMSTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSMSTATE` reader - Fine State Machine Status"] +pub struct FSMSTATE_R(crate::FieldReader); +impl FSMSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSMSTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(FSMSTATE_A::OFF), + 2 => Some(FSMSTATE_A::ON), + 4 => Some(FSMSTATE_A::SUSPEND), + 8 => Some(FSMSTATE_A::SLEEP), + 16 => Some(FSMSTATE_A::DNRESUME), + 32 => Some(FSMSTATE_A::UPRESUME), + 64 => Some(FSMSTATE_A::RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FSMSTATE_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + **self == FSMSTATE_A::ON + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == FSMSTATE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `SLEEP`"] + #[inline(always)] + pub fn is_sleep(&self) -> bool { + **self == FSMSTATE_A::SLEEP + } + #[doc = "Checks if the value of the field is `DNRESUME`"] + #[inline(always)] + pub fn is_dnresume(&self) -> bool { + **self == FSMSTATE_A::DNRESUME + } + #[doc = "Checks if the value of the field is `UPRESUME`"] + #[inline(always)] + pub fn is_upresume(&self) -> bool { + **self == FSMSTATE_A::UPRESUME + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == FSMSTATE_A::RESET + } +} +impl core::ops::Deref for FSMSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Fine State Machine Status"] + #[inline(always)] + pub fn fsmstate(&self) -> FSMSTATE_R { + FSMSTATE_R::new((self.bits & 0x7f) as u8) + } +} +#[doc = "Finite State Machine Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmstatus](index.html) module"] +pub struct FSMSTATUS_SPEC; +impl crate::RegisterSpec for FSMSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fsmstatus::R](R) reader structure"] +impl crate::Readable for FSMSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FSMSTATUS to value 0x01"] +impl crate::Resettable for FSMSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1e/src/usb/device/intenclr.rs b/pac/atsamda1e/src/usb/device/intenclr.rs new file mode 100644 index 00000000000..feffea27e6f --- /dev/null +++ b/pac/atsamda1e/src/usb/device/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/intenset.rs b/pac/atsamda1e/src/usb/device/intenset.rs new file mode 100644 index 00000000000..3f525c20e6a --- /dev/null +++ b/pac/atsamda1e/src/usb/device/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/intflag.rs b/pac/atsamda1e/src/usb/device/intflag.rs new file mode 100644 index 00000000000..1b52bfae973 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/padcal.rs b/pac/atsamda1e/src/usb/device/padcal.rs new file mode 100644 index 00000000000..9b11d4fc687 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/padcal.rs @@ -0,0 +1,177 @@ +#[doc = "Register `PADCAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PADCAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRANSP` reader - USB Pad Transp calibration"] +pub struct TRANSP_R(crate::FieldReader); +impl TRANSP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSP` writer - USB Pad Transp calibration"] +pub struct TRANSP_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `TRANSN` reader - USB Pad Transn calibration"] +pub struct TRANSN_R(crate::FieldReader); +impl TRANSN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSN` writer - USB Pad Transn calibration"] +pub struct TRANSN_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 6)) | ((value as u16 & 0x1f) << 6); + self.w + } +} +#[doc = "Field `TRIM` reader - USB Pad Trim calibration"] +pub struct TRIM_R(crate::FieldReader); +impl TRIM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIM` writer - USB Pad Trim calibration"] +pub struct TRIM_W<'a> { + w: &'a mut W, +} +impl<'a> TRIM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u16 & 0x07) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&self) -> TRANSP_R { + TRANSP_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&self) -> TRANSN_R { + TRANSN_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 12) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&mut self) -> TRANSP_W { + TRANSP_W { w: self } + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&mut self) -> TRANSN_W { + TRANSN_W { w: self } + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&mut self) -> TRIM_W { + TRIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB PAD Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [padcal](index.html) module"] +pub struct PADCAL_SPEC; +impl crate::RegisterSpec for PADCAL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [padcal::R](R) reader structure"] +impl crate::Readable for PADCAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [padcal::W](W) writer structure"] +impl crate::Writable for PADCAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PADCAL to value 0"] +impl crate::Resettable for PADCAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/device/qosctrl.rs b/pac/atsamda1e/src/usb/device/qosctrl.rs new file mode 100644 index 00000000000..86b85a16067 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/qosctrl.rs @@ -0,0 +1,290 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Configuration Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `CQOS` reader - Configuration Quality of Service"] +pub struct CQOS_R(crate::FieldReader); +impl CQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CQOS_A { + match self.bits { + 0 => CQOS_A::DISABLE, + 1 => CQOS_A::LOW, + 2 => CQOS_A::MEDIUM, + 3 => CQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == CQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == CQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == CQOS_A::HIGH + } +} +impl core::ops::Deref for CQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CQOS` writer - Configuration Quality of Service"] +pub struct CQOS_W<'a> { + w: &'a mut W, +} +impl<'a> CQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(CQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(CQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(CQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Data Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&self) -> CQOS_R { + CQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&mut self) -> CQOS_W { + CQOS_W { w: self } + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB Quality Of Service\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x05"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1e/src/usb/device/status.rs b/pac/atsamda1e/src/usb/device/status.rs new file mode 100644 index 00000000000..ef62be58537 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/status.rs @@ -0,0 +1,157 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Speed Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Full-speed mode"] + FS = 0, + #[doc = "1: High-speed mode"] + HS = 1, + #[doc = "2: Low-speed mode"] + LS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Status"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::FS), + 1 => Some(SPEED_A::HS), + 2 => Some(SPEED_A::LS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPEED_A::FS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + **self == SPEED_A::HS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + **self == SPEED_A::LS + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "USB Line State Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LINESTATE_A { + #[doc = "0: SE0/RESET"] + _0 = 0, + #[doc = "1: FS-J or LS-K State"] + _1 = 1, + #[doc = "2: FS-K or LS-J State"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LINESTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `LINESTATE` reader - USB Line State Status"] +pub struct LINESTATE_R(crate::FieldReader); +impl LINESTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINESTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LINESTATE_A::_0), + 1 => Some(LINESTATE_A::_1), + 2 => Some(LINESTATE_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == LINESTATE_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == LINESTATE_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == LINESTATE_A::_2 + } +} +impl core::ops::Deref for LINESTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&self) -> LINESTATE_R { + LINESTATE_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "DEVICE Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x40"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x40 + } +} diff --git a/pac/atsamda1e/src/usb/device/syncbusy.rs b/pac/atsamda1e/src/usb/device/syncbusy.rs new file mode 100644 index 00000000000..5f22af98954 --- /dev/null +++ b/pac/atsamda1e/src/usb/device/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host.rs b/pac/atsamda1e/src/usb/host.rs new file mode 100644 index 00000000000..4f2a018f914 --- /dev/null +++ b/pac/atsamda1e/src/usb/host.rs @@ -0,0 +1,84 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "USB Quality Of Service"] +pub mod qosctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "HOST Control B"] +pub mod ctrlb; +#[doc = "HSOFC register accessor: an alias for `Reg`"] +pub type HSOFC = crate::Reg; +#[doc = "HOST Host Start Of Frame Control"] +pub mod hsofc; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "HOST Status"] +pub mod status; +#[doc = "FSMSTATUS register accessor: an alias for `Reg`"] +pub type FSMSTATUS = crate::Reg; +#[doc = "Finite State Machine Status"] +pub mod fsmstatus; +#[doc = "FNUM register accessor: an alias for `Reg`"] +pub type FNUM = crate::Reg; +#[doc = "HOST Host Frame Number"] +pub mod fnum; +#[doc = "FLENHIGH register accessor: an alias for `Reg`"] +pub type FLENHIGH = crate::Reg; +#[doc = "HOST Host Frame Length"] +pub mod flenhigh; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "HOST Host Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "HOST Host Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "HOST Host Interrupt Flag"] +pub mod intflag; +#[doc = "PINTSMRY register accessor: an alias for `Reg`"] +pub type PINTSMRY = crate::Reg; +#[doc = "HOST Pipe Interrupt Summary"] +pub mod pintsmry; +#[doc = "DESCADD register accessor: an alias for `Reg`"] +pub type DESCADD = crate::Reg; +#[doc = "Descriptor Address"] +pub mod descadd; +#[doc = "PADCAL register accessor: an alias for `Reg`"] +pub type PADCAL = crate::Reg; +#[doc = "USB PAD Calibration"] +pub mod padcal; +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST_PIPE { + #[doc = "0x00 - HOST_PIPE End Point Configuration"] + pub pcfg: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x03 - HOST_PIPE Bus Access Period of Pipe"] + pub binterval: crate::Reg, + #[doc = "0x04 - HOST_PIPE End Point Pipe Status Clear"] + pub pstatusclr: crate::Reg, + #[doc = "0x05 - HOST_PIPE End Point Pipe Status Set"] + pub pstatusset: crate::Reg, + #[doc = "0x06 - HOST_PIPE End Point Pipe Status"] + pub pstatus: crate::Reg, + #[doc = "0x07 - HOST_PIPE Pipe Interrupt Flag"] + pub pintflag: crate::Reg, + #[doc = "0x08 - HOST_PIPE Pipe Interrupt Flag Clear"] + pub pintenclr: crate::Reg, + #[doc = "0x09 - HOST_PIPE Pipe Interrupt Flag Set"] + pub pintenset: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "HOST_PIPE\\[%s\\]"] +pub mod host_pipe; diff --git a/pac/atsamda1e/src/usb/host/ctrla.rs b/pac/atsamda1e/src/usb/host/ctrla.rs new file mode 100644 index 00000000000..f29253092ce --- /dev/null +++ b/pac/atsamda1e/src/usb/host/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby Mode"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby Mode"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Device Mode"] + DEVICE = 0, + #[doc = "1: Host Mode"] + HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::DEVICE, + true => MODE_A::HOST, + } + } + #[doc = "Checks if the value of the field is `DEVICE`"] + #[inline(always)] + pub fn is_device(&self) -> bool { + **self == MODE_A::DEVICE + } + #[doc = "Checks if the value of the field is `HOST`"] + #[inline(always)] + pub fn is_host(&self) -> bool { + **self == MODE_A::HOST + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Device Mode"] + #[inline(always)] + pub fn device(self) -> &'a mut W { + self.variant(MODE_A::DEVICE) + } + #[doc = "Host Mode"] + #[inline(always)] + pub fn host(self) -> &'a mut W { + self.variant(MODE_A::HOST) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/ctrlb.rs b/pac/atsamda1e/src/usb/host/ctrlb.rs new file mode 100644 index 00000000000..59536faa219 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/ctrlb.rs @@ -0,0 +1,481 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESUME` reader - Send USB Resume"] +pub struct RESUME_R(crate::FieldReader); +impl RESUME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESUME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESUME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESUME` writer - Send USB Resume"] +pub struct RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Configuration for Host\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPDCONF_A { + #[doc = "0: Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable."] + NORMAL = 0, + #[doc = "3: Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only."] + FS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPDCONF_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPDCONF` reader - Speed Configuration for Host"] +pub struct SPDCONF_R(crate::FieldReader); +impl SPDCONF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPDCONF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPDCONF_A::NORMAL), + 3 => Some(SPDCONF_A::FS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NORMAL`"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + **self == SPDCONF_A::NORMAL + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPDCONF_A::FS + } +} +impl core::ops::Deref for SPDCONF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPDCONF` writer - Speed Configuration for Host"] +pub struct SPDCONF_W<'a> { + w: &'a mut W, +} +impl<'a> SPDCONF_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPDCONF_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable."] + #[inline(always)] + pub fn normal(self) -> &'a mut W { + self.variant(SPDCONF_A::NORMAL) + } + #[doc = "Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only."] + #[inline(always)] + pub fn fs(self) -> &'a mut W { + self.variant(SPDCONF_A::FS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `TSTJ` reader - Test mode J"] +pub struct TSTJ_R(crate::FieldReader); +impl TSTJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTJ` writer - Test mode J"] +pub struct TSTJ_W<'a> { + w: &'a mut W, +} +impl<'a> TSTJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTK` reader - Test mode K"] +pub struct TSTK_R(crate::FieldReader); +impl TSTK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTK` writer - Test mode K"] +pub struct TSTK_W<'a> { + w: &'a mut W, +} +impl<'a> TSTK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SOFE` reader - Start of Frame Generation Enable"] +pub struct SOFE_R(crate::FieldReader); +impl SOFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOFE` writer - Start of Frame Generation Enable"] +pub struct SOFE_W<'a> { + w: &'a mut W, +} +impl<'a> SOFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BUSRESET` reader - Send USB Reset"] +pub struct BUSRESET_R(crate::FieldReader); +impl BUSRESET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSRESET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSRESET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSRESET` writer - Send USB Reset"] +pub struct BUSRESET_W<'a> { + w: &'a mut W, +} +impl<'a> BUSRESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `VBUSOK` reader - VBUS is OK"] +pub struct VBUSOK_R(crate::FieldReader); +impl VBUSOK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VBUSOK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VBUSOK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VBUSOK` writer - VBUS is OK"] +pub struct VBUSOK_W<'a> { + w: &'a mut W, +} +impl<'a> VBUSOK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `L1RESUME` reader - Send L1 Resume"] +pub struct L1RESUME_R(crate::FieldReader); +impl L1RESUME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + L1RESUME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for L1RESUME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `L1RESUME` writer - Send L1 Resume"] +pub struct L1RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> L1RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 1 - Send USB Resume"] + #[inline(always)] + pub fn resume(&self) -> RESUME_R { + RESUME_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Configuration for Host"] + #[inline(always)] + pub fn spdconf(&self) -> SPDCONF_R { + SPDCONF_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&self) -> TSTJ_R { + TSTJ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&self) -> TSTK_R { + TSTK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Start of Frame Generation Enable"] + #[inline(always)] + pub fn sofe(&self) -> SOFE_R { + SOFE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Send USB Reset"] + #[inline(always)] + pub fn busreset(&self) -> BUSRESET_R { + BUSRESET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - VBUS is OK"] + #[inline(always)] + pub fn vbusok(&self) -> VBUSOK_R { + VBUSOK_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Send L1 Resume"] + #[inline(always)] + pub fn l1resume(&self) -> L1RESUME_R { + L1RESUME_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Send USB Resume"] + #[inline(always)] + pub fn resume(&mut self) -> RESUME_W { + RESUME_W { w: self } + } + #[doc = "Bits 2:3 - Speed Configuration for Host"] + #[inline(always)] + pub fn spdconf(&mut self) -> SPDCONF_W { + SPDCONF_W { w: self } + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&mut self) -> TSTJ_W { + TSTJ_W { w: self } + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&mut self) -> TSTK_W { + TSTK_W { w: self } + } + #[doc = "Bit 8 - Start of Frame Generation Enable"] + #[inline(always)] + pub fn sofe(&mut self) -> SOFE_W { + SOFE_W { w: self } + } + #[doc = "Bit 9 - Send USB Reset"] + #[inline(always)] + pub fn busreset(&mut self) -> BUSRESET_W { + BUSRESET_W { w: self } + } + #[doc = "Bit 10 - VBUS is OK"] + #[inline(always)] + pub fn vbusok(&mut self) -> VBUSOK_W { + VBUSOK_W { w: self } + } + #[doc = "Bit 11 - Send L1 Resume"] + #[inline(always)] + pub fn l1resume(&mut self) -> L1RESUME_W { + L1RESUME_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/descadd.rs b/pac/atsamda1e/src/usb/host/descadd.rs new file mode 100644 index 00000000000..9fe18a8dcb2 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/descadd.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DESCADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DESCADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCADD` reader - Descriptor Address Value"] +pub struct DESCADD_R(crate::FieldReader); +impl DESCADD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCADD` writer - Descriptor Address Value"] +pub struct DESCADD_W<'a> { + w: &'a mut W, +} +impl<'a> DESCADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&self) -> DESCADD_R { + DESCADD_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&mut self) -> DESCADD_W { + DESCADD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [descadd](index.html) module"] +pub struct DESCADD_SPEC; +impl crate::RegisterSpec for DESCADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [descadd::R](R) reader structure"] +impl crate::Readable for DESCADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [descadd::W](W) writer structure"] +impl crate::Writable for DESCADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DESCADD to value 0"] +impl crate::Resettable for DESCADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/flenhigh.rs b/pac/atsamda1e/src/usb/host/flenhigh.rs new file mode 100644 index 00000000000..ab9d58be29b --- /dev/null +++ b/pac/atsamda1e/src/usb/host/flenhigh.rs @@ -0,0 +1,53 @@ +#[doc = "Register `FLENHIGH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FLENHIGH` reader - Frame Length"] +pub struct FLENHIGH_R(crate::FieldReader); +impl FLENHIGH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLENHIGH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENHIGH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Frame Length"] + #[inline(always)] + pub fn flenhigh(&self) -> FLENHIGH_R { + FLENHIGH_R::new(self.bits as u8) + } +} +#[doc = "HOST Host Frame Length\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flenhigh](index.html) module"] +pub struct FLENHIGH_SPEC; +impl crate::RegisterSpec for FLENHIGH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [flenhigh::R](R) reader structure"] +impl crate::Readable for FLENHIGH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FLENHIGH to value 0"] +impl crate::Resettable for FLENHIGH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/fnum.rs b/pac/atsamda1e/src/usb/host/fnum.rs new file mode 100644 index 00000000000..cc5f2b47dce --- /dev/null +++ b/pac/atsamda1e/src/usb/host/fnum.rs @@ -0,0 +1,140 @@ +#[doc = "Register `FNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MFNUM` reader - Micro Frame Number"] +pub struct MFNUM_R(crate::FieldReader); +impl MFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MFNUM` writer - Micro Frame Number"] +pub struct MFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> MFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `FNUM` reader - Frame Number"] +pub struct FNUM_R(crate::FieldReader); +impl FNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNUM` writer - Frame Number"] +pub struct FNUM_W<'a> { + w: &'a mut W, +} +impl<'a> FNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 3)) | ((value as u16 & 0x07ff) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&self) -> MFNUM_R { + MFNUM_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&self) -> FNUM_R { + FNUM_R::new(((self.bits >> 3) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&mut self) -> MFNUM_W { + MFNUM_W { w: self } + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&mut self) -> FNUM_W { + FNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Frame Number\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fnum](index.html) module"] +pub struct FNUM_SPEC; +impl crate::RegisterSpec for FNUM_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [fnum::R](R) reader structure"] +impl crate::Readable for FNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fnum::W](W) writer structure"] +impl crate::Writable for FNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FNUM to value 0"] +impl crate::Resettable for FNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/fsmstatus.rs b/pac/atsamda1e/src/usb/host/fsmstatus.rs new file mode 100644 index 00000000000..a89e8172c39 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/fsmstatus.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FSMSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Fine State Machine Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSMSTATE_A { + #[doc = "1: OFF (L3). It corresponds to the powered-off, disconnected, and disabled state"] + OFF = 1, + #[doc = "2: ON (L0). It corresponds to the Idle and Active states"] + ON = 2, + #[doc = "4: SUSPEND (L2)"] + SUSPEND = 4, + #[doc = "8: SLEEP (L1)"] + SLEEP = 8, + #[doc = "16: DNRESUME. Down Stream Resume."] + DNRESUME = 16, + #[doc = "32: UPRESUME. Up Stream Resume."] + UPRESUME = 32, + #[doc = "64: RESET. USB lines Reset."] + RESET = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSMSTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSMSTATE` reader - Fine State Machine Status"] +pub struct FSMSTATE_R(crate::FieldReader); +impl FSMSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSMSTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(FSMSTATE_A::OFF), + 2 => Some(FSMSTATE_A::ON), + 4 => Some(FSMSTATE_A::SUSPEND), + 8 => Some(FSMSTATE_A::SLEEP), + 16 => Some(FSMSTATE_A::DNRESUME), + 32 => Some(FSMSTATE_A::UPRESUME), + 64 => Some(FSMSTATE_A::RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FSMSTATE_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + **self == FSMSTATE_A::ON + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == FSMSTATE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `SLEEP`"] + #[inline(always)] + pub fn is_sleep(&self) -> bool { + **self == FSMSTATE_A::SLEEP + } + #[doc = "Checks if the value of the field is `DNRESUME`"] + #[inline(always)] + pub fn is_dnresume(&self) -> bool { + **self == FSMSTATE_A::DNRESUME + } + #[doc = "Checks if the value of the field is `UPRESUME`"] + #[inline(always)] + pub fn is_upresume(&self) -> bool { + **self == FSMSTATE_A::UPRESUME + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == FSMSTATE_A::RESET + } +} +impl core::ops::Deref for FSMSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Fine State Machine Status"] + #[inline(always)] + pub fn fsmstate(&self) -> FSMSTATE_R { + FSMSTATE_R::new((self.bits & 0x7f) as u8) + } +} +#[doc = "Finite State Machine Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmstatus](index.html) module"] +pub struct FSMSTATUS_SPEC; +impl crate::RegisterSpec for FSMSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fsmstatus::R](R) reader structure"] +impl crate::Readable for FSMSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FSMSTATUS to value 0x01"] +impl crate::Resettable for FSMSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe.rs b/pac/atsamda1e/src/usb/host/host_pipe.rs new file mode 100644 index 00000000000..e0a917f3a12 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe.rs @@ -0,0 +1,32 @@ +#[doc = "PCFG register accessor: an alias for `Reg`"] +pub type PCFG = crate::Reg; +#[doc = "HOST_PIPE End Point Configuration"] +pub mod pcfg; +#[doc = "BINTERVAL register accessor: an alias for `Reg`"] +pub type BINTERVAL = crate::Reg; +#[doc = "HOST_PIPE Bus Access Period of Pipe"] +pub mod binterval; +#[doc = "PSTATUSCLR register accessor: an alias for `Reg`"] +pub type PSTATUSCLR = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status Clear"] +pub mod pstatusclr; +#[doc = "PSTATUSSET register accessor: an alias for `Reg`"] +pub type PSTATUSSET = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status Set"] +pub mod pstatusset; +#[doc = "PSTATUS register accessor: an alias for `Reg`"] +pub type PSTATUS = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status"] +pub mod pstatus; +#[doc = "PINTFLAG register accessor: an alias for `Reg`"] +pub type PINTFLAG = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag"] +pub mod pintflag; +#[doc = "PINTENCLR register accessor: an alias for `Reg`"] +pub type PINTENCLR = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag Clear"] +pub mod pintenclr; +#[doc = "PINTENSET register accessor: an alias for `Reg`"] +pub type PINTENSET = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag Set"] +pub mod pintenset; diff --git a/pac/atsamda1e/src/usb/host/host_pipe/binterval.rs b/pac/atsamda1e/src/usb/host/host_pipe/binterval.rs new file mode 100644 index 00000000000..7b29db1e3d6 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/binterval.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BINTERVAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BINTERVAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BITINTERVAL` reader - Bit Interval"] +pub struct BITINTERVAL_R(crate::FieldReader); +impl BITINTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BITINTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BITINTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITINTERVAL` writer - Bit Interval"] +pub struct BITINTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BITINTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Bit Interval"] + #[inline(always)] + pub fn bitinterval(&self) -> BITINTERVAL_R { + BITINTERVAL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Bit Interval"] + #[inline(always)] + pub fn bitinterval(&mut self) -> BITINTERVAL_W { + BITINTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Bus Access Period of Pipe\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [binterval](index.html) module"] +pub struct BINTERVAL_SPEC; +impl crate::RegisterSpec for BINTERVAL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [binterval::R](R) reader structure"] +impl crate::Readable for BINTERVAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [binterval::W](W) writer structure"] +impl crate::Writable for BINTERVAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BINTERVAL to value 0"] +impl crate::Resettable for BINTERVAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe/pcfg.rs b/pac/atsamda1e/src/usb/host/host_pipe/pcfg.rs new file mode 100644 index 00000000000..c6677dce494 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/pcfg.rs @@ -0,0 +1,187 @@ +#[doc = "Register `PCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTOKEN` reader - Pipe Token"] +pub struct PTOKEN_R(crate::FieldReader); +impl PTOKEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PTOKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTOKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTOKEN` writer - Pipe Token"] +pub struct PTOKEN_W<'a> { + w: &'a mut W, +} +impl<'a> PTOKEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Field `BK` reader - Pipe Bank"] +pub struct BK_R(crate::FieldReader); +impl BK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK` writer - Pipe Bank"] +pub struct BK_W<'a> { + w: &'a mut W, +} +impl<'a> BK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PTYPE` reader - Pipe Type"] +pub struct PTYPE_R(crate::FieldReader); +impl PTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PTYPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTYPE` writer - Pipe Type"] +pub struct PTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> PTYPE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u8 & 0x07) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Pipe Token"] + #[inline(always)] + pub fn ptoken(&self) -> PTOKEN_R { + PTOKEN_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Pipe Bank"] + #[inline(always)] + pub fn bk(&self) -> BK_R { + BK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:5 - Pipe Type"] + #[inline(always)] + pub fn ptype(&self) -> PTYPE_R { + PTYPE_R::new(((self.bits >> 3) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Pipe Token"] + #[inline(always)] + pub fn ptoken(&mut self) -> PTOKEN_W { + PTOKEN_W { w: self } + } + #[doc = "Bit 2 - Pipe Bank"] + #[inline(always)] + pub fn bk(&mut self) -> BK_W { + BK_W { w: self } + } + #[doc = "Bits 3:5 - Pipe Type"] + #[inline(always)] + pub fn ptype(&mut self) -> PTYPE_W { + PTYPE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcfg](index.html) module"] +pub struct PCFG_SPEC; +impl crate::RegisterSpec for PCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pcfg::R](R) reader structure"] +impl crate::Readable for PCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pcfg::W](W) writer structure"] +impl crate::Writable for PCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCFG to value 0"] +impl crate::Resettable for PCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe/pintenclr.rs b/pac/atsamda1e/src/usb/host/host_pipe/pintenclr.rs new file mode 100644 index 00000000000..d994194d579 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/pintenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Disable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Disable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Disable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Disable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Disable"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Disable"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Disable"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Disable"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Disable"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Disable"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Disable"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Disable"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Disable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Disable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Disable"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Disable"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Disable"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Disable"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Disable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Disable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Disable"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Disable"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Disable"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Disable"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintenclr](index.html) module"] +pub struct PINTENCLR_SPEC; +impl crate::RegisterSpec for PINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintenclr::R](R) reader structure"] +impl crate::Readable for PINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintenclr::W](W) writer structure"] +impl crate::Writable for PINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTENCLR to value 0"] +impl crate::Resettable for PINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe/pintenset.rs b/pac/atsamda1e/src/usb/host/host_pipe/pintenset.rs new file mode 100644 index 00000000000..fc7368fe117 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/pintenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Enable"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Enable"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Enable"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Enable"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Enable"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Enable"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Enable"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Enable"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Enable"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Enable"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Enable"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Enable"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Enable"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Enable"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Enable"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Enable"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintenset](index.html) module"] +pub struct PINTENSET_SPEC; +impl crate::RegisterSpec for PINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintenset::R](R) reader structure"] +impl crate::Readable for PINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintenset::W](W) writer structure"] +impl crate::Writable for PINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTENSET to value 0"] +impl crate::Resettable for PINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe/pintflag.rs b/pac/atsamda1e/src/usb/host/host_pipe/pintflag.rs new file mode 100644 index 00000000000..9724af9984c --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/pintflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Flag"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Flag"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Flag"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Flag"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Flag"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Flag"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Flag"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Flag"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Flag"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Flag"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Flag"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Flag"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Flag"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Flag"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Flag"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Flag"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Flag"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Flag"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Flag"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Flag"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Flag"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Flag"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintflag](index.html) module"] +pub struct PINTFLAG_SPEC; +impl crate::RegisterSpec for PINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintflag::R](R) reader structure"] +impl crate::Readable for PINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintflag::W](W) writer structure"] +impl crate::Writable for PINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTFLAG to value 0"] +impl crate::Resettable for PINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe/pstatus.rs b/pac/atsamda1e/src/usb/host/host_pipe/pstatus.rs new file mode 100644 index 00000000000..072b3621ff5 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/pstatus.rs @@ -0,0 +1,133 @@ +#[doc = "Register `PSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DTGL` reader - Data Toggle"] +pub struct DTGL_R(crate::FieldReader); +impl DTGL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURBK` reader - Current Bank"] +pub struct CURBK_R(crate::FieldReader); +impl CURBK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CURBK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURBK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PFREEZE` reader - Pipe Freeze"] +pub struct PFREEZE_R(crate::FieldReader); +impl PFREEZE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PFREEZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PFREEZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK0RDY` reader - Bank 0 ready"] +pub struct BK0RDY_R(crate::FieldReader); +impl BK0RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK0RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK0RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK1RDY` reader - Bank 1 ready"] +pub struct BK1RDY_R(crate::FieldReader); +impl BK1RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK1RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK1RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Data Toggle"] + #[inline(always)] + pub fn dtgl(&self) -> DTGL_R { + DTGL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Current Bank"] + #[inline(always)] + pub fn curbk(&self) -> CURBK_R { + CURBK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Pipe Freeze"] + #[inline(always)] + pub fn pfreeze(&self) -> PFREEZE_R { + PFREEZE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Bank 0 ready"] + #[inline(always)] + pub fn bk0rdy(&self) -> BK0RDY_R { + BK0RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bank 1 ready"] + #[inline(always)] + pub fn bk1rdy(&self) -> BK1RDY_R { + BK1RDY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "HOST_PIPE End Point Pipe Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatus](index.html) module"] +pub struct PSTATUS_SPEC; +impl crate::RegisterSpec for PSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pstatus::R](R) reader structure"] +impl crate::Readable for PSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PSTATUS to value 0"] +impl crate::Resettable for PSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe/pstatusclr.rs b/pac/atsamda1e/src/usb/host/host_pipe/pstatusclr.rs new file mode 100644 index 00000000000..6fb40667a9d --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/pstatusclr.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PSTATUSCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGL` writer - Data Toggle clear"] +pub struct DTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DTGL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CURBK` writer - Curren Bank clear"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PFREEZE` writer - Pipe Freeze Clear"] +pub struct PFREEZE_W<'a> { + w: &'a mut W, +} +impl<'a> PFREEZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Clear"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Clear"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle clear"] + #[inline(always)] + pub fn dtgl(&mut self) -> DTGL_W { + DTGL_W { w: self } + } + #[doc = "Bit 2 - Curren Bank clear"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Pipe Freeze Clear"] + #[inline(always)] + pub fn pfreeze(&mut self) -> PFREEZE_W { + PFREEZE_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Clear"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Clear"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Pipe Status Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatusclr](index.html) module"] +pub struct PSTATUSCLR_SPEC; +impl crate::RegisterSpec for PSTATUSCLR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [pstatusclr::W](W) writer structure"] +impl crate::Writable for PSTATUSCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSTATUSCLR to value 0"] +impl crate::Resettable for PSTATUSCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/host_pipe/pstatusset.rs b/pac/atsamda1e/src/usb/host/host_pipe/pstatusset.rs new file mode 100644 index 00000000000..2d3e855e41f --- /dev/null +++ b/pac/atsamda1e/src/usb/host/host_pipe/pstatusset.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PSTATUSSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGL` writer - Data Toggle Set"] +pub struct DTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DTGL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CURBK` writer - Current Bank Set"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PFREEZE` writer - Pipe Freeze Set"] +pub struct PFREEZE_W<'a> { + w: &'a mut W, +} +impl<'a> PFREEZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Set"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Set"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle Set"] + #[inline(always)] + pub fn dtgl(&mut self) -> DTGL_W { + DTGL_W { w: self } + } + #[doc = "Bit 2 - Current Bank Set"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Pipe Freeze Set"] + #[inline(always)] + pub fn pfreeze(&mut self) -> PFREEZE_W { + PFREEZE_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Set"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Set"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Pipe Status Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatusset](index.html) module"] +pub struct PSTATUSSET_SPEC; +impl crate::RegisterSpec for PSTATUSSET_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [pstatusset::W](W) writer structure"] +impl crate::Writable for PSTATUSSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSTATUSSET to value 0"] +impl crate::Resettable for PSTATUSSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/hsofc.rs b/pac/atsamda1e/src/usb/host/hsofc.rs new file mode 100644 index 00000000000..bc714a862ff --- /dev/null +++ b/pac/atsamda1e/src/usb/host/hsofc.rs @@ -0,0 +1,150 @@ +#[doc = "Register `HSOFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HSOFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLENC` reader - Frame Length Control"] +pub struct FLENC_R(crate::FieldReader); +impl FLENC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLENC` writer - Frame Length Control"] +pub struct FLENC_W<'a> { + w: &'a mut W, +} +impl<'a> FLENC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `FLENCE` reader - Frame Length Control Enable"] +pub struct FLENCE_R(crate::FieldReader); +impl FLENCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLENCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLENCE` writer - Frame Length Control Enable"] +pub struct FLENCE_W<'a> { + w: &'a mut W, +} +impl<'a> FLENCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Frame Length Control"] + #[inline(always)] + pub fn flenc(&self) -> FLENC_R { + FLENC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Frame Length Control Enable"] + #[inline(always)] + pub fn flence(&self) -> FLENCE_R { + FLENCE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Frame Length Control"] + #[inline(always)] + pub fn flenc(&mut self) -> FLENC_W { + FLENC_W { w: self } + } + #[doc = "Bit 7 - Frame Length Control Enable"] + #[inline(always)] + pub fn flence(&mut self) -> FLENCE_W { + FLENCE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Start Of Frame Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hsofc](index.html) module"] +pub struct HSOFC_SPEC; +impl crate::RegisterSpec for HSOFC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [hsofc::R](R) reader structure"] +impl crate::Readable for HSOFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hsofc::W](W) writer structure"] +impl crate::Writable for HSOFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HSOFC to value 0"] +impl crate::Resettable for HSOFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/intenclr.rs b/pac/atsamda1e/src/usb/host/intenclr.rs new file mode 100644 index 00000000000..df6a7c7b78e --- /dev/null +++ b/pac/atsamda1e/src/usb/host/intenclr.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Disable"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Disable"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - BUS Reset Interrupt Disable"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - BUS Reset Interrupt Disable"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Disable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Disable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - DownStream to Device Interrupt Disable"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - DownStream to Device Interrupt Disable"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume from Device Interrupt Disable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume from Device Interrupt Disable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Disable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Disable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Device Connection Interrupt Disable"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Device Connection Interrupt Disable"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Disable"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Disable"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BUS Reset Interrupt Disable"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Disable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Disable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Device Connection Interrupt Disable"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - BUS Reset Interrupt Disable"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Disable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Disable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Device Connection Interrupt Disable"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/intenset.rs b/pac/atsamda1e/src/usb/host/intenset.rs new file mode 100644 index 00000000000..dce5e3a61f7 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/intenset.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Enable"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Enable"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - Bus Reset Interrupt Enable"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - Bus Reset Interrupt Enable"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - DownStream to the Device Interrupt Enable"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - DownStream to the Device Interrupt Enable"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume fromthe device Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume fromthe device Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Link Power Management Interrupt Enable"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Link Power Management Interrupt Enable"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Enable"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Enable"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Bus Reset Interrupt Enable"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DownStream to the Device Interrupt Enable"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume fromthe device Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Interrupt Enable"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection Interrupt Enable"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - Bus Reset Interrupt Enable"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - DownStream to the Device Interrupt Enable"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume fromthe device Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Interrupt Enable"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection Interrupt Enable"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/intflag.rs b/pac/atsamda1e/src/usb/host/intflag.rs new file mode 100644 index 00000000000..14fbcfb2d1a --- /dev/null +++ b/pac/atsamda1e/src/usb/host/intflag.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - Bus Reset"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - Bus Reset"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - Downstream"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - Downstream"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume from the Device"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume from the Device"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Device Connection"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Device Connection"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Bus Reset"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Downstream"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume from the Device"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Device Connection"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - Bus Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - Downstream"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume from the Device"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Device Connection"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/padcal.rs b/pac/atsamda1e/src/usb/host/padcal.rs new file mode 100644 index 00000000000..9b11d4fc687 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/padcal.rs @@ -0,0 +1,177 @@ +#[doc = "Register `PADCAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PADCAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRANSP` reader - USB Pad Transp calibration"] +pub struct TRANSP_R(crate::FieldReader); +impl TRANSP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSP` writer - USB Pad Transp calibration"] +pub struct TRANSP_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `TRANSN` reader - USB Pad Transn calibration"] +pub struct TRANSN_R(crate::FieldReader); +impl TRANSN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSN` writer - USB Pad Transn calibration"] +pub struct TRANSN_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 6)) | ((value as u16 & 0x1f) << 6); + self.w + } +} +#[doc = "Field `TRIM` reader - USB Pad Trim calibration"] +pub struct TRIM_R(crate::FieldReader); +impl TRIM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIM` writer - USB Pad Trim calibration"] +pub struct TRIM_W<'a> { + w: &'a mut W, +} +impl<'a> TRIM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u16 & 0x07) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&self) -> TRANSP_R { + TRANSP_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&self) -> TRANSN_R { + TRANSN_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 12) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&mut self) -> TRANSP_W { + TRANSP_W { w: self } + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&mut self) -> TRANSN_W { + TRANSN_W { w: self } + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&mut self) -> TRIM_W { + TRIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB PAD Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [padcal](index.html) module"] +pub struct PADCAL_SPEC; +impl crate::RegisterSpec for PADCAL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [padcal::R](R) reader structure"] +impl crate::Readable for PADCAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [padcal::W](W) writer structure"] +impl crate::Writable for PADCAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PADCAL to value 0"] +impl crate::Resettable for PADCAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/pintsmry.rs b/pac/atsamda1e/src/usb/host/pintsmry.rs new file mode 100644 index 00000000000..bc0fba3f12e --- /dev/null +++ b/pac/atsamda1e/src/usb/host/pintsmry.rs @@ -0,0 +1,193 @@ +#[doc = "Register `PINTSMRY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPINT0` reader - Pipe 0 Interrupt"] +pub struct EPINT0_R(crate::FieldReader); +impl EPINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT1` reader - Pipe 1 Interrupt"] +pub struct EPINT1_R(crate::FieldReader); +impl EPINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT2` reader - Pipe 2 Interrupt"] +pub struct EPINT2_R(crate::FieldReader); +impl EPINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT3` reader - Pipe 3 Interrupt"] +pub struct EPINT3_R(crate::FieldReader); +impl EPINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT4` reader - Pipe 4 Interrupt"] +pub struct EPINT4_R(crate::FieldReader); +impl EPINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT5` reader - Pipe 5 Interrupt"] +pub struct EPINT5_R(crate::FieldReader); +impl EPINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT6` reader - Pipe 6 Interrupt"] +pub struct EPINT6_R(crate::FieldReader); +impl EPINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT7` reader - Pipe 7 Interrupt"] +pub struct EPINT7_R(crate::FieldReader); +impl EPINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pipe 0 Interrupt"] + #[inline(always)] + pub fn epint0(&self) -> EPINT0_R { + EPINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pipe 1 Interrupt"] + #[inline(always)] + pub fn epint1(&self) -> EPINT1_R { + EPINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pipe 2 Interrupt"] + #[inline(always)] + pub fn epint2(&self) -> EPINT2_R { + EPINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe 3 Interrupt"] + #[inline(always)] + pub fn epint3(&self) -> EPINT3_R { + EPINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pipe 4 Interrupt"] + #[inline(always)] + pub fn epint4(&self) -> EPINT4_R { + EPINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pipe 5 Interrupt"] + #[inline(always)] + pub fn epint5(&self) -> EPINT5_R { + EPINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pipe 6 Interrupt"] + #[inline(always)] + pub fn epint6(&self) -> EPINT6_R { + EPINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pipe 7 Interrupt"] + #[inline(always)] + pub fn epint7(&self) -> EPINT7_R { + EPINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "HOST Pipe Interrupt Summary\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintsmry](index.html) module"] +pub struct PINTSMRY_SPEC; +impl crate::RegisterSpec for PINTSMRY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pintsmry::R](R) reader structure"] +impl crate::Readable for PINTSMRY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PINTSMRY to value 0"] +impl crate::Resettable for PINTSMRY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/qosctrl.rs b/pac/atsamda1e/src/usb/host/qosctrl.rs new file mode 100644 index 00000000000..86b85a16067 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/qosctrl.rs @@ -0,0 +1,290 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Configuration Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `CQOS` reader - Configuration Quality of Service"] +pub struct CQOS_R(crate::FieldReader); +impl CQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CQOS_A { + match self.bits { + 0 => CQOS_A::DISABLE, + 1 => CQOS_A::LOW, + 2 => CQOS_A::MEDIUM, + 3 => CQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == CQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == CQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == CQOS_A::HIGH + } +} +impl core::ops::Deref for CQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CQOS` writer - Configuration Quality of Service"] +pub struct CQOS_W<'a> { + w: &'a mut W, +} +impl<'a> CQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(CQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(CQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(CQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Data Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&self) -> CQOS_R { + CQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&mut self) -> CQOS_W { + CQOS_W { w: self } + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB Quality Of Service\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x05"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1e/src/usb/host/status.rs b/pac/atsamda1e/src/usb/host/status.rs new file mode 100644 index 00000000000..45cf612fdac --- /dev/null +++ b/pac/atsamda1e/src/usb/host/status.rs @@ -0,0 +1,140 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPEED` reader - Speed Status"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Status"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Field `LINESTATE` reader - USB Line State Status"] +pub struct LINESTATE_R(crate::FieldReader); +impl LINESTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINESTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINESTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINESTATE` writer - USB Line State Status"] +pub struct LINESTATE_W<'a> { + w: &'a mut W, +} +impl<'a> LINESTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&self) -> LINESTATE_R { + LINESTATE_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&mut self) -> LINESTATE_W { + LINESTATE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/usb/host/syncbusy.rs b/pac/atsamda1e/src/usb/host/syncbusy.rs new file mode 100644 index 00000000000..5f22af98954 --- /dev/null +++ b/pac/atsamda1e/src/usb/host/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/wdt.rs b/pac/atsamda1e/src/wdt.rs new file mode 100644 index 00000000000..0c5da61ba13 --- /dev/null +++ b/pac/atsamda1e/src/wdt.rs @@ -0,0 +1,53 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamda1e/src/wdt/clear.rs b/pac/atsamda1e/src/wdt/clear.rs new file mode 100644 index 00000000000..61ee21f3246 --- /dev/null +++ b/pac/atsamda1e/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/wdt/config.rs b/pac/atsamda1e/src/wdt/config.rs new file mode 100644 index 00000000000..b87e8a0a9bd --- /dev/null +++ b/pac/atsamda1e/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::_8), + 1 => Some(PER_A::_16), + 2 => Some(PER_A::_32), + 3 => Some(PER_A::_64), + 4 => Some(PER_A::_128), + 5 => Some(PER_A::_256), + 6 => Some(PER_A::_512), + 7 => Some(PER_A::_1K), + 8 => Some(PER_A::_2K), + 9 => Some(PER_A::_4K), + 10 => Some(PER_A::_8K), + 11 => Some(PER_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PER_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PER_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PER_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PER_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PER_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PER_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PER_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == PER_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == PER_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == PER_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == PER_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == PER_A::_16K + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PER_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PER_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PER_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PER_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PER_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PER_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PER_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(PER_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(PER_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(PER_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(PER_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(PER_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::_8), + 1 => Some(WINDOW_A::_16), + 2 => Some(WINDOW_A::_32), + 3 => Some(WINDOW_A::_64), + 4 => Some(WINDOW_A::_128), + 5 => Some(WINDOW_A::_256), + 6 => Some(WINDOW_A::_512), + 7 => Some(WINDOW_A::_1K), + 8 => Some(WINDOW_A::_2K), + 9 => Some(WINDOW_A::_4K), + 10 => Some(WINDOW_A::_8K), + 11 => Some(WINDOW_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == WINDOW_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == WINDOW_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == WINDOW_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == WINDOW_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == WINDOW_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == WINDOW_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == WINDOW_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == WINDOW_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == WINDOW_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == WINDOW_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == WINDOW_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == WINDOW_A::_16K + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(WINDOW_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(WINDOW_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(WINDOW_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(WINDOW_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(WINDOW_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(WINDOW_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(WINDOW_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(WINDOW_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(WINDOW_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(WINDOW_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(WINDOW_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(WINDOW_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamda1e/src/wdt/ctrl.rs b/pac/atsamda1e/src/wdt/ctrl.rs new file mode 100644 index 00000000000..d312316d919 --- /dev/null +++ b/pac/atsamda1e/src/wdt/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/wdt/ewctrl.rs b/pac/atsamda1e/src/wdt/ewctrl.rs new file mode 100644 index 00000000000..6c7e31273c3 --- /dev/null +++ b/pac/atsamda1e/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::_8), + 1 => Some(EWOFFSET_A::_16), + 2 => Some(EWOFFSET_A::_32), + 3 => Some(EWOFFSET_A::_64), + 4 => Some(EWOFFSET_A::_128), + 5 => Some(EWOFFSET_A::_256), + 6 => Some(EWOFFSET_A::_512), + 7 => Some(EWOFFSET_A::_1K), + 8 => Some(EWOFFSET_A::_2K), + 9 => Some(EWOFFSET_A::_4K), + 10 => Some(EWOFFSET_A::_8K), + 11 => Some(EWOFFSET_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == EWOFFSET_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == EWOFFSET_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == EWOFFSET_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == EWOFFSET_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == EWOFFSET_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == EWOFFSET_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == EWOFFSET_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == EWOFFSET_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == EWOFFSET_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == EWOFFSET_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == EWOFFSET_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == EWOFFSET_A::_16K + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(EWOFFSET_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(EWOFFSET_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(EWOFFSET_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(EWOFFSET_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(EWOFFSET_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(EWOFFSET_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(EWOFFSET_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamda1e/src/wdt/intenclr.rs b/pac/atsamda1e/src/wdt/intenclr.rs new file mode 100644 index 00000000000..ed4021f96cc --- /dev/null +++ b/pac/atsamda1e/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/wdt/intenset.rs b/pac/atsamda1e/src/wdt/intenset.rs new file mode 100644 index 00000000000..5a0928ff053 --- /dev/null +++ b/pac/atsamda1e/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/wdt/intflag.rs b/pac/atsamda1e/src/wdt/intflag.rs new file mode 100644 index 00000000000..f2c9b858a19 --- /dev/null +++ b/pac/atsamda1e/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1e/src/wdt/status.rs b/pac/atsamda1e/src/wdt/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1e/src/wdt/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/Cargo.toml b/pac/atsamda1g/Cargo.toml new file mode 100644 index 00000000000..bc43c659972 --- /dev/null +++ b/pac/atsamda1g/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamda1g" +description = "Peripheral access API for ATSAMDA1G microcontrollers (generated using svd2rust)" +version = "0.12.0" +authors = ["Wez Furlong ", "Paul Sajna "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamda1g/README.md b/pac/atsamda1g/README.md new file mode 100644 index 00000000000..ad10d5d3083 --- /dev/null +++ b/pac/atsamda1g/README.md @@ -0,0 +1,26 @@ +# ATSAMDA1G + +A peripheral access crate for the ATSAMDA1G chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamda1g.svg)](https://crates.io/crates/atsamda1g) + +## [Documentation](https://docs.rs/atsamda1g) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamda1g/build.rs b/pac/atsamda1g/build.rs new file mode 100644 index 00000000000..597923f5089 --- /dev/null +++ b/pac/atsamda1g/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamda1g/device.x b/pac/atsamda1g/device.x new file mode 100644 index 00000000000..c0f686af5ad --- /dev/null +++ b/pac/atsamda1g/device.x @@ -0,0 +1,29 @@ +PROVIDE(PM = DefaultHandler); +PROVIDE(SYSCTRL = DefaultHandler); +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(USB = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(SERCOM4 = DefaultHandler); +PROVIDE(SERCOM5 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(TC5 = DefaultHandler); +PROVIDE(TC6 = DefaultHandler); +PROVIDE(TC7 = DefaultHandler); +PROVIDE(ADC = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(DAC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); +PROVIDE(I2S = DefaultHandler); + diff --git a/pac/atsamda1g/src/ac.rs b/pac/atsamda1g/src/ac.rs new file mode 100644 index 00000000000..ed9e2eeafde --- /dev/null +++ b/pac/atsamda1g/src/ac.rs @@ -0,0 +1,80 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x09 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x0a - Status C"] + pub statusc: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x0c - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x03], + #[doc = "0x10..0x18 - Comparator Control n"] + pub compctrl: [crate::Reg; 2], + _reserved11: [u8; 0x08], + #[doc = "0x20 - Scaler n"] + pub scaler: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; diff --git a/pac/atsamda1g/src/ac/compctrl.rs b/pac/atsamda1g/src/ac/compctrl.rs new file mode 100644 index 00000000000..531766edc60 --- /dev/null +++ b/pac/atsamda1g/src/ac/compctrl.rs @@ -0,0 +1,927 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "1: High speed"] + HIGH = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 1 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEG_A { + match self.bits { + 0 => MUXNEG_A::PIN0, + 1 => MUXNEG_A::PIN1, + 2 => MUXNEG_A::PIN2, + 3 => MUXNEG_A::PIN3, + 4 => MUXNEG_A::GND, + 5 => MUXNEG_A::VSCALE, + 6 => MUXNEG_A::BANDGAP, + 7 => MUXNEG_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXNEG_A::DAC + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEG_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXPOS_A { + match self.bits { + 0 => MUXPOS_A::PIN0, + 1 => MUXPOS_A::PIN1, + 2 => MUXPOS_A::PIN2, + 3 => MUXPOS_A::PIN3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:13 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 2:3 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bits 5:6 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:13 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/ctrla.rs b/pac/atsamda1g/src/ac/ctrla.rs new file mode 100644 index 00000000000..1a9beb48325 --- /dev/null +++ b/pac/atsamda1g/src/ac/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LPMUX` reader - Low-Power Mux"] +pub struct LPMUX_R(crate::FieldReader); +impl LPMUX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMUX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMUX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMUX` writer - Low-Power Mux"] +pub struct LPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> LPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Low-Power Mux"] + #[inline(always)] + pub fn lpmux(&self) -> LPMUX_R { + LPMUX_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Low-Power Mux"] + #[inline(always)] + pub fn lpmux(&mut self) -> LPMUX_W { + LPMUX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/ctrlb.rs b/pac/atsamda1g/src/ac/ctrlb.rs new file mode 100644 index 00000000000..68aa8d2a20b --- /dev/null +++ b/pac/atsamda1g/src/ac/ctrlb.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/evctrl.rs b/pac/atsamda1g/src/ac/evctrl.rs new file mode 100644 index 00000000000..88fbebc8430 --- /dev/null +++ b/pac/atsamda1g/src/ac/evctrl.rs @@ -0,0 +1,301 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/intenclr.rs b/pac/atsamda1g/src/ac/intenclr.rs new file mode 100644 index 00000000000..45e3320d293 --- /dev/null +++ b/pac/atsamda1g/src/ac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/intenset.rs b/pac/atsamda1g/src/ac/intenset.rs new file mode 100644 index 00000000000..5354a4d111d --- /dev/null +++ b/pac/atsamda1g/src/ac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/intflag.rs b/pac/atsamda1g/src/ac/intflag.rs new file mode 100644 index 00000000000..7da0fea7569 --- /dev/null +++ b/pac/atsamda1g/src/ac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/scaler.rs b/pac/atsamda1g/src/ac/scaler.rs new file mode 100644 index 00000000000..091cacfaeb4 --- /dev/null +++ b/pac/atsamda1g/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/statusa.rs b/pac/atsamda1g/src/ac/statusa.rs new file mode 100644 index 00000000000..7b98c567e8a --- /dev/null +++ b/pac/atsamda1g/src/ac/statusa.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/statusb.rs b/pac/atsamda1g/src/ac/statusb.rs new file mode 100644 index 00000000000..fa16c8bda71 --- /dev/null +++ b/pac/atsamda1g/src/ac/statusb.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/statusc.rs b/pac/atsamda1g/src/ac/statusc.rs new file mode 100644 index 00000000000..7bef2226d54 --- /dev/null +++ b/pac/atsamda1g/src/ac/statusc.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/ac/winctrl.rs b/pac/atsamda1g/src/ac/winctrl.rs new file mode 100644 index 00000000000..3259570489e --- /dev/null +++ b/pac/atsamda1g/src/ac/winctrl.rs @@ -0,0 +1,225 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc.rs b/pac/atsamda1g/src/adc.rs new file mode 100644 index 00000000000..33524a423c2 --- /dev/null +++ b/pac/atsamda1g/src/adc.rs @@ -0,0 +1,130 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x02 - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x03 - Sampling Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x08 - Window Monitor Control"] + pub winctrl: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x0c - Software Trigger"] + pub swtrig: crate::Reg, + _reserved7: [u8; 0x03], + #[doc = "0x10 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x14 - Event Control"] + pub evctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x16 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x17 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x19 - Status"] + pub status: crate::Reg, + #[doc = "0x1a - Result"] + pub result: crate::Reg, + #[doc = "0x1c - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + _reserved15: [u8; 0x02], + #[doc = "0x20 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x24 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x26 - Offset Correction"] + pub offsetcorr: crate::Reg, + #[doc = "0x28 - Calibration"] + pub calib: crate::Reg, + #[doc = "0x2a - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sampling Time Control"] +pub mod sampctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Monitor Control"] +pub mod winctrl; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1g/src/adc/avgctrl.rs b/pac/atsamda1g/src/adc/avgctrl.rs new file mode 100644 index 00000000000..ddb735715c9 --- /dev/null +++ b/pac/atsamda1g/src/adc/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/calib.rs b/pac/atsamda1g/src/adc/calib.rs new file mode 100644 index 00000000000..553ad515946 --- /dev/null +++ b/pac/atsamda1g/src/adc/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LINEARITY_CAL` reader - Linearity Calibration Value"] +pub struct LINEARITY_CAL_R(crate::FieldReader); +impl LINEARITY_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINEARITY_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINEARITY_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINEARITY_CAL` writer - Linearity Calibration Value"] +pub struct LINEARITY_CAL_W<'a> { + w: &'a mut W, +} +impl<'a> LINEARITY_CAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Field `BIAS_CAL` reader - Bias Calibration Value"] +pub struct BIAS_CAL_R(crate::FieldReader); +impl BIAS_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIAS_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIAS_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIAS_CAL` writer - Bias Calibration Value"] +pub struct BIAS_CAL_W<'a> { + w: &'a mut W, +} +impl<'a> BIAS_CAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Linearity Calibration Value"] + #[inline(always)] + pub fn linearity_cal(&self) -> LINEARITY_CAL_R { + LINEARITY_CAL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Bias Calibration Value"] + #[inline(always)] + pub fn bias_cal(&self) -> BIAS_CAL_R { + BIAS_CAL_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Linearity Calibration Value"] + #[inline(always)] + pub fn linearity_cal(&mut self) -> LINEARITY_CAL_W { + LINEARITY_CAL_W { w: self } + } + #[doc = "Bits 8:10 - Bias Calibration Value"] + #[inline(always)] + pub fn bias_cal(&mut self) -> BIAS_CAL_W { + BIAS_CAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/ctrla.rs b/pac/atsamda1g/src/adc/ctrla.rs new file mode 100644 index 00000000000..117922e5aae --- /dev/null +++ b/pac/atsamda1g/src/adc/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/ctrlb.rs b/pac/atsamda1g/src/adc/ctrlb.rs new file mode 100644 index 00000000000..79137605c46 --- /dev/null +++ b/pac/atsamda1g/src/adc/ctrlb.rs @@ -0,0 +1,530 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enabled"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enabled"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit result"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit result"] + _10BIT = 2, + #[doc = "3: 8-bit result"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit result"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit result"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit result"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 4"] + DIV4 = 0, + #[doc = "1: Peripheral clock divided by 8"] + DIV8 = 1, + #[doc = "2: Peripheral clock divided by 16"] + DIV16 = 2, + #[doc = "3: Peripheral clock divided by 32"] + DIV32 = 3, + #[doc = "4: Peripheral clock divided by 64"] + DIV64 = 4, + #[doc = "5: Peripheral clock divided by 128"] + DIV128 = 5, + #[doc = "6: Peripheral clock divided by 256"] + DIV256 = 6, + #[doc = "7: Peripheral clock divided by 512"] + DIV512 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV4, + 1 => PRESCALER_A::DIV8, + 2 => PRESCALER_A::DIV16, + 3 => PRESCALER_A::DIV32, + 4 => PRESCALER_A::DIV64, + 5 => PRESCALER_A::DIV128, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV512, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Peripheral clock divided by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enabled"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enabled"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/dbgctrl.rs b/pac/atsamda1g/src/adc/dbgctrl.rs new file mode 100644 index 00000000000..53636eb2b33 --- /dev/null +++ b/pac/atsamda1g/src/adc/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/evctrl.rs b/pac/atsamda1g/src/adc/evctrl.rs new file mode 100644 index 00000000000..cf040e96c73 --- /dev/null +++ b/pac/atsamda1g/src/adc/evctrl.rs @@ -0,0 +1,254 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event In"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event In"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCEI` reader - Synchronization Event In"] +pub struct SYNCEI_R(crate::FieldReader); +impl SYNCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCEI` writer - Synchronization Event In"] +pub struct SYNCEI_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event In"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Synchronization Event In"] + #[inline(always)] + pub fn syncei(&self) -> SYNCEI_R { + SYNCEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event In"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Synchronization Event In"] + #[inline(always)] + pub fn syncei(&mut self) -> SYNCEI_W { + SYNCEI_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/gaincorr.rs b/pac/atsamda1g/src/adc/gaincorr.rs new file mode 100644 index 00000000000..496cb8c6021 --- /dev/null +++ b/pac/atsamda1g/src/adc/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/inputctrl.rs b/pac/atsamda1g/src/adc/inputctrl.rs new file mode 100644 index 00000000000..8a7dc86535b --- /dev/null +++ b/pac/atsamda1g/src/adc/inputctrl.rs @@ -0,0 +1,853 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + PIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + PIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + PIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + PIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + PIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + PIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + PIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + PIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + PIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + PIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + PIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + PIN11 = 11, + #[doc = "12: ADC AIN12 Pin"] + PIN12 = 12, + #[doc = "13: ADC AIN13 Pin"] + PIN13 = 13, + #[doc = "14: ADC AIN14 Pin"] + PIN14 = 14, + #[doc = "15: ADC AIN15 Pin"] + PIN15 = 15, + #[doc = "16: ADC AIN16 Pin"] + PIN16 = 16, + #[doc = "17: ADC AIN17 Pin"] + PIN17 = 17, + #[doc = "18: ADC AIN18 Pin"] + PIN18 = 18, + #[doc = "19: ADC AIN19 Pin"] + PIN19 = 19, + #[doc = "24: Temperature Reference"] + TEMP = 24, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "28: DAC Output"] + DAC = 28, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::PIN4), + 5 => Some(MUXPOS_A::PIN5), + 6 => Some(MUXPOS_A::PIN6), + 7 => Some(MUXPOS_A::PIN7), + 8 => Some(MUXPOS_A::PIN8), + 9 => Some(MUXPOS_A::PIN9), + 10 => Some(MUXPOS_A::PIN10), + 11 => Some(MUXPOS_A::PIN11), + 12 => Some(MUXPOS_A::PIN12), + 13 => Some(MUXPOS_A::PIN13), + 14 => Some(MUXPOS_A::PIN14), + 15 => Some(MUXPOS_A::PIN15), + 16 => Some(MUXPOS_A::PIN16), + 17 => Some(MUXPOS_A::PIN17), + 18 => Some(MUXPOS_A::PIN18), + 19 => Some(MUXPOS_A::PIN19), + 24 => Some(MUXPOS_A::TEMP), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + 28 => Some(MUXPOS_A::DAC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `PIN4`"] + #[inline(always)] + pub fn is_pin4(&self) -> bool { + **self == MUXPOS_A::PIN4 + } + #[doc = "Checks if the value of the field is `PIN5`"] + #[inline(always)] + pub fn is_pin5(&self) -> bool { + **self == MUXPOS_A::PIN5 + } + #[doc = "Checks if the value of the field is `PIN6`"] + #[inline(always)] + pub fn is_pin6(&self) -> bool { + **self == MUXPOS_A::PIN6 + } + #[doc = "Checks if the value of the field is `PIN7`"] + #[inline(always)] + pub fn is_pin7(&self) -> bool { + **self == MUXPOS_A::PIN7 + } + #[doc = "Checks if the value of the field is `PIN8`"] + #[inline(always)] + pub fn is_pin8(&self) -> bool { + **self == MUXPOS_A::PIN8 + } + #[doc = "Checks if the value of the field is `PIN9`"] + #[inline(always)] + pub fn is_pin9(&self) -> bool { + **self == MUXPOS_A::PIN9 + } + #[doc = "Checks if the value of the field is `PIN10`"] + #[inline(always)] + pub fn is_pin10(&self) -> bool { + **self == MUXPOS_A::PIN10 + } + #[doc = "Checks if the value of the field is `PIN11`"] + #[inline(always)] + pub fn is_pin11(&self) -> bool { + **self == MUXPOS_A::PIN11 + } + #[doc = "Checks if the value of the field is `PIN12`"] + #[inline(always)] + pub fn is_pin12(&self) -> bool { + **self == MUXPOS_A::PIN12 + } + #[doc = "Checks if the value of the field is `PIN13`"] + #[inline(always)] + pub fn is_pin13(&self) -> bool { + **self == MUXPOS_A::PIN13 + } + #[doc = "Checks if the value of the field is `PIN14`"] + #[inline(always)] + pub fn is_pin14(&self) -> bool { + **self == MUXPOS_A::PIN14 + } + #[doc = "Checks if the value of the field is `PIN15`"] + #[inline(always)] + pub fn is_pin15(&self) -> bool { + **self == MUXPOS_A::PIN15 + } + #[doc = "Checks if the value of the field is `PIN16`"] + #[inline(always)] + pub fn is_pin16(&self) -> bool { + **self == MUXPOS_A::PIN16 + } + #[doc = "Checks if the value of the field is `PIN17`"] + #[inline(always)] + pub fn is_pin17(&self) -> bool { + **self == MUXPOS_A::PIN17 + } + #[doc = "Checks if the value of the field is `PIN18`"] + #[inline(always)] + pub fn is_pin18(&self) -> bool { + **self == MUXPOS_A::PIN18 + } + #[doc = "Checks if the value of the field is `PIN19`"] + #[inline(always)] + pub fn is_pin19(&self) -> bool { + **self == MUXPOS_A::PIN19 + } + #[doc = "Checks if the value of the field is `TEMP`"] + #[inline(always)] + pub fn is_temp(&self) -> bool { + **self == MUXPOS_A::TEMP + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXPOS_A::DAC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn pin4(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn pin5(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn pin6(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn pin7(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn pin8(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn pin9(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn pin10(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn pin11(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN11) + } + #[doc = "ADC AIN12 Pin"] + #[inline(always)] + pub fn pin12(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN12) + } + #[doc = "ADC AIN13 Pin"] + #[inline(always)] + pub fn pin13(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN13) + } + #[doc = "ADC AIN14 Pin"] + #[inline(always)] + pub fn pin14(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN14) + } + #[doc = "ADC AIN15 Pin"] + #[inline(always)] + pub fn pin15(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN15) + } + #[doc = "ADC AIN16 Pin"] + #[inline(always)] + pub fn pin16(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN16) + } + #[doc = "ADC AIN17 Pin"] + #[inline(always)] + pub fn pin17(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN17) + } + #[doc = "ADC AIN18 Pin"] + #[inline(always)] + pub fn pin18(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN18) + } + #[doc = "ADC AIN19 Pin"] + #[inline(always)] + pub fn pin19(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN19) + } + #[doc = "Temperature Reference"] + #[inline(always)] + pub fn temp(self) -> &'a mut W { + self.variant(MUXPOS_A::TEMP) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = "DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXPOS_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + PIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + PIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + PIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + PIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + PIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + PIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + PIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + PIN7 = 7, + #[doc = "24: Internal Ground"] + GND = 24, + #[doc = "25: I/O Ground"] + IOGND = 25, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::PIN0), + 1 => Some(MUXNEG_A::PIN1), + 2 => Some(MUXNEG_A::PIN2), + 3 => Some(MUXNEG_A::PIN3), + 4 => Some(MUXNEG_A::PIN4), + 5 => Some(MUXNEG_A::PIN5), + 6 => Some(MUXNEG_A::PIN6), + 7 => Some(MUXNEG_A::PIN7), + 24 => Some(MUXNEG_A::GND), + 25 => Some(MUXNEG_A::IOGND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `PIN4`"] + #[inline(always)] + pub fn is_pin4(&self) -> bool { + **self == MUXNEG_A::PIN4 + } + #[doc = "Checks if the value of the field is `PIN5`"] + #[inline(always)] + pub fn is_pin5(&self) -> bool { + **self == MUXNEG_A::PIN5 + } + #[doc = "Checks if the value of the field is `PIN6`"] + #[inline(always)] + pub fn is_pin6(&self) -> bool { + **self == MUXNEG_A::PIN6 + } + #[doc = "Checks if the value of the field is `PIN7`"] + #[inline(always)] + pub fn is_pin7(&self) -> bool { + **self == MUXNEG_A::PIN7 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `IOGND`"] + #[inline(always)] + pub fn is_iognd(&self) -> bool { + **self == MUXNEG_A::IOGND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn pin4(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn pin5(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn pin6(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn pin7(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN7) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "I/O Ground"] + #[inline(always)] + pub fn iognd(self) -> &'a mut W { + self.variant(MUXNEG_A::IOGND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `INPUTSCAN` reader - Number of Input Channels Included in Scan"] +pub struct INPUTSCAN_R(crate::FieldReader); +impl INPUTSCAN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INPUTSCAN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTSCAN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTSCAN` writer - Number of Input Channels Included in Scan"] +pub struct INPUTSCAN_W<'a> { + w: &'a mut W, +} +impl<'a> INPUTSCAN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INPUTOFFSET` reader - Positive Mux Setting Offset"] +pub struct INPUTOFFSET_R(crate::FieldReader); +impl INPUTOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INPUTOFFSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTOFFSET` writer - Positive Mux Setting Offset"] +pub struct INPUTOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> INPUTOFFSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Gain Factor Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 1x"] + _1X = 0, + #[doc = "1: 2x"] + _2X = 1, + #[doc = "2: 4x"] + _4X = 2, + #[doc = "3: 8x"] + _8X = 3, + #[doc = "4: 16x"] + _16X = 4, + #[doc = "15: 1/2x"] + DIV2 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Gain Factor Selection"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::_1X), + 1 => Some(GAIN_A::_2X), + 2 => Some(GAIN_A::_4X), + 3 => Some(GAIN_A::_8X), + 4 => Some(GAIN_A::_16X), + 15 => Some(GAIN_A::DIV2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1X`"] + #[inline(always)] + pub fn is_1x(&self) -> bool { + **self == GAIN_A::_1X + } + #[doc = "Checks if the value of the field is `_2X`"] + #[inline(always)] + pub fn is_2x(&self) -> bool { + **self == GAIN_A::_2X + } + #[doc = "Checks if the value of the field is `_4X`"] + #[inline(always)] + pub fn is_4x(&self) -> bool { + **self == GAIN_A::_4X + } + #[doc = "Checks if the value of the field is `_8X`"] + #[inline(always)] + pub fn is_8x(&self) -> bool { + **self == GAIN_A::_8X + } + #[doc = "Checks if the value of the field is `_16X`"] + #[inline(always)] + pub fn is_16x(&self) -> bool { + **self == GAIN_A::_16X + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == GAIN_A::DIV2 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Gain Factor Selection"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1x"] + #[inline(always)] + pub fn _1x(self) -> &'a mut W { + self.variant(GAIN_A::_1X) + } + #[doc = "2x"] + #[inline(always)] + pub fn _2x(self) -> &'a mut W { + self.variant(GAIN_A::_2X) + } + #[doc = "4x"] + #[inline(always)] + pub fn _4x(self) -> &'a mut W { + self.variant(GAIN_A::_4X) + } + #[doc = "8x"] + #[inline(always)] + pub fn _8x(self) -> &'a mut W { + self.variant(GAIN_A::_8X) + } + #[doc = "16x"] + #[inline(always)] + pub fn _16x(self) -> &'a mut W { + self.variant(GAIN_A::_16X) + } + #[doc = "1/2x"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(GAIN_A::DIV2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] + #[inline(always)] + pub fn inputscan(&self) -> INPUTSCAN_R { + INPUTSCAN_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Positive Mux Setting Offset"] + #[inline(always)] + pub fn inputoffset(&self) -> INPUTOFFSET_R { + INPUTOFFSET_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Gain Factor Selection"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] + #[inline(always)] + pub fn inputscan(&mut self) -> INPUTSCAN_W { + INPUTSCAN_W { w: self } + } + #[doc = "Bits 20:23 - Positive Mux Setting Offset"] + #[inline(always)] + pub fn inputoffset(&mut self) -> INPUTOFFSET_W { + INPUTOFFSET_W { w: self } + } + #[doc = "Bits 24:27 - Gain Factor Selection"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/intenclr.rs b/pac/atsamda1g/src/adc/intenclr.rs new file mode 100644 index 00000000000..453afa12c61 --- /dev/null +++ b/pac/atsamda1g/src/adc/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/intenset.rs b/pac/atsamda1g/src/adc/intenset.rs new file mode 100644 index 00000000000..0d36429e544 --- /dev/null +++ b/pac/atsamda1g/src/adc/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/intflag.rs b/pac/atsamda1g/src/adc/intflag.rs new file mode 100644 index 00000000000..fec838269e9 --- /dev/null +++ b/pac/atsamda1g/src/adc/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/offsetcorr.rs b/pac/atsamda1g/src/adc/offsetcorr.rs new file mode 100644 index 00000000000..24a97427c64 --- /dev/null +++ b/pac/atsamda1g/src/adc/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/refctrl.rs b/pac/atsamda1g/src/adc/refctrl.rs new file mode 100644 index 00000000000..8053351459b --- /dev/null +++ b/pac/atsamda1g/src/adc/refctrl.rs @@ -0,0 +1,238 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: 1.0V voltage reference"] + INT1V = 0, + #[doc = "1: 1/1.48 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA (only for VDDANA > 2.0V)"] + INTVCC1 = 2, + #[doc = "3: External reference A"] + AREFA = 3, + #[doc = "4: External reference B"] + AREFB = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 4 => Some(REFSEL_A::AREFB), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + **self == REFSEL_A::AREFB + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.0V voltage reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "1/1.48 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA (only for VDDANA > 2.0V)"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External reference A"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "External reference B"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSEL_A::AREFB) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/result.rs b/pac/atsamda1g/src/adc/result.rs new file mode 100644 index 00000000000..f93bf58c6ba --- /dev/null +++ b/pac/atsamda1g/src/adc/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Conversion Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Conversion Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/sampctrl.rs b/pac/atsamda1g/src/adc/sampctrl.rs new file mode 100644 index 00000000000..b8cbc598b10 --- /dev/null +++ b/pac/atsamda1g/src/adc/sampctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sampling Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/status.rs b/pac/atsamda1g/src/adc/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1g/src/adc/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/swtrig.rs b/pac/atsamda1g/src/adc/swtrig.rs new file mode 100644 index 00000000000..111c0662dea --- /dev/null +++ b/pac/atsamda1g/src/adc/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Conversion Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Conversion Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - ADC Start Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - ADC Start Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Conversion Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ADC Start Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Conversion Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - ADC Start Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/winctrl.rs b/pac/atsamda1g/src/adc/winctrl.rs new file mode 100644 index 00000000000..6dd12786c7f --- /dev/null +++ b/pac/atsamda1g/src/adc/winctrl.rs @@ -0,0 +1,191 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: Mode 1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: Mode 2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: Mode 3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: Mode 4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "Mode 1: RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "Mode 2: RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "Mode 3: WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "Mode 4: !(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/winlt.rs b/pac/atsamda1g/src/adc/winlt.rs new file mode 100644 index 00000000000..2a339768476 --- /dev/null +++ b/pac/atsamda1g/src/adc/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/adc/winut.rs b/pac/atsamda1g/src/adc/winut.rs new file mode 100644 index 00000000000..0ea12317493 --- /dev/null +++ b/pac/atsamda1g/src/adc/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac.rs b/pac/atsamda1g/src/dac.rs new file mode 100644 index 00000000000..1816621e5db --- /dev/null +++ b/pac/atsamda1g/src/dac.rs @@ -0,0 +1,60 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Data"] + pub data: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x0c - Data Buffer"] + pub databuf: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DATABUF register accessor: an alias for `Reg`"] +pub type DATABUF = crate::Reg; +#[doc = "Data Buffer"] +pub mod databuf; diff --git a/pac/atsamda1g/src/dac/ctrla.rs b/pac/atsamda1g/src/dac/ctrla.rs new file mode 100644 index 00000000000..117922e5aae --- /dev/null +++ b/pac/atsamda1g/src/dac/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/ctrlb.rs b/pac/atsamda1g/src/dac/ctrlb.rs new file mode 100644 index 00000000000..1da837c6d4a --- /dev/null +++ b/pac/atsamda1g/src/dac/ctrlb.rs @@ -0,0 +1,400 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EOEN` reader - External Output Enable"] +pub struct EOEN_R(crate::FieldReader); +impl EOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EOEN` writer - External Output Enable"] +pub struct EOEN_W<'a> { + w: &'a mut W, +} +impl<'a> EOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `IOEN` reader - Internal Output Enable"] +pub struct IOEN_R(crate::FieldReader); +impl IOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOEN` writer - Internal Output Enable"] +pub struct IOEN_W<'a> { + w: &'a mut W, +} +impl<'a> IOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VPD` reader - Voltage Pump Disable"] +pub struct VPD_R(crate::FieldReader); +impl VPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VPD` writer - Voltage Pump Disable"] +pub struct VPD_W<'a> { + w: &'a mut W, +} +impl<'a> VPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BDWP` reader - Bypass DATABUF Write Protection"] +pub struct BDWP_R(crate::FieldReader); +impl BDWP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BDWP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BDWP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BDWP` writer - Bypass DATABUF Write Protection"] +pub struct BDWP_W<'a> { + w: &'a mut W, +} +impl<'a> BDWP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal 1.0V reference"] + INT1V = 0, + #[doc = "1: AVCC"] + AVCC = 1, + #[doc = "2: External reference"] + VREFP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::AVCC), + 2 => Some(REFSEL_A::VREFP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `AVCC`"] + #[inline(always)] + pub fn is_avcc(&self) -> bool { + **self == REFSEL_A::AVCC + } + #[doc = "Checks if the value of the field is `VREFP`"] + #[inline(always)] + pub fn is_vrefp(&self) -> bool { + **self == REFSEL_A::VREFP + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal 1.0V reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "AVCC"] + #[inline(always)] + pub fn avcc(self) -> &'a mut W { + self.variant(REFSEL_A::AVCC) + } + #[doc = "External reference"] + #[inline(always)] + pub fn vrefp(self) -> &'a mut W { + self.variant(REFSEL_A::VREFP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&self) -> EOEN_R { + EOEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&self) -> IOEN_R { + IOEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&self) -> VPD_R { + VPD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Bypass DATABUF Write Protection"] + #[inline(always)] + pub fn bdwp(&self) -> BDWP_R { + BDWP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&mut self) -> EOEN_W { + EOEN_W { w: self } + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&mut self) -> IOEN_W { + IOEN_W { w: self } + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&mut self) -> VPD_W { + VPD_W { w: self } + } + #[doc = "Bit 4 - Bypass DATABUF Write Protection"] + #[inline(always)] + pub fn bdwp(&mut self) -> BDWP_W { + BDWP_W { w: self } + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/data.rs b/pac/atsamda1g/src/dac/data.rs new file mode 100644 index 00000000000..4caca5e0a51 --- /dev/null +++ b/pac/atsamda1g/src/dac/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data value to be converted"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data value to be converted"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/databuf.rs b/pac/atsamda1g/src/dac/databuf.rs new file mode 100644 index 00000000000..1e945f893ff --- /dev/null +++ b/pac/atsamda1g/src/dac/databuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATABUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATABUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATABUF` reader - Data Buffer"] +pub struct DATABUF_R(crate::FieldReader); +impl DATABUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATABUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATABUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATABUF` writer - Data Buffer"] +pub struct DATABUF_W<'a> { + w: &'a mut W, +} +impl<'a> DATABUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&self) -> DATABUF_R { + DATABUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&mut self) -> DATABUF_W { + DATABUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databuf](index.html) module"] +pub struct DATABUF_SPEC; +impl crate::RegisterSpec for DATABUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [databuf::R](R) reader structure"] +impl crate::Readable for DATABUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [databuf::W](W) writer structure"] +impl crate::Writable for DATABUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATABUF to value 0"] +impl crate::Resettable for DATABUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/evctrl.rs b/pac/atsamda1g/src/dac/evctrl.rs new file mode 100644 index 00000000000..7d48fce2186 --- /dev/null +++ b/pac/atsamda1g/src/dac/evctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTYEO` reader - Data Buffer Empty Event Output"] +pub struct EMPTYEO_R(crate::FieldReader); +impl EMPTYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTYEO` writer - Data Buffer Empty Event Output"] +pub struct EMPTYEO_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&self) -> EMPTYEO_R { + EMPTYEO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&mut self) -> EMPTYEO_W { + EMPTYEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/intenclr.rs b/pac/atsamda1g/src/dac/intenclr.rs new file mode 100644 index 00000000000..5d97a2c4cd4 --- /dev/null +++ b/pac/atsamda1g/src/dac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/intenset.rs b/pac/atsamda1g/src/dac/intenset.rs new file mode 100644 index 00000000000..27b8e50d55a --- /dev/null +++ b/pac/atsamda1g/src/dac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/intflag.rs b/pac/atsamda1g/src/dac/intflag.rs new file mode 100644 index 00000000000..0df47b31e15 --- /dev/null +++ b/pac/atsamda1g/src/dac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dac/status.rs b/pac/atsamda1g/src/dac/status.rs new file mode 100644 index 00000000000..2667b356df2 --- /dev/null +++ b/pac/atsamda1g/src/dac/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy Status"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy Status"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac.rs b/pac/atsamda1g/src/dmac.rs new file mode 100644 index 00000000000..c23d3669755 --- /dev/null +++ b/pac/atsamda1g/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamda1g/src/dmac/active.rs b/pac/atsamda1g/src/dmac/active.rs new file mode 100644 index 00000000000..c3cc5a0420b --- /dev/null +++ b/pac/atsamda1g/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/baseaddr.rs b/pac/atsamda1g/src/dmac/baseaddr.rs new file mode 100644 index 00000000000..cec8c8cf077 --- /dev/null +++ b/pac/atsamda1g/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/busych.rs b/pac/atsamda1g/src/dmac/busych.rs new file mode 100644 index 00000000000..6f9419d5828 --- /dev/null +++ b/pac/atsamda1g/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/chctrla.rs b/pac/atsamda1g/src/dmac/chctrla.rs new file mode 100644 index 00000000000..49471b92938 --- /dev/null +++ b/pac/atsamda1g/src/dmac/chctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/chctrlb.rs b/pac/atsamda1g/src/dmac/chctrlb.rs new file mode 100644 index 00000000000..c52f6f8de35 --- /dev/null +++ b/pac/atsamda1g/src/dmac/chctrlb.rs @@ -0,0 +1,1331 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Peripheral Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: SERCOM0 RX Trigger"] + SERCOM0_RX = 1, + #[doc = "2: SERCOM0 TX Trigger"] + SERCOM0_TX = 2, + #[doc = "3: SERCOM1 RX Trigger"] + SERCOM1_RX = 3, + #[doc = "4: SERCOM1 TX Trigger"] + SERCOM1_TX = 4, + #[doc = "5: SERCOM2 RX Trigger"] + SERCOM2_RX = 5, + #[doc = "6: SERCOM2 TX Trigger"] + SERCOM2_TX = 6, + #[doc = "7: SERCOM3 RX Trigger"] + SERCOM3_RX = 7, + #[doc = "8: SERCOM3 TX Trigger"] + SERCOM3_TX = 8, + #[doc = "9: SERCOM4 RX Trigger"] + SERCOM4_RX = 9, + #[doc = "10: SERCOM4 TX Trigger"] + SERCOM4_TX = 10, + #[doc = "11: SERCOM5 RX Trigger"] + SERCOM5_RX = 11, + #[doc = "12: SERCOM5 TX Trigger"] + SERCOM5_TX = 12, + #[doc = "13: TCC0 Overflow Trigger"] + TCC0_OVF = 13, + #[doc = "14: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 14, + #[doc = "15: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 15, + #[doc = "16: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 16, + #[doc = "17: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 17, + #[doc = "18: TCC1 Overflow Trigger"] + TCC1_OVF = 18, + #[doc = "19: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 19, + #[doc = "20: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 20, + #[doc = "21: TCC2 Overflow Trigger"] + TCC2_OVF = 21, + #[doc = "22: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 22, + #[doc = "23: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 23, + #[doc = "24: TC3 Overflow Trigger"] + TC3_OVF = 24, + #[doc = "25: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 25, + #[doc = "26: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 26, + #[doc = "27: TC4 Overflow Trigger"] + TC4_OVF = 27, + #[doc = "28: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 28, + #[doc = "29: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 29, + #[doc = "30: TC5 Overflow Trigger"] + TC5_OVF = 30, + #[doc = "31: TC5 Match/Compare 0 Trigger"] + TC5_MC0 = 31, + #[doc = "32: TC5 Match/Compare 1 Trigger"] + TC5_MC1 = 32, + #[doc = "33: TC6 Overflow Trigger"] + TC6_OVF = 33, + #[doc = "34: TC6 Match/Compare 0 Trigger"] + TC6_MC0 = 34, + #[doc = "35: TC6 Match/Compare 1 Trigger"] + TC6_MC1 = 35, + #[doc = "36: TC7 Overflow Trigger"] + TC7_OVF = 36, + #[doc = "37: TC7 Match/Compare 0 Trigger"] + TC7_MC0 = 37, + #[doc = "38: TC7 Match/Compare 1 Trigger"] + TC7_MC1 = 38, + #[doc = "39: ADC Result Ready Trigger"] + ADC_RESRDY = 39, + #[doc = "40: DAC Empty Trigger"] + DAC_EMPTY = 40, + #[doc = "41: I2S RX 0 Trigger"] + I2S_RX_0 = 41, + #[doc = "42: I2S RX 1 Trigger"] + I2S_RX_1 = 42, + #[doc = "43: I2S TX 0 Trigger"] + I2S_TX_0 = 43, + #[doc = "44: I2S TX 1 Trigger"] + I2S_TX_1 = 44, + #[doc = "45: TCC3 Overflow Trigger"] + TCC3_OVF = 45, + #[doc = "46: TCC3 Match/Compare 0 Trigger"] + TCC3_MC0 = 46, + #[doc = "47: TCC3 Match/Compare 1 Trigger"] + TCC3_MC1 = 47, + #[doc = "48: Match/Compare 2 Trigger"] + TCC3_MC2 = 48, + #[doc = "49: Match/Compare 3 Trigger"] + TCC3_MC3 = 49, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Peripheral Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::SERCOM0_RX), + 2 => Some(TRIGSRC_A::SERCOM0_TX), + 3 => Some(TRIGSRC_A::SERCOM1_RX), + 4 => Some(TRIGSRC_A::SERCOM1_TX), + 5 => Some(TRIGSRC_A::SERCOM2_RX), + 6 => Some(TRIGSRC_A::SERCOM2_TX), + 7 => Some(TRIGSRC_A::SERCOM3_RX), + 8 => Some(TRIGSRC_A::SERCOM3_TX), + 9 => Some(TRIGSRC_A::SERCOM4_RX), + 10 => Some(TRIGSRC_A::SERCOM4_TX), + 11 => Some(TRIGSRC_A::SERCOM5_RX), + 12 => Some(TRIGSRC_A::SERCOM5_TX), + 13 => Some(TRIGSRC_A::TCC0_OVF), + 14 => Some(TRIGSRC_A::TCC0_MC0), + 15 => Some(TRIGSRC_A::TCC0_MC1), + 16 => Some(TRIGSRC_A::TCC0_MC2), + 17 => Some(TRIGSRC_A::TCC0_MC3), + 18 => Some(TRIGSRC_A::TCC1_OVF), + 19 => Some(TRIGSRC_A::TCC1_MC0), + 20 => Some(TRIGSRC_A::TCC1_MC1), + 21 => Some(TRIGSRC_A::TCC2_OVF), + 22 => Some(TRIGSRC_A::TCC2_MC0), + 23 => Some(TRIGSRC_A::TCC2_MC1), + 24 => Some(TRIGSRC_A::TC3_OVF), + 25 => Some(TRIGSRC_A::TC3_MC0), + 26 => Some(TRIGSRC_A::TC3_MC1), + 27 => Some(TRIGSRC_A::TC4_OVF), + 28 => Some(TRIGSRC_A::TC4_MC0), + 29 => Some(TRIGSRC_A::TC4_MC1), + 30 => Some(TRIGSRC_A::TC5_OVF), + 31 => Some(TRIGSRC_A::TC5_MC0), + 32 => Some(TRIGSRC_A::TC5_MC1), + 33 => Some(TRIGSRC_A::TC6_OVF), + 34 => Some(TRIGSRC_A::TC6_MC0), + 35 => Some(TRIGSRC_A::TC6_MC1), + 36 => Some(TRIGSRC_A::TC7_OVF), + 37 => Some(TRIGSRC_A::TC7_MC0), + 38 => Some(TRIGSRC_A::TC7_MC1), + 39 => Some(TRIGSRC_A::ADC_RESRDY), + 40 => Some(TRIGSRC_A::DAC_EMPTY), + 41 => Some(TRIGSRC_A::I2S_RX_0), + 42 => Some(TRIGSRC_A::I2S_RX_1), + 43 => Some(TRIGSRC_A::I2S_TX_0), + 44 => Some(TRIGSRC_A::I2S_TX_1), + 45 => Some(TRIGSRC_A::TCC3_OVF), + 46 => Some(TRIGSRC_A::TCC3_MC0), + 47 => Some(TRIGSRC_A::TCC3_MC1), + 48 => Some(TRIGSRC_A::TCC3_MC2), + 49 => Some(TRIGSRC_A::TCC3_MC3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `TC5_OVF`"] + #[inline(always)] + pub fn is_tc5_ovf(&self) -> bool { + **self == TRIGSRC_A::TC5_OVF + } + #[doc = "Checks if the value of the field is `TC5_MC0`"] + #[inline(always)] + pub fn is_tc5_mc0(&self) -> bool { + **self == TRIGSRC_A::TC5_MC0 + } + #[doc = "Checks if the value of the field is `TC5_MC1`"] + #[inline(always)] + pub fn is_tc5_mc1(&self) -> bool { + **self == TRIGSRC_A::TC5_MC1 + } + #[doc = "Checks if the value of the field is `TC6_OVF`"] + #[inline(always)] + pub fn is_tc6_ovf(&self) -> bool { + **self == TRIGSRC_A::TC6_OVF + } + #[doc = "Checks if the value of the field is `TC6_MC0`"] + #[inline(always)] + pub fn is_tc6_mc0(&self) -> bool { + **self == TRIGSRC_A::TC6_MC0 + } + #[doc = "Checks if the value of the field is `TC6_MC1`"] + #[inline(always)] + pub fn is_tc6_mc1(&self) -> bool { + **self == TRIGSRC_A::TC6_MC1 + } + #[doc = "Checks if the value of the field is `TC7_OVF`"] + #[inline(always)] + pub fn is_tc7_ovf(&self) -> bool { + **self == TRIGSRC_A::TC7_OVF + } + #[doc = "Checks if the value of the field is `TC7_MC0`"] + #[inline(always)] + pub fn is_tc7_mc0(&self) -> bool { + **self == TRIGSRC_A::TC7_MC0 + } + #[doc = "Checks if the value of the field is `TC7_MC1`"] + #[inline(always)] + pub fn is_tc7_mc1(&self) -> bool { + **self == TRIGSRC_A::TC7_MC1 + } + #[doc = "Checks if the value of the field is `ADC_RESRDY`"] + #[inline(always)] + pub fn is_adc_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `I2S_RX_0`"] + #[inline(always)] + pub fn is_i2s_rx_0(&self) -> bool { + **self == TRIGSRC_A::I2S_RX_0 + } + #[doc = "Checks if the value of the field is `I2S_RX_1`"] + #[inline(always)] + pub fn is_i2s_rx_1(&self) -> bool { + **self == TRIGSRC_A::I2S_RX_1 + } + #[doc = "Checks if the value of the field is `I2S_TX_0`"] + #[inline(always)] + pub fn is_i2s_tx_0(&self) -> bool { + **self == TRIGSRC_A::I2S_TX_0 + } + #[doc = "Checks if the value of the field is `I2S_TX_1`"] + #[inline(always)] + pub fn is_i2s_tx_1(&self) -> bool { + **self == TRIGSRC_A::I2S_TX_1 + } + #[doc = "Checks if the value of the field is `TCC3_OVF`"] + #[inline(always)] + pub fn is_tcc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC3_OVF + } + #[doc = "Checks if the value of the field is `TCC3_MC0`"] + #[inline(always)] + pub fn is_tcc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC0 + } + #[doc = "Checks if the value of the field is `TCC3_MC1`"] + #[inline(always)] + pub fn is_tcc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC1 + } + #[doc = "Checks if the value of the field is `TCC3_MC2`"] + #[inline(always)] + pub fn is_tcc3_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC2 + } + #[doc = "Checks if the value of the field is `TCC3_MC3`"] + #[inline(always)] + pub fn is_tcc3_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC3 + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Peripheral Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "TC5 Overflow Trigger"] + #[inline(always)] + pub fn tc5_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_OVF) + } + #[doc = "TC5 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc5_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC0) + } + #[doc = "TC5 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc5_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC1) + } + #[doc = "TC6 Overflow Trigger"] + #[inline(always)] + pub fn tc6_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_OVF) + } + #[doc = "TC6 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc6_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC0) + } + #[doc = "TC6 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc6_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC1) + } + #[doc = "TC7 Overflow Trigger"] + #[inline(always)] + pub fn tc7_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_OVF) + } + #[doc = "TC7 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc7_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC0) + } + #[doc = "TC7 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc7_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC1) + } + #[doc = "ADC Result Ready Trigger"] + #[inline(always)] + pub fn adc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "I2S RX 0 Trigger"] + #[inline(always)] + pub fn i2s_rx_0(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_RX_0) + } + #[doc = "I2S RX 1 Trigger"] + #[inline(always)] + pub fn i2s_rx_1(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_RX_1) + } + #[doc = "I2S TX 0 Trigger"] + #[inline(always)] + pub fn i2s_tx_0(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_TX_0) + } + #[doc = "I2S TX 1 Trigger"] + #[inline(always)] + pub fn i2s_tx_1(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_TX_1) + } + #[doc = "TCC3 Overflow Trigger"] + #[inline(always)] + pub fn tcc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_OVF) + } + #[doc = "TCC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC0) + } + #[doc = "TCC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC1) + } + #[doc = "Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc3_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC2) + } + #[doc = "Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc3_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Peripheral Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Peripheral Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/chid.rs b/pac/atsamda1g/src/dmac/chid.rs new file mode 100644 index 00000000000..19151d8e10b --- /dev/null +++ b/pac/atsamda1g/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/chintenclr.rs b/pac/atsamda1g/src/dmac/chintenclr.rs new file mode 100644 index 00000000000..e9e3e0d2e41 --- /dev/null +++ b/pac/atsamda1g/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/chintenset.rs b/pac/atsamda1g/src/dmac/chintenset.rs new file mode 100644 index 00000000000..473843d7f81 --- /dev/null +++ b/pac/atsamda1g/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/chintflag.rs b/pac/atsamda1g/src/dmac/chintflag.rs new file mode 100644 index 00000000000..dd8e72546c1 --- /dev/null +++ b/pac/atsamda1g/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/chstatus.rs b/pac/atsamda1g/src/dmac/chstatus.rs new file mode 100644 index 00000000000..f9432e61dab --- /dev/null +++ b/pac/atsamda1g/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/crcchksum.rs b/pac/atsamda1g/src/dmac/crcchksum.rs new file mode 100644 index 00000000000..89eb5b38a09 --- /dev/null +++ b/pac/atsamda1g/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/crcctrl.rs b/pac/atsamda1g/src/dmac/crcctrl.rs new file mode 100644 index 00000000000..a1d022dd9e6 --- /dev/null +++ b/pac/atsamda1g/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: Byte bus access"] + BYTE = 0, + #[doc = "1: Half-word bus access"] + HWORD = 1, + #[doc = "2: Word bus access"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Byte bus access"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "Half-word bus access"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "Word bus access"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/crcdatain.rs b/pac/atsamda1g/src/dmac/crcdatain.rs new file mode 100644 index 00000000000..ca0879a1213 --- /dev/null +++ b/pac/atsamda1g/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/crcstatus.rs b/pac/atsamda1g/src/dmac/crcstatus.rs new file mode 100644 index 00000000000..a132e9d5cd0 --- /dev/null +++ b/pac/atsamda1g/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/ctrl.rs b/pac/atsamda1g/src/dmac/ctrl.rs new file mode 100644 index 00000000000..fabae9d82a6 --- /dev/null +++ b/pac/atsamda1g/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/dbgctrl.rs b/pac/atsamda1g/src/dmac/dbgctrl.rs new file mode 100644 index 00000000000..53636eb2b33 --- /dev/null +++ b/pac/atsamda1g/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/intpend.rs b/pac/atsamda1g/src/dmac/intpend.rs new file mode 100644 index 00000000000..a107c4c32e6 --- /dev/null +++ b/pac/atsamda1g/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/intstatus.rs b/pac/atsamda1g/src/dmac/intstatus.rs new file mode 100644 index 00000000000..74a836f4a2f --- /dev/null +++ b/pac/atsamda1g/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/pendch.rs b/pac/atsamda1g/src/dmac/pendch.rs new file mode 100644 index 00000000000..8bb68ff8fa5 --- /dev/null +++ b/pac/atsamda1g/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/prictrl0.rs b/pac/atsamda1g/src/dmac/prictrl0.rs new file mode 100644 index 00000000000..ad795d0ba68 --- /dev/null +++ b/pac/atsamda1g/src/dmac/prictrl0.rs @@ -0,0 +1,402 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/qosctrl.rs b/pac/atsamda1g/src/dmac/qosctrl.rs new file mode 100644 index 00000000000..2f8906f0614 --- /dev/null +++ b/pac/atsamda1g/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x15"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x15 + } +} diff --git a/pac/atsamda1g/src/dmac/swtrigctrl.rs b/pac/atsamda1g/src/dmac/swtrigctrl.rs new file mode 100644 index 00000000000..8590fef852d --- /dev/null +++ b/pac/atsamda1g/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dmac/wrbaddr.rs b/pac/atsamda1g/src/dmac/wrbaddr.rs new file mode 100644 index 00000000000..ccf2a376b85 --- /dev/null +++ b/pac/atsamda1g/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu.rs b/pac/atsamda1g/src/dsu.rs new file mode 100644 index 00000000000..499c49a0262 --- /dev/null +++ b/pac/atsamda1g/src/dsu.rs @@ -0,0 +1,134 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved8: [u8; 0x0fe4], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved11: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + _reserved13: [u8; 0x0c], + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamda1g/src/dsu/addr.rs b/pac/atsamda1g/src/dsu/addr.rs new file mode 100644 index 00000000000..1e0a7ad719c --- /dev/null +++ b/pac/atsamda1g/src/dsu/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/cid0.rs b/pac/atsamda1g/src/dsu/cid0.rs new file mode 100644 index 00000000000..b3c2373dfc9 --- /dev/null +++ b/pac/atsamda1g/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamda1g/src/dsu/cid1.rs b/pac/atsamda1g/src/dsu/cid1.rs new file mode 100644 index 00000000000..3628ceac64a --- /dev/null +++ b/pac/atsamda1g/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1g/src/dsu/cid2.rs b/pac/atsamda1g/src/dsu/cid2.rs new file mode 100644 index 00000000000..714078d5c43 --- /dev/null +++ b/pac/atsamda1g/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1g/src/dsu/cid3.rs b/pac/atsamda1g/src/dsu/cid3.rs new file mode 100644 index 00000000000..a345af7b516 --- /dev/null +++ b/pac/atsamda1g/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamda1g/src/dsu/ctrl.rs b/pac/atsamda1g/src/dsu/ctrl.rs new file mode 100644 index 00000000000..ab4b0cd332d --- /dev/null +++ b/pac/atsamda1g/src/dsu/ctrl.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Check"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory Built-In Self-Test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Check"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory Built-In Self-Test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/data.rs b/pac/atsamda1g/src/dsu/data.rs new file mode 100644 index 00000000000..193cc49a07f --- /dev/null +++ b/pac/atsamda1g/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/dcc.rs b/pac/atsamda1g/src/dsu/dcc.rs new file mode 100644 index 00000000000..354323a499e --- /dev/null +++ b/pac/atsamda1g/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/did.rs b/pac/atsamda1g/src/dsu/did.rs new file mode 100644 index 00000000000..52c8fab7990 --- /dev/null +++ b/pac/atsamda1g/src/dsu/did.rs @@ -0,0 +1,153 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Identification"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERIES` reader - Product Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAMILY` reader - Product Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Identification"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Product Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Product Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1001_1567"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1001_1567 + } +} diff --git a/pac/atsamda1g/src/dsu/end.rs b/pac/atsamda1g/src/dsu/end.rs new file mode 100644 index 00000000000..cce2edea2bc --- /dev/null +++ b/pac/atsamda1g/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/entry0.rs b/pac/atsamda1g/src/dsu/entry0.rs new file mode 100644 index 00000000000..d8563990e82 --- /dev/null +++ b/pac/atsamda1g/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamda1g/src/dsu/entry1.rs b/pac/atsamda1g/src/dsu/entry1.rs new file mode 100644 index 00000000000..8a5358aaa93 --- /dev/null +++ b/pac/atsamda1g/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x3002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3002 + } +} diff --git a/pac/atsamda1g/src/dsu/length.rs b/pac/atsamda1g/src/dsu/length.rs new file mode 100644 index 00000000000..2dc771f74df --- /dev/null +++ b/pac/atsamda1g/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/memtype.rs b/pac/atsamda1g/src/dsu/memtype.rs new file mode 100644 index 00000000000..3cc841e2ba7 --- /dev/null +++ b/pac/atsamda1g/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/pid0.rs b/pac/atsamda1g/src/dsu/pid0.rs new file mode 100644 index 00000000000..98028ea6283 --- /dev/null +++ b/pac/atsamda1g/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamda1g/src/dsu/pid1.rs b/pac/atsamda1g/src/dsu/pid1.rs new file mode 100644 index 00000000000..4f94b853507 --- /dev/null +++ b/pac/atsamda1g/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamda1g/src/dsu/pid2.rs b/pac/atsamda1g/src/dsu/pid2.rs new file mode 100644 index 00000000000..d8f8ed10192 --- /dev/null +++ b/pac/atsamda1g/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamda1g/src/dsu/pid3.rs b/pac/atsamda1g/src/dsu/pid3.rs new file mode 100644 index 00000000000..c0a8fb2d7f9 --- /dev/null +++ b/pac/atsamda1g/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/pid4.rs b/pac/atsamda1g/src/dsu/pid4.rs new file mode 100644 index 00000000000..d239852ee8f --- /dev/null +++ b/pac/atsamda1g/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB Count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB Count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/statusa.rs b/pac/atsamda1g/src/dsu/statusa.rs new file mode 100644 index 00000000000..c7b90a13e49 --- /dev/null +++ b/pac/atsamda1g/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/dsu/statusb.rs b/pac/atsamda1g/src/dsu/statusb.rs new file mode 100644 index 00000000000..3dc6ea897d3 --- /dev/null +++ b/pac/atsamda1g/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x10"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1g/src/eic.rs b/pac/atsamda1g/src/eic.rs new file mode 100644 index 00000000000..dcfa8655a9f --- /dev/null +++ b/pac/atsamda1g/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status"] + pub status: crate::Reg, + #[doc = "0x02 - Non-Maskable Interrupt Control"] + pub nmictrl: crate::Reg, + #[doc = "0x03 - Non-Maskable Interrupt Flag Status and Clear"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0c - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x10 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x14 - Wake-Up Enable"] + pub wakeup: crate::Reg, + #[doc = "0x18..0x20 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "Non-Maskable Interrupt Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "Non-Maskable Interrupt Flag Status and Clear"] +pub mod nmiflag; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "WAKEUP register accessor: an alias for `Reg`"] +pub type WAKEUP = crate::Reg; +#[doc = "Wake-Up Enable"] +pub mod wakeup; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamda1g/src/eic/config.rs b/pac/atsamda1g/src/eic/config.rs new file mode 100644 index 00000000000..5223e0514d5 --- /dev/null +++ b/pac/atsamda1g/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense 0 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense 0 Configuration"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense 0 Configuration"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter 0 Enable"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter 0 Enable"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense 1 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense 1 Configuration"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense 1 Configuration"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter 1 Enable"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter 1 Enable"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense 2 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense 2 Configuration"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense 2 Configuration"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter 2 Enable"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter 2 Enable"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense 3 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense 3 Configuration"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense 3 Configuration"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter 3 Enable"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter 3 Enable"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense 4 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense 4 Configuration"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense 4 Configuration"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter 4 Enable"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter 4 Enable"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense 5 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense 5 Configuration"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense 5 Configuration"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter 5 Enable"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter 5 Enable"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense 6 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense 6 Configuration"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense 6 Configuration"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter 6 Enable"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter 6 Enable"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense 7 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense 7 Configuration"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense 7 Configuration"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter 7 Enable"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter 7 Enable"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense 0 Configuration"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter 0 Enable"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense 1 Configuration"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter 1 Enable"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense 2 Configuration"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter 2 Enable"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense 3 Configuration"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter 3 Enable"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense 4 Configuration"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter 4 Enable"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense 5 Configuration"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter 5 Enable"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense 6 Configuration"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter 6 Enable"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense 7 Configuration"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter 7 Enable"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense 0 Configuration"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter 0 Enable"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense 1 Configuration"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter 1 Enable"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense 2 Configuration"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter 2 Enable"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense 3 Configuration"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter 3 Enable"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense 4 Configuration"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter 4 Enable"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense 5 Configuration"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter 5 Enable"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense 6 Configuration"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter 6 Enable"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense 7 Configuration"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter 7 Enable"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/ctrl.rs b/pac/atsamda1g/src/eic/ctrl.rs new file mode 100644 index 00000000000..3d5f7d86a1f --- /dev/null +++ b/pac/atsamda1g/src/eic/ctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/evctrl.rs b/pac/atsamda1g/src/eic/evctrl.rs new file mode 100644 index 00000000000..660952cdc88 --- /dev/null +++ b/pac/atsamda1g/src/eic/evctrl.rs @@ -0,0 +1,818 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO0` reader - External Interrupt 0 Event Output Enable"] +pub struct EXTINTEO0_R(crate::FieldReader); +impl EXTINTEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO0` writer - External Interrupt 0 Event Output Enable"] +pub struct EXTINTEO0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINTEO1` reader - External Interrupt 1 Event Output Enable"] +pub struct EXTINTEO1_R(crate::FieldReader); +impl EXTINTEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO1` writer - External Interrupt 1 Event Output Enable"] +pub struct EXTINTEO1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINTEO2` reader - External Interrupt 2 Event Output Enable"] +pub struct EXTINTEO2_R(crate::FieldReader); +impl EXTINTEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO2` writer - External Interrupt 2 Event Output Enable"] +pub struct EXTINTEO2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINTEO3` reader - External Interrupt 3 Event Output Enable"] +pub struct EXTINTEO3_R(crate::FieldReader); +impl EXTINTEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO3` writer - External Interrupt 3 Event Output Enable"] +pub struct EXTINTEO3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINTEO4` reader - External Interrupt 4 Event Output Enable"] +pub struct EXTINTEO4_R(crate::FieldReader); +impl EXTINTEO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO4` writer - External Interrupt 4 Event Output Enable"] +pub struct EXTINTEO4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINTEO5` reader - External Interrupt 5 Event Output Enable"] +pub struct EXTINTEO5_R(crate::FieldReader); +impl EXTINTEO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO5` writer - External Interrupt 5 Event Output Enable"] +pub struct EXTINTEO5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINTEO6` reader - External Interrupt 6 Event Output Enable"] +pub struct EXTINTEO6_R(crate::FieldReader); +impl EXTINTEO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO6` writer - External Interrupt 6 Event Output Enable"] +pub struct EXTINTEO6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINTEO7` reader - External Interrupt 7 Event Output Enable"] +pub struct EXTINTEO7_R(crate::FieldReader); +impl EXTINTEO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO7` writer - External Interrupt 7 Event Output Enable"] +pub struct EXTINTEO7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINTEO8` reader - External Interrupt 8 Event Output Enable"] +pub struct EXTINTEO8_R(crate::FieldReader); +impl EXTINTEO8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO8` writer - External Interrupt 8 Event Output Enable"] +pub struct EXTINTEO8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINTEO9` reader - External Interrupt 9 Event Output Enable"] +pub struct EXTINTEO9_R(crate::FieldReader); +impl EXTINTEO9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO9` writer - External Interrupt 9 Event Output Enable"] +pub struct EXTINTEO9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINTEO10` reader - External Interrupt 10 Event Output Enable"] +pub struct EXTINTEO10_R(crate::FieldReader); +impl EXTINTEO10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO10` writer - External Interrupt 10 Event Output Enable"] +pub struct EXTINTEO10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINTEO11` reader - External Interrupt 11 Event Output Enable"] +pub struct EXTINTEO11_R(crate::FieldReader); +impl EXTINTEO11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO11` writer - External Interrupt 11 Event Output Enable"] +pub struct EXTINTEO11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINTEO12` reader - External Interrupt 12 Event Output Enable"] +pub struct EXTINTEO12_R(crate::FieldReader); +impl EXTINTEO12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO12` writer - External Interrupt 12 Event Output Enable"] +pub struct EXTINTEO12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINTEO13` reader - External Interrupt 13 Event Output Enable"] +pub struct EXTINTEO13_R(crate::FieldReader); +impl EXTINTEO13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO13` writer - External Interrupt 13 Event Output Enable"] +pub struct EXTINTEO13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINTEO14` reader - External Interrupt 14 Event Output Enable"] +pub struct EXTINTEO14_R(crate::FieldReader); +impl EXTINTEO14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO14` writer - External Interrupt 14 Event Output Enable"] +pub struct EXTINTEO14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINTEO15` reader - External Interrupt 15 Event Output Enable"] +pub struct EXTINTEO15_R(crate::FieldReader); +impl EXTINTEO15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO15` writer - External Interrupt 15 Event Output Enable"] +pub struct EXTINTEO15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] + #[inline(always)] + pub fn extinteo0(&self) -> EXTINTEO0_R { + EXTINTEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] + #[inline(always)] + pub fn extinteo1(&self) -> EXTINTEO1_R { + EXTINTEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] + #[inline(always)] + pub fn extinteo2(&self) -> EXTINTEO2_R { + EXTINTEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] + #[inline(always)] + pub fn extinteo3(&self) -> EXTINTEO3_R { + EXTINTEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] + #[inline(always)] + pub fn extinteo4(&self) -> EXTINTEO4_R { + EXTINTEO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] + #[inline(always)] + pub fn extinteo5(&self) -> EXTINTEO5_R { + EXTINTEO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] + #[inline(always)] + pub fn extinteo6(&self) -> EXTINTEO6_R { + EXTINTEO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] + #[inline(always)] + pub fn extinteo7(&self) -> EXTINTEO7_R { + EXTINTEO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] + #[inline(always)] + pub fn extinteo8(&self) -> EXTINTEO8_R { + EXTINTEO8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] + #[inline(always)] + pub fn extinteo9(&self) -> EXTINTEO9_R { + EXTINTEO9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] + #[inline(always)] + pub fn extinteo10(&self) -> EXTINTEO10_R { + EXTINTEO10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] + #[inline(always)] + pub fn extinteo11(&self) -> EXTINTEO11_R { + EXTINTEO11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] + #[inline(always)] + pub fn extinteo12(&self) -> EXTINTEO12_R { + EXTINTEO12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] + #[inline(always)] + pub fn extinteo13(&self) -> EXTINTEO13_R { + EXTINTEO13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] + #[inline(always)] + pub fn extinteo14(&self) -> EXTINTEO14_R { + EXTINTEO14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] + #[inline(always)] + pub fn extinteo15(&self) -> EXTINTEO15_R { + EXTINTEO15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] + #[inline(always)] + pub fn extinteo0(&mut self) -> EXTINTEO0_W { + EXTINTEO0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] + #[inline(always)] + pub fn extinteo1(&mut self) -> EXTINTEO1_W { + EXTINTEO1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] + #[inline(always)] + pub fn extinteo2(&mut self) -> EXTINTEO2_W { + EXTINTEO2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] + #[inline(always)] + pub fn extinteo3(&mut self) -> EXTINTEO3_W { + EXTINTEO3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] + #[inline(always)] + pub fn extinteo4(&mut self) -> EXTINTEO4_W { + EXTINTEO4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] + #[inline(always)] + pub fn extinteo5(&mut self) -> EXTINTEO5_W { + EXTINTEO5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] + #[inline(always)] + pub fn extinteo6(&mut self) -> EXTINTEO6_W { + EXTINTEO6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] + #[inline(always)] + pub fn extinteo7(&mut self) -> EXTINTEO7_W { + EXTINTEO7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] + #[inline(always)] + pub fn extinteo8(&mut self) -> EXTINTEO8_W { + EXTINTEO8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] + #[inline(always)] + pub fn extinteo9(&mut self) -> EXTINTEO9_W { + EXTINTEO9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] + #[inline(always)] + pub fn extinteo10(&mut self) -> EXTINTEO10_W { + EXTINTEO10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] + #[inline(always)] + pub fn extinteo11(&mut self) -> EXTINTEO11_W { + EXTINTEO11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] + #[inline(always)] + pub fn extinteo12(&mut self) -> EXTINTEO12_W { + EXTINTEO12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] + #[inline(always)] + pub fn extinteo13(&mut self) -> EXTINTEO13_W { + EXTINTEO13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] + #[inline(always)] + pub fn extinteo14(&mut self) -> EXTINTEO14_W { + EXTINTEO14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] + #[inline(always)] + pub fn extinteo15(&mut self) -> EXTINTEO15_W { + EXTINTEO15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/intenclr.rs b/pac/atsamda1g/src/eic/intenclr.rs new file mode 100644 index 00000000000..e8e877b5ed3 --- /dev/null +++ b/pac/atsamda1g/src/eic/intenclr.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0 Enable"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0 Enable"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1 Enable"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1 Enable"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2 Enable"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2 Enable"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3 Enable"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3 Enable"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4 Enable"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4 Enable"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5 Enable"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5 Enable"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6 Enable"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6 Enable"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7 Enable"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7 Enable"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8 Enable"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8 Enable"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9 Enable"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9 Enable"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10 Enable"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10 Enable"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11 Enable"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11 Enable"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12 Enable"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12 Enable"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13 Enable"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13 Enable"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14 Enable"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14 Enable"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15 Enable"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15 Enable"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/intenset.rs b/pac/atsamda1g/src/eic/intenset.rs new file mode 100644 index 00000000000..2ff10d0def2 --- /dev/null +++ b/pac/atsamda1g/src/eic/intenset.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0 Enable"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0 Enable"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1 Enable"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1 Enable"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2 Enable"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2 Enable"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3 Enable"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3 Enable"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4 Enable"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4 Enable"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5 Enable"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5 Enable"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6 Enable"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6 Enable"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7 Enable"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7 Enable"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8 Enable"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8 Enable"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9 Enable"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9 Enable"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10 Enable"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10 Enable"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11 Enable"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11 Enable"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12 Enable"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12 Enable"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13 Enable"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13 Enable"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14 Enable"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14 Enable"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15 Enable"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15 Enable"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/intflag.rs b/pac/atsamda1g/src/eic/intflag.rs new file mode 100644 index 00000000000..057d3868ffd --- /dev/null +++ b/pac/atsamda1g/src/eic/intflag.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/nmictrl.rs b/pac/atsamda1g/src/eic/nmictrl.rs new file mode 100644 index 00000000000..9abdb233a86 --- /dev/null +++ b/pac/atsamda1g/src/eic/nmictrl.rs @@ -0,0 +1,251 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Non-Maskable Interrupt Sense\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - Non-Maskable Interrupt Sense"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - Non-Maskable Interrupt Sense"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/nmiflag.rs b/pac/atsamda1g/src/eic/nmiflag.rs new file mode 100644 index 00000000000..b2e0be1761d --- /dev/null +++ b/pac/atsamda1g/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - Non-Maskable Interrupt"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - Non-Maskable Interrupt"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/status.rs b/pac/atsamda1g/src/eic/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1g/src/eic/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/eic/wakeup.rs b/pac/atsamda1g/src/eic/wakeup.rs new file mode 100644 index 00000000000..2c5d046923a --- /dev/null +++ b/pac/atsamda1g/src/eic/wakeup.rs @@ -0,0 +1,818 @@ +#[doc = "Register `WAKEUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAKEUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WAKEUPEN0` reader - External Interrupt 0 Wake-up Enable"] +pub struct WAKEUPEN0_R(crate::FieldReader); +impl WAKEUPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN0` writer - External Interrupt 0 Wake-up Enable"] +pub struct WAKEUPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `WAKEUPEN1` reader - External Interrupt 1 Wake-up Enable"] +pub struct WAKEUPEN1_R(crate::FieldReader); +impl WAKEUPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN1` writer - External Interrupt 1 Wake-up Enable"] +pub struct WAKEUPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAKEUPEN2` reader - External Interrupt 2 Wake-up Enable"] +pub struct WAKEUPEN2_R(crate::FieldReader); +impl WAKEUPEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN2` writer - External Interrupt 2 Wake-up Enable"] +pub struct WAKEUPEN2_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WAKEUPEN3` reader - External Interrupt 3 Wake-up Enable"] +pub struct WAKEUPEN3_R(crate::FieldReader); +impl WAKEUPEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN3` writer - External Interrupt 3 Wake-up Enable"] +pub struct WAKEUPEN3_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUPEN4` reader - External Interrupt 4 Wake-up Enable"] +pub struct WAKEUPEN4_R(crate::FieldReader); +impl WAKEUPEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN4` writer - External Interrupt 4 Wake-up Enable"] +pub struct WAKEUPEN4_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WAKEUPEN5` reader - External Interrupt 5 Wake-up Enable"] +pub struct WAKEUPEN5_R(crate::FieldReader); +impl WAKEUPEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN5` writer - External Interrupt 5 Wake-up Enable"] +pub struct WAKEUPEN5_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `WAKEUPEN6` reader - External Interrupt 6 Wake-up Enable"] +pub struct WAKEUPEN6_R(crate::FieldReader); +impl WAKEUPEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN6` writer - External Interrupt 6 Wake-up Enable"] +pub struct WAKEUPEN6_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WAKEUPEN7` reader - External Interrupt 7 Wake-up Enable"] +pub struct WAKEUPEN7_R(crate::FieldReader); +impl WAKEUPEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN7` writer - External Interrupt 7 Wake-up Enable"] +pub struct WAKEUPEN7_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WAKEUPEN8` reader - External Interrupt 8 Wake-up Enable"] +pub struct WAKEUPEN8_R(crate::FieldReader); +impl WAKEUPEN8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN8` writer - External Interrupt 8 Wake-up Enable"] +pub struct WAKEUPEN8_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `WAKEUPEN9` reader - External Interrupt 9 Wake-up Enable"] +pub struct WAKEUPEN9_R(crate::FieldReader); +impl WAKEUPEN9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN9` writer - External Interrupt 9 Wake-up Enable"] +pub struct WAKEUPEN9_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `WAKEUPEN10` reader - External Interrupt 10 Wake-up Enable"] +pub struct WAKEUPEN10_R(crate::FieldReader); +impl WAKEUPEN10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN10` writer - External Interrupt 10 Wake-up Enable"] +pub struct WAKEUPEN10_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `WAKEUPEN11` reader - External Interrupt 11 Wake-up Enable"] +pub struct WAKEUPEN11_R(crate::FieldReader); +impl WAKEUPEN11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN11` writer - External Interrupt 11 Wake-up Enable"] +pub struct WAKEUPEN11_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `WAKEUPEN12` reader - External Interrupt 12 Wake-up Enable"] +pub struct WAKEUPEN12_R(crate::FieldReader); +impl WAKEUPEN12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN12` writer - External Interrupt 12 Wake-up Enable"] +pub struct WAKEUPEN12_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `WAKEUPEN13` reader - External Interrupt 13 Wake-up Enable"] +pub struct WAKEUPEN13_R(crate::FieldReader); +impl WAKEUPEN13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN13` writer - External Interrupt 13 Wake-up Enable"] +pub struct WAKEUPEN13_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `WAKEUPEN14` reader - External Interrupt 14 Wake-up Enable"] +pub struct WAKEUPEN14_R(crate::FieldReader); +impl WAKEUPEN14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN14` writer - External Interrupt 14 Wake-up Enable"] +pub struct WAKEUPEN14_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `WAKEUPEN15` reader - External Interrupt 15 Wake-up Enable"] +pub struct WAKEUPEN15_R(crate::FieldReader); +impl WAKEUPEN15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN15` writer - External Interrupt 15 Wake-up Enable"] +pub struct WAKEUPEN15_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen0(&self) -> WAKEUPEN0_R { + WAKEUPEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen1(&self) -> WAKEUPEN1_R { + WAKEUPEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen2(&self) -> WAKEUPEN2_R { + WAKEUPEN2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen3(&self) -> WAKEUPEN3_R { + WAKEUPEN3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen4(&self) -> WAKEUPEN4_R { + WAKEUPEN4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen5(&self) -> WAKEUPEN5_R { + WAKEUPEN5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen6(&self) -> WAKEUPEN6_R { + WAKEUPEN6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen7(&self) -> WAKEUPEN7_R { + WAKEUPEN7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen8(&self) -> WAKEUPEN8_R { + WAKEUPEN8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen9(&self) -> WAKEUPEN9_R { + WAKEUPEN9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen10(&self) -> WAKEUPEN10_R { + WAKEUPEN10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen11(&self) -> WAKEUPEN11_R { + WAKEUPEN11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen12(&self) -> WAKEUPEN12_R { + WAKEUPEN12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen13(&self) -> WAKEUPEN13_R { + WAKEUPEN13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen14(&self) -> WAKEUPEN14_R { + WAKEUPEN14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen15(&self) -> WAKEUPEN15_R { + WAKEUPEN15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen0(&mut self) -> WAKEUPEN0_W { + WAKEUPEN0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen1(&mut self) -> WAKEUPEN1_W { + WAKEUPEN1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen2(&mut self) -> WAKEUPEN2_W { + WAKEUPEN2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen3(&mut self) -> WAKEUPEN3_W { + WAKEUPEN3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen4(&mut self) -> WAKEUPEN4_W { + WAKEUPEN4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen5(&mut self) -> WAKEUPEN5_W { + WAKEUPEN5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen6(&mut self) -> WAKEUPEN6_W { + WAKEUPEN6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen7(&mut self) -> WAKEUPEN7_W { + WAKEUPEN7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen8(&mut self) -> WAKEUPEN8_W { + WAKEUPEN8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen9(&mut self) -> WAKEUPEN9_W { + WAKEUPEN9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen10(&mut self) -> WAKEUPEN10_W { + WAKEUPEN10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen11(&mut self) -> WAKEUPEN11_W { + WAKEUPEN11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen12(&mut self) -> WAKEUPEN12_W { + WAKEUPEN12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen13(&mut self) -> WAKEUPEN13_W { + WAKEUPEN13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen14(&mut self) -> WAKEUPEN14_W { + WAKEUPEN14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen15(&mut self) -> WAKEUPEN15_W { + WAKEUPEN15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Wake-Up Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wakeup](index.html) module"] +pub struct WAKEUP_SPEC; +impl crate::RegisterSpec for WAKEUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wakeup::R](R) reader structure"] +impl crate::Readable for WAKEUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wakeup::W](W) writer structure"] +impl crate::Writable for WAKEUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAKEUP to value 0"] +impl crate::Resettable for WAKEUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/evsys.rs b/pac/atsamda1g/src/evsys.rs new file mode 100644 index 00000000000..73f42bb8158 --- /dev/null +++ b/pac/atsamda1g/src/evsys.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Channel"] + pub channel: crate::Reg, + #[doc = "0x08 - User Multiplexer"] + pub user: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer"] +pub mod user; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; diff --git a/pac/atsamda1g/src/evsys/channel.rs b/pac/atsamda1g/src/evsys/channel.rs new file mode 100644 index 00000000000..e17ac9fdf25 --- /dev/null +++ b/pac/atsamda1g/src/evsys/channel.rs @@ -0,0 +1,398 @@ +#[doc = "Register `CHANNEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `SWEVT` reader - Software Event"] +pub struct SWEVT_R(crate::FieldReader); +impl SWEVT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWEVT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWEVT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWEVT` writer - Software Event"] +pub struct SWEVT_W<'a> { + w: &'a mut W, +} +impl<'a> SWEVT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 26)) | ((value as u32 & 0x03) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Software Event"] + #[inline(always)] + pub fn swevt(&self) -> SWEVT_R { + SWEVT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:25 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 26:27 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 26) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Bit 8 - Software Event"] + #[inline(always)] + pub fn swevt(&mut self) -> SWEVT_W { + SWEVT_W { w: self } + } + #[doc = "Bits 16:22 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 24:25 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 26:27 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL to value 0"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/evsys/chstatus.rs b/pac/atsamda1g/src/evsys/chstatus.rs new file mode 100644 index 00000000000..9f5bba4c55c --- /dev/null +++ b/pac/atsamda1g/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0x000f_00ff"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x000f_00ff + } +} diff --git a/pac/atsamda1g/src/evsys/ctrl.rs b/pac/atsamda1g/src/evsys/ctrl.rs new file mode 100644 index 00000000000..0c1cacd5ec1 --- /dev/null +++ b/pac/atsamda1g/src/evsys/ctrl.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `GCLKREQ` writer - Generic Clock Requests"] +pub struct GCLKREQ_W<'a> { + w: &'a mut W, +} +impl<'a> GCLKREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 4 - Generic Clock Requests"] + #[inline(always)] + pub fn gclkreq(&mut self) -> GCLKREQ_W { + GCLKREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/evsys/intenclr.rs b/pac/atsamda1g/src/evsys/intenclr.rs new file mode 100644 index 00000000000..bb007d3cdd4 --- /dev/null +++ b/pac/atsamda1g/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/evsys/intenset.rs b/pac/atsamda1g/src/evsys/intenset.rs new file mode 100644 index 00000000000..a2c0b908380 --- /dev/null +++ b/pac/atsamda1g/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/evsys/intflag.rs b/pac/atsamda1g/src/evsys/intflag.rs new file mode 100644 index 00000000000..7fac4593d6d --- /dev/null +++ b/pac/atsamda1g/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/evsys/user.rs b/pac/atsamda1g/src/evsys/user.rs new file mode 100644 index 00000000000..06019221dab --- /dev/null +++ b/pac/atsamda1g/src/evsys/user.rs @@ -0,0 +1,176 @@ +#[doc = "Register `USER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `USER` reader - User Multiplexer Selection"] +pub struct USER_R(crate::FieldReader); +impl USER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + USER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USER` writer - User Multiplexer Selection"] +pub struct USER_W<'a> { + w: &'a mut W, +} +impl<'a> USER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Channel Event Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHANNEL_A { + #[doc = "0: No Channel Output Selected"] + _0 = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHANNEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHANNEL_A::_0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == CHANNEL_A::_0 + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHANNEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Channel Output Selected"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(CHANNEL_A::_0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - User Multiplexer Selection"] + #[inline(always)] + pub fn user(&self) -> USER_R { + USER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - User Multiplexer Selection"] + #[inline(always)] + pub fn user(&mut self) -> USER_W { + USER_W { w: self } + } + #[doc = "Bits 8:12 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/gclk.rs b/pac/atsamda1g/src/gclk.rs new file mode 100644 index 00000000000..c8e002f5502 --- /dev/null +++ b/pac/atsamda1g/src/gclk.rs @@ -0,0 +1,34 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status"] + pub status: crate::Reg, + #[doc = "0x02 - Generic Clock Control"] + pub clkctrl: crate::Reg, + #[doc = "0x04 - Generic Clock Generator Control"] + pub genctrl: crate::Reg, + #[doc = "0x08 - Generic Clock Generator Division"] + pub gendiv: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "CLKCTRL register accessor: an alias for `Reg`"] +pub type CLKCTRL = crate::Reg; +#[doc = "Generic Clock Control"] +pub mod clkctrl; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "GENDIV register accessor: an alias for `Reg`"] +pub type GENDIV = crate::Reg; +#[doc = "Generic Clock Generator Division"] +pub mod gendiv; diff --git a/pac/atsamda1g/src/gclk/clkctrl.rs b/pac/atsamda1g/src/gclk/clkctrl.rs new file mode 100644 index 00000000000..513de299ef9 --- /dev/null +++ b/pac/atsamda1g/src/gclk/clkctrl.rs @@ -0,0 +1,865 @@ +#[doc = "Register `CLKCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Selection ID\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ID_A { + #[doc = "0: DFLL48"] + DFLL48 = 0, + #[doc = "1: FDPLL"] + FDPLL = 1, + #[doc = "2: FDPLL32K"] + FDPLL32K = 2, + #[doc = "3: WDT"] + WDT = 3, + #[doc = "4: RTC"] + RTC = 4, + #[doc = "5: EIC"] + EIC = 5, + #[doc = "6: USB"] + USB = 6, + #[doc = "7: EVSYS_0"] + EVSYS_0 = 7, + #[doc = "8: EVSYS_1"] + EVSYS_1 = 8, + #[doc = "9: EVSYS_2"] + EVSYS_2 = 9, + #[doc = "10: EVSYS_3"] + EVSYS_3 = 10, + #[doc = "11: EVSYS_4"] + EVSYS_4 = 11, + #[doc = "12: EVSYS_5"] + EVSYS_5 = 12, + #[doc = "13: EVSYS_6"] + EVSYS_6 = 13, + #[doc = "14: EVSYS_7"] + EVSYS_7 = 14, + #[doc = "15: EVSYS_8"] + EVSYS_8 = 15, + #[doc = "16: EVSYS_9"] + EVSYS_9 = 16, + #[doc = "17: EVSYS_10"] + EVSYS_10 = 17, + #[doc = "18: EVSYS_11"] + EVSYS_11 = 18, + #[doc = "19: SERCOMX_SLOW"] + SERCOMX_SLOW = 19, + #[doc = "20: SERCOM0_CORE"] + SERCOM0_CORE = 20, + #[doc = "21: SERCOM1_CORE"] + SERCOM1_CORE = 21, + #[doc = "22: SERCOM2_CORE"] + SERCOM2_CORE = 22, + #[doc = "23: SERCOM3_CORE"] + SERCOM3_CORE = 23, + #[doc = "24: SERCOM4_CORE"] + SERCOM4_CORE = 24, + #[doc = "25: SERCOM5_CORE"] + SERCOM5_CORE = 25, + #[doc = "26: TCC0_TCC1"] + TCC0_TCC1 = 26, + #[doc = "27: TCC2_TC3"] + TCC2_TC3 = 27, + #[doc = "28: TC4_TC5"] + TC4_TC5 = 28, + #[doc = "29: TC6_TC7"] + TC6_TC7 = 29, + #[doc = "30: ADC"] + ADC = 30, + #[doc = "31: AC_DIG"] + AC_DIG = 31, + #[doc = "32: AC_ANA"] + AC_ANA = 32, + #[doc = "33: DAC"] + DAC = 33, + #[doc = "35: I2S_0"] + I2S_0 = 35, + #[doc = "36: I2S_1"] + I2S_1 = 36, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ID_A) -> Self { + variant as _ + } +} +#[doc = "Field `ID` reader - Generic Clock Selection ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ID_A::DFLL48), + 1 => Some(ID_A::FDPLL), + 2 => Some(ID_A::FDPLL32K), + 3 => Some(ID_A::WDT), + 4 => Some(ID_A::RTC), + 5 => Some(ID_A::EIC), + 6 => Some(ID_A::USB), + 7 => Some(ID_A::EVSYS_0), + 8 => Some(ID_A::EVSYS_1), + 9 => Some(ID_A::EVSYS_2), + 10 => Some(ID_A::EVSYS_3), + 11 => Some(ID_A::EVSYS_4), + 12 => Some(ID_A::EVSYS_5), + 13 => Some(ID_A::EVSYS_6), + 14 => Some(ID_A::EVSYS_7), + 15 => Some(ID_A::EVSYS_8), + 16 => Some(ID_A::EVSYS_9), + 17 => Some(ID_A::EVSYS_10), + 18 => Some(ID_A::EVSYS_11), + 19 => Some(ID_A::SERCOMX_SLOW), + 20 => Some(ID_A::SERCOM0_CORE), + 21 => Some(ID_A::SERCOM1_CORE), + 22 => Some(ID_A::SERCOM2_CORE), + 23 => Some(ID_A::SERCOM3_CORE), + 24 => Some(ID_A::SERCOM4_CORE), + 25 => Some(ID_A::SERCOM5_CORE), + 26 => Some(ID_A::TCC0_TCC1), + 27 => Some(ID_A::TCC2_TC3), + 28 => Some(ID_A::TC4_TC5), + 29 => Some(ID_A::TC6_TC7), + 30 => Some(ID_A::ADC), + 31 => Some(ID_A::AC_DIG), + 32 => Some(ID_A::AC_ANA), + 33 => Some(ID_A::DAC), + 35 => Some(ID_A::I2S_0), + 36 => Some(ID_A::I2S_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DFLL48`"] + #[inline(always)] + pub fn is_dfll48(&self) -> bool { + **self == ID_A::DFLL48 + } + #[doc = "Checks if the value of the field is `FDPLL`"] + #[inline(always)] + pub fn is_fdpll(&self) -> bool { + **self == ID_A::FDPLL + } + #[doc = "Checks if the value of the field is `FDPLL32K`"] + #[inline(always)] + pub fn is_fdpll32k(&self) -> bool { + **self == ID_A::FDPLL32K + } + #[doc = "Checks if the value of the field is `WDT`"] + #[inline(always)] + pub fn is_wdt(&self) -> bool { + **self == ID_A::WDT + } + #[doc = "Checks if the value of the field is `RTC`"] + #[inline(always)] + pub fn is_rtc(&self) -> bool { + **self == ID_A::RTC + } + #[doc = "Checks if the value of the field is `EIC`"] + #[inline(always)] + pub fn is_eic(&self) -> bool { + **self == ID_A::EIC + } + #[doc = "Checks if the value of the field is `USB`"] + #[inline(always)] + pub fn is_usb(&self) -> bool { + **self == ID_A::USB + } + #[doc = "Checks if the value of the field is `EVSYS_0`"] + #[inline(always)] + pub fn is_evsys_0(&self) -> bool { + **self == ID_A::EVSYS_0 + } + #[doc = "Checks if the value of the field is `EVSYS_1`"] + #[inline(always)] + pub fn is_evsys_1(&self) -> bool { + **self == ID_A::EVSYS_1 + } + #[doc = "Checks if the value of the field is `EVSYS_2`"] + #[inline(always)] + pub fn is_evsys_2(&self) -> bool { + **self == ID_A::EVSYS_2 + } + #[doc = "Checks if the value of the field is `EVSYS_3`"] + #[inline(always)] + pub fn is_evsys_3(&self) -> bool { + **self == ID_A::EVSYS_3 + } + #[doc = "Checks if the value of the field is `EVSYS_4`"] + #[inline(always)] + pub fn is_evsys_4(&self) -> bool { + **self == ID_A::EVSYS_4 + } + #[doc = "Checks if the value of the field is `EVSYS_5`"] + #[inline(always)] + pub fn is_evsys_5(&self) -> bool { + **self == ID_A::EVSYS_5 + } + #[doc = "Checks if the value of the field is `EVSYS_6`"] + #[inline(always)] + pub fn is_evsys_6(&self) -> bool { + **self == ID_A::EVSYS_6 + } + #[doc = "Checks if the value of the field is `EVSYS_7`"] + #[inline(always)] + pub fn is_evsys_7(&self) -> bool { + **self == ID_A::EVSYS_7 + } + #[doc = "Checks if the value of the field is `EVSYS_8`"] + #[inline(always)] + pub fn is_evsys_8(&self) -> bool { + **self == ID_A::EVSYS_8 + } + #[doc = "Checks if the value of the field is `EVSYS_9`"] + #[inline(always)] + pub fn is_evsys_9(&self) -> bool { + **self == ID_A::EVSYS_9 + } + #[doc = "Checks if the value of the field is `EVSYS_10`"] + #[inline(always)] + pub fn is_evsys_10(&self) -> bool { + **self == ID_A::EVSYS_10 + } + #[doc = "Checks if the value of the field is `EVSYS_11`"] + #[inline(always)] + pub fn is_evsys_11(&self) -> bool { + **self == ID_A::EVSYS_11 + } + #[doc = "Checks if the value of the field is `SERCOMX_SLOW`"] + #[inline(always)] + pub fn is_sercomx_slow(&self) -> bool { + **self == ID_A::SERCOMX_SLOW + } + #[doc = "Checks if the value of the field is `SERCOM0_CORE`"] + #[inline(always)] + pub fn is_sercom0_core(&self) -> bool { + **self == ID_A::SERCOM0_CORE + } + #[doc = "Checks if the value of the field is `SERCOM1_CORE`"] + #[inline(always)] + pub fn is_sercom1_core(&self) -> bool { + **self == ID_A::SERCOM1_CORE + } + #[doc = "Checks if the value of the field is `SERCOM2_CORE`"] + #[inline(always)] + pub fn is_sercom2_core(&self) -> bool { + **self == ID_A::SERCOM2_CORE + } + #[doc = "Checks if the value of the field is `SERCOM3_CORE`"] + #[inline(always)] + pub fn is_sercom3_core(&self) -> bool { + **self == ID_A::SERCOM3_CORE + } + #[doc = "Checks if the value of the field is `SERCOM4_CORE`"] + #[inline(always)] + pub fn is_sercom4_core(&self) -> bool { + **self == ID_A::SERCOM4_CORE + } + #[doc = "Checks if the value of the field is `SERCOM5_CORE`"] + #[inline(always)] + pub fn is_sercom5_core(&self) -> bool { + **self == ID_A::SERCOM5_CORE + } + #[doc = "Checks if the value of the field is `TCC0_TCC1`"] + #[inline(always)] + pub fn is_tcc0_tcc1(&self) -> bool { + **self == ID_A::TCC0_TCC1 + } + #[doc = "Checks if the value of the field is `TCC2_TC3`"] + #[inline(always)] + pub fn is_tcc2_tc3(&self) -> bool { + **self == ID_A::TCC2_TC3 + } + #[doc = "Checks if the value of the field is `TC4_TC5`"] + #[inline(always)] + pub fn is_tc4_tc5(&self) -> bool { + **self == ID_A::TC4_TC5 + } + #[doc = "Checks if the value of the field is `TC6_TC7`"] + #[inline(always)] + pub fn is_tc6_tc7(&self) -> bool { + **self == ID_A::TC6_TC7 + } + #[doc = "Checks if the value of the field is `ADC`"] + #[inline(always)] + pub fn is_adc(&self) -> bool { + **self == ID_A::ADC + } + #[doc = "Checks if the value of the field is `AC_DIG`"] + #[inline(always)] + pub fn is_ac_dig(&self) -> bool { + **self == ID_A::AC_DIG + } + #[doc = "Checks if the value of the field is `AC_ANA`"] + #[inline(always)] + pub fn is_ac_ana(&self) -> bool { + **self == ID_A::AC_ANA + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == ID_A::DAC + } + #[doc = "Checks if the value of the field is `I2S_0`"] + #[inline(always)] + pub fn is_i2s_0(&self) -> bool { + **self == ID_A::I2S_0 + } + #[doc = "Checks if the value of the field is `I2S_1`"] + #[inline(always)] + pub fn is_i2s_1(&self) -> bool { + **self == ID_A::I2S_1 + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Selection ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ID_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DFLL48"] + #[inline(always)] + pub fn dfll48(self) -> &'a mut W { + self.variant(ID_A::DFLL48) + } + #[doc = "FDPLL"] + #[inline(always)] + pub fn fdpll(self) -> &'a mut W { + self.variant(ID_A::FDPLL) + } + #[doc = "FDPLL32K"] + #[inline(always)] + pub fn fdpll32k(self) -> &'a mut W { + self.variant(ID_A::FDPLL32K) + } + #[doc = "WDT"] + #[inline(always)] + pub fn wdt(self) -> &'a mut W { + self.variant(ID_A::WDT) + } + #[doc = "RTC"] + #[inline(always)] + pub fn rtc(self) -> &'a mut W { + self.variant(ID_A::RTC) + } + #[doc = "EIC"] + #[inline(always)] + pub fn eic(self) -> &'a mut W { + self.variant(ID_A::EIC) + } + #[doc = "USB"] + #[inline(always)] + pub fn usb(self) -> &'a mut W { + self.variant(ID_A::USB) + } + #[doc = "EVSYS_0"] + #[inline(always)] + pub fn evsys_0(self) -> &'a mut W { + self.variant(ID_A::EVSYS_0) + } + #[doc = "EVSYS_1"] + #[inline(always)] + pub fn evsys_1(self) -> &'a mut W { + self.variant(ID_A::EVSYS_1) + } + #[doc = "EVSYS_2"] + #[inline(always)] + pub fn evsys_2(self) -> &'a mut W { + self.variant(ID_A::EVSYS_2) + } + #[doc = "EVSYS_3"] + #[inline(always)] + pub fn evsys_3(self) -> &'a mut W { + self.variant(ID_A::EVSYS_3) + } + #[doc = "EVSYS_4"] + #[inline(always)] + pub fn evsys_4(self) -> &'a mut W { + self.variant(ID_A::EVSYS_4) + } + #[doc = "EVSYS_5"] + #[inline(always)] + pub fn evsys_5(self) -> &'a mut W { + self.variant(ID_A::EVSYS_5) + } + #[doc = "EVSYS_6"] + #[inline(always)] + pub fn evsys_6(self) -> &'a mut W { + self.variant(ID_A::EVSYS_6) + } + #[doc = "EVSYS_7"] + #[inline(always)] + pub fn evsys_7(self) -> &'a mut W { + self.variant(ID_A::EVSYS_7) + } + #[doc = "EVSYS_8"] + #[inline(always)] + pub fn evsys_8(self) -> &'a mut W { + self.variant(ID_A::EVSYS_8) + } + #[doc = "EVSYS_9"] + #[inline(always)] + pub fn evsys_9(self) -> &'a mut W { + self.variant(ID_A::EVSYS_9) + } + #[doc = "EVSYS_10"] + #[inline(always)] + pub fn evsys_10(self) -> &'a mut W { + self.variant(ID_A::EVSYS_10) + } + #[doc = "EVSYS_11"] + #[inline(always)] + pub fn evsys_11(self) -> &'a mut W { + self.variant(ID_A::EVSYS_11) + } + #[doc = "SERCOMX_SLOW"] + #[inline(always)] + pub fn sercomx_slow(self) -> &'a mut W { + self.variant(ID_A::SERCOMX_SLOW) + } + #[doc = "SERCOM0_CORE"] + #[inline(always)] + pub fn sercom0_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM0_CORE) + } + #[doc = "SERCOM1_CORE"] + #[inline(always)] + pub fn sercom1_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM1_CORE) + } + #[doc = "SERCOM2_CORE"] + #[inline(always)] + pub fn sercom2_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM2_CORE) + } + #[doc = "SERCOM3_CORE"] + #[inline(always)] + pub fn sercom3_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM3_CORE) + } + #[doc = "SERCOM4_CORE"] + #[inline(always)] + pub fn sercom4_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM4_CORE) + } + #[doc = "SERCOM5_CORE"] + #[inline(always)] + pub fn sercom5_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM5_CORE) + } + #[doc = "TCC0_TCC1"] + #[inline(always)] + pub fn tcc0_tcc1(self) -> &'a mut W { + self.variant(ID_A::TCC0_TCC1) + } + #[doc = "TCC2_TC3"] + #[inline(always)] + pub fn tcc2_tc3(self) -> &'a mut W { + self.variant(ID_A::TCC2_TC3) + } + #[doc = "TC4_TC5"] + #[inline(always)] + pub fn tc4_tc5(self) -> &'a mut W { + self.variant(ID_A::TC4_TC5) + } + #[doc = "TC6_TC7"] + #[inline(always)] + pub fn tc6_tc7(self) -> &'a mut W { + self.variant(ID_A::TC6_TC7) + } + #[doc = "ADC"] + #[inline(always)] + pub fn adc(self) -> &'a mut W { + self.variant(ID_A::ADC) + } + #[doc = "AC_DIG"] + #[inline(always)] + pub fn ac_dig(self) -> &'a mut W { + self.variant(ID_A::AC_DIG) + } + #[doc = "AC_ANA"] + #[inline(always)] + pub fn ac_ana(self) -> &'a mut W { + self.variant(ID_A::AC_ANA) + } + #[doc = "DAC"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(ID_A::DAC) + } + #[doc = "I2S_0"] + #[inline(always)] + pub fn i2s_0(self) -> &'a mut W { + self.variant(ID_A::I2S_0) + } + #[doc = "I2S_1"] + #[inline(always)] + pub fn i2s_1(self) -> &'a mut W { + self.variant(ID_A::I2S_1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLKEN` reader - Clock Enable"] +pub struct CLKEN_R(crate::FieldReader); +impl CLKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKEN` writer - Clock Enable"] +pub struct CLKEN_W<'a> { + w: &'a mut W, +} +impl<'a> CLKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Generic Clock Selection ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:11 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 14 - Clock Enable"] + #[inline(always)] + pub fn clken(&self) -> CLKEN_R { + CLKEN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Generic Clock Selection ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:11 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 14 - Clock Enable"] + #[inline(always)] + pub fn clken(&mut self) -> CLKEN_W { + CLKEN_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkctrl](index.html) module"] +pub struct CLKCTRL_SPEC; +impl crate::RegisterSpec for CLKCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [clkctrl::R](R) reader structure"] +impl crate::Readable for CLKCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkctrl::W](W) writer structure"] +impl crate::Writable for CLKCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKCTRL to value 0"] +impl crate::Resettable for CLKCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/gclk/ctrl.rs b/pac/atsamda1g/src/gclk/ctrl.rs new file mode 100644 index 00000000000..2c4cbd696a1 --- /dev/null +++ b/pac/atsamda1g/src/gclk/ctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/gclk/genctrl.rs b/pac/atsamda1g/src/gclk/genctrl.rs new file mode 100644 index 00000000000..0c339999e03 --- /dev/null +++ b/pac/atsamda1g/src/gclk/genctrl.rs @@ -0,0 +1,609 @@ +#[doc = "Register `GENCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Generic Clock Generator Selection"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Generator Selection"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC8M oscillator output"] + OSC8M = 6, + #[doc = "7: DFLL48M output"] + DFLL48M = 7, + #[doc = "8: DPLL96M output"] + DPLL96M = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::XOSC), + 1 => Some(SRC_A::GCLKIN), + 2 => Some(SRC_A::GCLKGEN1), + 3 => Some(SRC_A::OSCULP32K), + 4 => Some(SRC_A::OSC32K), + 5 => Some(SRC_A::XOSC32K), + 6 => Some(SRC_A::OSC8M), + 7 => Some(SRC_A::DFLL48M), + 8 => Some(SRC_A::DPLL96M), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC8M`"] + #[inline(always)] + pub fn is_osc8m(&self) -> bool { + **self == SRC_A::OSC8M + } + #[doc = "Checks if the value of the field is `DFLL48M`"] + #[inline(always)] + pub fn is_dfll48m(&self) -> bool { + **self == SRC_A::DFLL48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC8M oscillator output"] + #[inline(always)] + pub fn osc8m(self) -> &'a mut W { + self.variant(SRC_A::OSC8M) + } + #[doc = "DFLL48M output"] + #[inline(always)] + pub fn dfll48m(self) -> &'a mut W { + self.variant(SRC_A::DFLL48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:12 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 16 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 17 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 18 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 19 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 20 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 21 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/gclk/gendiv.rs b/pac/atsamda1g/src/gclk/gendiv.rs new file mode 100644 index 00000000000..203d2e384c0 --- /dev/null +++ b/pac/atsamda1g/src/gclk/gendiv.rs @@ -0,0 +1,140 @@ +#[doc = "Register `GENDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Generic Clock Generator Selection"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Generator Selection"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 8)) | ((value as u32 & 0xffff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:23 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 8) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:23 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gendiv](index.html) module"] +pub struct GENDIV_SPEC; +impl crate::RegisterSpec for GENDIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gendiv::R](R) reader structure"] +impl crate::Readable for GENDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gendiv::W](W) writer structure"] +impl crate::Writable for GENDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENDIV to value 0"] +impl crate::Resettable for GENDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/gclk/status.rs b/pac/atsamda1g/src/gclk/status.rs new file mode 100644 index 00000000000..2667b356df2 --- /dev/null +++ b/pac/atsamda1g/src/gclk/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy Status"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy Status"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/generic.rs b/pac/atsamda1g/src/generic.rs new file mode 100644 index 00000000000..76159643acf --- /dev/null +++ b/pac/atsamda1g/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamda1g/src/i2s.rs b/pac/atsamda1g/src/i2s.rs new file mode 100644 index 00000000000..2a81ff75c9f --- /dev/null +++ b/pac/atsamda1g/src/i2s.rs @@ -0,0 +1,58 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04..0x0c - Clock Unit n Control"] + pub clkctrl: [crate::Reg; 2], + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x02], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x18 - Synchronization Status"] + pub syncbusy: crate::Reg, + _reserved6: [u8; 0x06], + #[doc = "0x20..0x28 - Serializer n Control"] + pub serctrl: [crate::Reg; 2], + _reserved7: [u8; 0x08], + #[doc = "0x30..0x38 - Data n"] + pub data: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CLKCTRL register accessor: an alias for `Reg`"] +pub type CLKCTRL = crate::Reg; +#[doc = "Clock Unit n Control"] +pub mod clkctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "SERCTRL register accessor: an alias for `Reg`"] +pub type SERCTRL = crate::Reg; +#[doc = "Serializer n Control"] +pub mod serctrl; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data n"] +pub mod data; diff --git a/pac/atsamda1g/src/i2s/clkctrl.rs b/pac/atsamda1g/src/i2s/clkctrl.rs new file mode 100644 index 00000000000..b2d71698332 --- /dev/null +++ b/pac/atsamda1g/src/i2s/clkctrl.rs @@ -0,0 +1,1013 @@ +#[doc = "Register `CLKCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Slot Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLOTSIZE_A { + #[doc = "0: 8-bit Slot for Clock Unit n"] + _8 = 0, + #[doc = "1: 16-bit Slot for Clock Unit n"] + _16 = 1, + #[doc = "2: 24-bit Slot for Clock Unit n"] + _24 = 2, + #[doc = "3: 32-bit Slot for Clock Unit n"] + _32 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLOTSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLOTSIZE` reader - Slot Size"] +pub struct SLOTSIZE_R(crate::FieldReader); +impl SLOTSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOTSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLOTSIZE_A { + match self.bits { + 0 => SLOTSIZE_A::_8, + 1 => SLOTSIZE_A::_16, + 2 => SLOTSIZE_A::_24, + 3 => SLOTSIZE_A::_32, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SLOTSIZE_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SLOTSIZE_A::_16 + } + #[doc = "Checks if the value of the field is `_24`"] + #[inline(always)] + pub fn is_24(&self) -> bool { + **self == SLOTSIZE_A::_24 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SLOTSIZE_A::_32 + } +} +impl core::ops::Deref for SLOTSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTSIZE` writer - Slot Size"] +pub struct SLOTSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLOTSIZE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_8) + } + #[doc = "16-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_16) + } + #[doc = "24-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _24(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_24) + } + #[doc = "32-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `NBSLOTS` reader - Number of Slots in Frame"] +pub struct NBSLOTS_R(crate::FieldReader); +impl NBSLOTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NBSLOTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NBSLOTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NBSLOTS` writer - Number of Slots in Frame"] +pub struct NBSLOTS_W<'a> { + w: &'a mut W, +} +impl<'a> NBSLOTS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Frame Sync Width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSWIDTH_A { + #[doc = "0: Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"] + SLOT = 0, + #[doc = "1: Frame Sync Pulse is half a Frame wide"] + HALF = 1, + #[doc = "2: Frame Sync Pulse is 1 Bit wide"] + BIT = 2, + #[doc = "3: Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"] + BURST = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSWIDTH_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSWIDTH` reader - Frame Sync Width"] +pub struct FSWIDTH_R(crate::FieldReader); +impl FSWIDTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSWIDTH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSWIDTH_A { + match self.bits { + 0 => FSWIDTH_A::SLOT, + 1 => FSWIDTH_A::HALF, + 2 => FSWIDTH_A::BIT, + 3 => FSWIDTH_A::BURST, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `SLOT`"] + #[inline(always)] + pub fn is_slot(&self) -> bool { + **self == FSWIDTH_A::SLOT + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == FSWIDTH_A::HALF + } + #[doc = "Checks if the value of the field is `BIT`"] + #[inline(always)] + pub fn is_bit_(&self) -> bool { + **self == FSWIDTH_A::BIT + } + #[doc = "Checks if the value of the field is `BURST`"] + #[inline(always)] + pub fn is_burst(&self) -> bool { + **self == FSWIDTH_A::BURST + } +} +impl core::ops::Deref for FSWIDTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSWIDTH` writer - Frame Sync Width"] +pub struct FSWIDTH_W<'a> { + w: &'a mut W, +} +impl<'a> FSWIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FSWIDTH_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"] + #[inline(always)] + pub fn slot(self) -> &'a mut W { + self.variant(FSWIDTH_A::SLOT) + } + #[doc = "Frame Sync Pulse is half a Frame wide"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(FSWIDTH_A::HALF) + } + #[doc = "Frame Sync Pulse is 1 Bit wide"] + #[inline(always)] + pub fn bit_(self) -> &'a mut W { + self.variant(FSWIDTH_A::BIT) + } + #[doc = "Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"] + #[inline(always)] + pub fn burst(self) -> &'a mut W { + self.variant(FSWIDTH_A::BURST) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Data Delay from Frame Sync\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BITDELAY_A { + #[doc = "0: Left Justified (0 Bit Delay)"] + LJ = 0, + #[doc = "1: I2S (1 Bit Delay)"] + I2S = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BITDELAY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BITDELAY` reader - Data Delay from Frame Sync"] +pub struct BITDELAY_R(crate::FieldReader); +impl BITDELAY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BITDELAY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BITDELAY_A { + match self.bits { + false => BITDELAY_A::LJ, + true => BITDELAY_A::I2S, + } + } + #[doc = "Checks if the value of the field is `LJ`"] + #[inline(always)] + pub fn is_lj(&self) -> bool { + **self == BITDELAY_A::LJ + } + #[doc = "Checks if the value of the field is `I2S`"] + #[inline(always)] + pub fn is_i2s(&self) -> bool { + **self == BITDELAY_A::I2S + } +} +impl core::ops::Deref for BITDELAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITDELAY` writer - Data Delay from Frame Sync"] +pub struct BITDELAY_W<'a> { + w: &'a mut W, +} +impl<'a> BITDELAY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BITDELAY_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Left Justified (0 Bit Delay)"] + #[inline(always)] + pub fn lj(self) -> &'a mut W { + self.variant(BITDELAY_A::LJ) + } + #[doc = "I2S (1 Bit Delay)"] + #[inline(always)] + pub fn i2s(self) -> &'a mut W { + self.variant(BITDELAY_A::I2S) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Frame Sync Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FSSEL_A { + #[doc = "0: Divided Serial Clock n is used as Frame Sync n source"] + SCKDIV = 0, + #[doc = "1: FSn input pin is used as Frame Sync n source"] + FSPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FSSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FSSEL` reader - Frame Sync Select"] +pub struct FSSEL_R(crate::FieldReader); +impl FSSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSSEL_A { + match self.bits { + false => FSSEL_A::SCKDIV, + true => FSSEL_A::FSPIN, + } + } + #[doc = "Checks if the value of the field is `SCKDIV`"] + #[inline(always)] + pub fn is_sckdiv(&self) -> bool { + **self == FSSEL_A::SCKDIV + } + #[doc = "Checks if the value of the field is `FSPIN`"] + #[inline(always)] + pub fn is_fspin(&self) -> bool { + **self == FSSEL_A::FSPIN + } +} +impl core::ops::Deref for FSSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSSEL` writer - Frame Sync Select"] +pub struct FSSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FSSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FSSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divided Serial Clock n is used as Frame Sync n source"] + #[inline(always)] + pub fn sckdiv(self) -> &'a mut W { + self.variant(FSSEL_A::SCKDIV) + } + #[doc = "FSn input pin is used as Frame Sync n source"] + #[inline(always)] + pub fn fspin(self) -> &'a mut W { + self.variant(FSSEL_A::FSPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FSINV` reader - Frame Sync Invert"] +pub struct FSINV_R(crate::FieldReader); +impl FSINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSINV` writer - Frame Sync Invert"] +pub struct FSINV_W<'a> { + w: &'a mut W, +} +impl<'a> FSINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Serial Clock Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SCKSEL_A { + #[doc = "0: Divided Master Clock n is used as Serial Clock n source"] + MCKDIV = 0, + #[doc = "1: SCKn input pin is used as Serial Clock n source"] + SCKPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SCKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SCKSEL` reader - Serial Clock Select"] +pub struct SCKSEL_R(crate::FieldReader); +impl SCKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SCKSEL_A { + match self.bits { + false => SCKSEL_A::MCKDIV, + true => SCKSEL_A::SCKPIN, + } + } + #[doc = "Checks if the value of the field is `MCKDIV`"] + #[inline(always)] + pub fn is_mckdiv(&self) -> bool { + **self == SCKSEL_A::MCKDIV + } + #[doc = "Checks if the value of the field is `SCKPIN`"] + #[inline(always)] + pub fn is_sckpin(&self) -> bool { + **self == SCKSEL_A::SCKPIN + } +} +impl core::ops::Deref for SCKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCKSEL` writer - Serial Clock Select"] +pub struct SCKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SCKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SCKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divided Master Clock n is used as Serial Clock n source"] + #[inline(always)] + pub fn mckdiv(self) -> &'a mut W { + self.variant(SCKSEL_A::MCKDIV) + } + #[doc = "SCKn input pin is used as Serial Clock n source"] + #[inline(always)] + pub fn sckpin(self) -> &'a mut W { + self.variant(SCKSEL_A::SCKPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Master Clock Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MCKSEL_A { + #[doc = "0: GCLK_I2S_n is used as Master Clock n source"] + GCLK = 0, + #[doc = "1: MCKn input pin is used as Master Clock n source"] + MCKPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MCKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MCKSEL` reader - Master Clock Select"] +pub struct MCKSEL_R(crate::FieldReader); +impl MCKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MCKSEL_A { + match self.bits { + false => MCKSEL_A::GCLK, + true => MCKSEL_A::MCKPIN, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == MCKSEL_A::GCLK + } + #[doc = "Checks if the value of the field is `MCKPIN`"] + #[inline(always)] + pub fn is_mckpin(&self) -> bool { + **self == MCKSEL_A::MCKPIN + } +} +impl core::ops::Deref for MCKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKSEL` writer - Master Clock Select"] +pub struct MCKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> MCKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MCKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "GCLK_I2S_n is used as Master Clock n source"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(MCKSEL_A::GCLK) + } + #[doc = "MCKn input pin is used as Master Clock n source"] + #[inline(always)] + pub fn mckpin(self) -> &'a mut W { + self.variant(MCKSEL_A::MCKPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCKEN` reader - Master Clock Enable"] +pub struct MCKEN_R(crate::FieldReader); +impl MCKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKEN` writer - Master Clock Enable"] +pub struct MCKEN_W<'a> { + w: &'a mut W, +} +impl<'a> MCKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCKDIV` reader - Master Clock Division Factor"] +pub struct MCKDIV_R(crate::FieldReader); +impl MCKDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MCKDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKDIV` writer - Master Clock Division Factor"] +pub struct MCKDIV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKDIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 19)) | ((value as u32 & 0x1f) << 19); + self.w + } +} +#[doc = "Field `MCKOUTDIV` reader - Master Clock Output Division Factor"] +pub struct MCKOUTDIV_R(crate::FieldReader); +impl MCKOUTDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MCKOUTDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKOUTDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKOUTDIV` writer - Master Clock Output Division Factor"] +pub struct MCKOUTDIV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKOUTDIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `FSOUTINV` reader - Frame Sync Output Invert"] +pub struct FSOUTINV_R(crate::FieldReader); +impl FSOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSOUTINV` writer - Frame Sync Output Invert"] +pub struct FSOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> FSOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `SCKOUTINV` reader - Serial Clock Output Invert"] +pub struct SCKOUTINV_R(crate::FieldReader); +impl SCKOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCKOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCKOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCKOUTINV` writer - Serial Clock Output Invert"] +pub struct SCKOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> SCKOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `MCKOUTINV` reader - Master Clock Output Invert"] +pub struct MCKOUTINV_R(crate::FieldReader); +impl MCKOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKOUTINV` writer - Master Clock Output Invert"] +pub struct MCKOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Slot Size"] + #[inline(always)] + pub fn slotsize(&self) -> SLOTSIZE_R { + SLOTSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:4 - Number of Slots in Frame"] + #[inline(always)] + pub fn nbslots(&self) -> NBSLOTS_R { + NBSLOTS_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bits 5:6 - Frame Sync Width"] + #[inline(always)] + pub fn fswidth(&self) -> FSWIDTH_R { + FSWIDTH_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Data Delay from Frame Sync"] + #[inline(always)] + pub fn bitdelay(&self) -> BITDELAY_R { + BITDELAY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Frame Sync Select"] + #[inline(always)] + pub fn fssel(&self) -> FSSEL_R { + FSSEL_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 11 - Frame Sync Invert"] + #[inline(always)] + pub fn fsinv(&self) -> FSINV_R { + FSINV_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Serial Clock Select"] + #[inline(always)] + pub fn scksel(&self) -> SCKSEL_R { + SCKSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 16 - Master Clock Select"] + #[inline(always)] + pub fn mcksel(&self) -> MCKSEL_R { + MCKSEL_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 18 - Master Clock Enable"] + #[inline(always)] + pub fn mcken(&self) -> MCKEN_R { + MCKEN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bits 19:23 - Master Clock Division Factor"] + #[inline(always)] + pub fn mckdiv(&self) -> MCKDIV_R { + MCKDIV_R::new(((self.bits >> 19) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - Master Clock Output Division Factor"] + #[inline(always)] + pub fn mckoutdiv(&self) -> MCKOUTDIV_R { + MCKOUTDIV_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 29 - Frame Sync Output Invert"] + #[inline(always)] + pub fn fsoutinv(&self) -> FSOUTINV_R { + FSOUTINV_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Serial Clock Output Invert"] + #[inline(always)] + pub fn sckoutinv(&self) -> SCKOUTINV_R { + SCKOUTINV_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Master Clock Output Invert"] + #[inline(always)] + pub fn mckoutinv(&self) -> MCKOUTINV_R { + MCKOUTINV_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Slot Size"] + #[inline(always)] + pub fn slotsize(&mut self) -> SLOTSIZE_W { + SLOTSIZE_W { w: self } + } + #[doc = "Bits 2:4 - Number of Slots in Frame"] + #[inline(always)] + pub fn nbslots(&mut self) -> NBSLOTS_W { + NBSLOTS_W { w: self } + } + #[doc = "Bits 5:6 - Frame Sync Width"] + #[inline(always)] + pub fn fswidth(&mut self) -> FSWIDTH_W { + FSWIDTH_W { w: self } + } + #[doc = "Bit 7 - Data Delay from Frame Sync"] + #[inline(always)] + pub fn bitdelay(&mut self) -> BITDELAY_W { + BITDELAY_W { w: self } + } + #[doc = "Bit 8 - Frame Sync Select"] + #[inline(always)] + pub fn fssel(&mut self) -> FSSEL_W { + FSSEL_W { w: self } + } + #[doc = "Bit 11 - Frame Sync Invert"] + #[inline(always)] + pub fn fsinv(&mut self) -> FSINV_W { + FSINV_W { w: self } + } + #[doc = "Bit 12 - Serial Clock Select"] + #[inline(always)] + pub fn scksel(&mut self) -> SCKSEL_W { + SCKSEL_W { w: self } + } + #[doc = "Bit 16 - Master Clock Select"] + #[inline(always)] + pub fn mcksel(&mut self) -> MCKSEL_W { + MCKSEL_W { w: self } + } + #[doc = "Bit 18 - Master Clock Enable"] + #[inline(always)] + pub fn mcken(&mut self) -> MCKEN_W { + MCKEN_W { w: self } + } + #[doc = "Bits 19:23 - Master Clock Division Factor"] + #[inline(always)] + pub fn mckdiv(&mut self) -> MCKDIV_W { + MCKDIV_W { w: self } + } + #[doc = "Bits 24:28 - Master Clock Output Division Factor"] + #[inline(always)] + pub fn mckoutdiv(&mut self) -> MCKOUTDIV_W { + MCKOUTDIV_W { w: self } + } + #[doc = "Bit 29 - Frame Sync Output Invert"] + #[inline(always)] + pub fn fsoutinv(&mut self) -> FSOUTINV_W { + FSOUTINV_W { w: self } + } + #[doc = "Bit 30 - Serial Clock Output Invert"] + #[inline(always)] + pub fn sckoutinv(&mut self) -> SCKOUTINV_W { + SCKOUTINV_W { w: self } + } + #[doc = "Bit 31 - Master Clock Output Invert"] + #[inline(always)] + pub fn mckoutinv(&mut self) -> MCKOUTINV_W { + MCKOUTINV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Unit n Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkctrl](index.html) module"] +pub struct CLKCTRL_SPEC; +impl crate::RegisterSpec for CLKCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkctrl::R](R) reader structure"] +impl crate::Readable for CLKCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkctrl::W](W) writer structure"] +impl crate::Writable for CLKCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKCTRL[%s] +to value 0"] +impl crate::Resettable for CLKCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/i2s/ctrla.rs b/pac/atsamda1g/src/i2s/ctrla.rs new file mode 100644 index 00000000000..116902b0a11 --- /dev/null +++ b/pac/atsamda1g/src/i2s/ctrla.rs @@ -0,0 +1,348 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CKEN0` reader - Clock Unit 0 Enable"] +pub struct CKEN0_R(crate::FieldReader); +impl CKEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN0` writer - Clock Unit 0 Enable"] +pub struct CKEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CKEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CKEN1` reader - Clock Unit 1 Enable"] +pub struct CKEN1_R(crate::FieldReader); +impl CKEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN1` writer - Clock Unit 1 Enable"] +pub struct CKEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CKEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SEREN0` reader - Serializer 0 Enable"] +pub struct SEREN0_R(crate::FieldReader); +impl SEREN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN0` writer - Serializer 0 Enable"] +pub struct SEREN0_W<'a> { + w: &'a mut W, +} +impl<'a> SEREN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SEREN1` reader - Serializer 1 Enable"] +pub struct SEREN1_R(crate::FieldReader); +impl SEREN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN1` writer - Serializer 1 Enable"] +pub struct SEREN1_W<'a> { + w: &'a mut W, +} +impl<'a> SEREN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Unit 0 Enable"] + #[inline(always)] + pub fn cken0(&self) -> CKEN0_R { + CKEN0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Unit 1 Enable"] + #[inline(always)] + pub fn cken1(&self) -> CKEN1_R { + CKEN1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Serializer 0 Enable"] + #[inline(always)] + pub fn seren0(&self) -> SEREN0_R { + SEREN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Serializer 1 Enable"] + #[inline(always)] + pub fn seren1(&self) -> SEREN1_R { + SEREN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Clock Unit 0 Enable"] + #[inline(always)] + pub fn cken0(&mut self) -> CKEN0_W { + CKEN0_W { w: self } + } + #[doc = "Bit 3 - Clock Unit 1 Enable"] + #[inline(always)] + pub fn cken1(&mut self) -> CKEN1_W { + CKEN1_W { w: self } + } + #[doc = "Bit 4 - Serializer 0 Enable"] + #[inline(always)] + pub fn seren0(&mut self) -> SEREN0_W { + SEREN0_W { w: self } + } + #[doc = "Bit 5 - Serializer 1 Enable"] + #[inline(always)] + pub fn seren1(&mut self) -> SEREN1_W { + SEREN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/i2s/data.rs b/pac/atsamda1g/src/i2s/data.rs new file mode 100644 index 00000000000..6184a1e36a2 --- /dev/null +++ b/pac/atsamda1g/src/i2s/data.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DATA[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Sample Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Sample Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Sample Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Sample Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA[%s] +to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/i2s/intenclr.rs b/pac/atsamda1g/src/i2s/intenclr.rs new file mode 100644 index 00000000000..8bfa22bba98 --- /dev/null +++ b/pac/atsamda1g/src/i2s/intenclr.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/i2s/intenset.rs b/pac/atsamda1g/src/i2s/intenset.rs new file mode 100644 index 00000000000..45473048a4d --- /dev/null +++ b/pac/atsamda1g/src/i2s/intenset.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/i2s/intflag.rs b/pac/atsamda1g/src/i2s/intflag.rs new file mode 100644 index 00000000000..eaedff6ff40 --- /dev/null +++ b/pac/atsamda1g/src/i2s/intflag.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/i2s/serctrl.rs b/pac/atsamda1g/src/i2s/serctrl.rs new file mode 100644 index 00000000000..1c1ab945454 --- /dev/null +++ b/pac/atsamda1g/src/i2s/serctrl.rs @@ -0,0 +1,1622 @@ +#[doc = "Register `SERCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SERCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Serializer Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERMODE_A { + #[doc = "0: Receive"] + RX = 0, + #[doc = "1: Transmit"] + TX = 1, + #[doc = "2: Receive one PDM data on each serial clock edge"] + PDM2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERMODE` reader - Serializer Mode"] +pub struct SERMODE_R(crate::FieldReader); +impl SERMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERMODE_A::RX), + 1 => Some(SERMODE_A::TX), + 2 => Some(SERMODE_A::PDM2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + **self == SERMODE_A::RX + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + **self == SERMODE_A::TX + } + #[doc = "Checks if the value of the field is `PDM2`"] + #[inline(always)] + pub fn is_pdm2(&self) -> bool { + **self == SERMODE_A::PDM2 + } +} +impl core::ops::Deref for SERMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERMODE` writer - Serializer Mode"] +pub struct SERMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SERMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SERMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Receive"] + #[inline(always)] + pub fn rx(self) -> &'a mut W { + self.variant(SERMODE_A::RX) + } + #[doc = "Transmit"] + #[inline(always)] + pub fn tx(self) -> &'a mut W { + self.variant(SERMODE_A::TX) + } + #[doc = "Receive one PDM data on each serial clock edge"] + #[inline(always)] + pub fn pdm2(self) -> &'a mut W { + self.variant(SERMODE_A::PDM2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Line Default Line when Slot Disabled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXDEFAULT_A { + #[doc = "0: Output Default Value is 0"] + ZERO = 0, + #[doc = "1: Output Default Value is 1"] + ONE = 1, + #[doc = "3: Output Default Value is high impedance"] + HIZ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXDEFAULT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXDEFAULT` reader - Line Default Line when Slot Disabled"] +pub struct TXDEFAULT_R(crate::FieldReader); +impl TXDEFAULT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXDEFAULT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXDEFAULT_A::ZERO), + 1 => Some(TXDEFAULT_A::ONE), + 3 => Some(TXDEFAULT_A::HIZ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TXDEFAULT_A::ZERO + } + #[doc = "Checks if the value of the field is `ONE`"] + #[inline(always)] + pub fn is_one(&self) -> bool { + **self == TXDEFAULT_A::ONE + } + #[doc = "Checks if the value of the field is `HIZ`"] + #[inline(always)] + pub fn is_hiz(&self) -> bool { + **self == TXDEFAULT_A::HIZ + } +} +impl core::ops::Deref for TXDEFAULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXDEFAULT` writer - Line Default Line when Slot Disabled"] +pub struct TXDEFAULT_W<'a> { + w: &'a mut W, +} +impl<'a> TXDEFAULT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXDEFAULT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Output Default Value is 0"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TXDEFAULT_A::ZERO) + } + #[doc = "Output Default Value is 1"] + #[inline(always)] + pub fn one(self) -> &'a mut W { + self.variant(TXDEFAULT_A::ONE) + } + #[doc = "Output Default Value is high impedance"] + #[inline(always)] + pub fn hiz(self) -> &'a mut W { + self.variant(TXDEFAULT_A::HIZ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Transmit Data when Underrun\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSAME_A { + #[doc = "0: Zero data transmitted in case of underrun"] + ZERO = 0, + #[doc = "1: Last data transmitted in case of underrun"] + SAME = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSAME_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSAME` reader - Transmit Data when Underrun"] +pub struct TXSAME_R(crate::FieldReader); +impl TXSAME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSAME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSAME_A { + match self.bits { + false => TXSAME_A::ZERO, + true => TXSAME_A::SAME, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TXSAME_A::ZERO + } + #[doc = "Checks if the value of the field is `SAME`"] + #[inline(always)] + pub fn is_same(&self) -> bool { + **self == TXSAME_A::SAME + } +} +impl core::ops::Deref for TXSAME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSAME` writer - Transmit Data when Underrun"] +pub struct TXSAME_W<'a> { + w: &'a mut W, +} +impl<'a> TXSAME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXSAME_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Zero data transmitted in case of underrun"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TXSAME_A::ZERO) + } + #[doc = "Last data transmitted in case of underrun"] + #[inline(always)] + pub fn same(self) -> &'a mut W { + self.variant(TXSAME_A::SAME) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Clock Unit Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSEL_A { + #[doc = "0: Use Clock Unit 0"] + CLK0 = 0, + #[doc = "1: Use Clock Unit 1"] + CLK1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSEL` reader - Clock Unit Selection"] +pub struct CLKSEL_R(crate::FieldReader); +impl CLKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSEL_A { + match self.bits { + false => CLKSEL_A::CLK0, + true => CLKSEL_A::CLK1, + } + } + #[doc = "Checks if the value of the field is `CLK0`"] + #[inline(always)] + pub fn is_clk0(&self) -> bool { + **self == CLKSEL_A::CLK0 + } + #[doc = "Checks if the value of the field is `CLK1`"] + #[inline(always)] + pub fn is_clk1(&self) -> bool { + **self == CLKSEL_A::CLK1 + } +} +impl core::ops::Deref for CLKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSEL` writer - Clock Unit Selection"] +pub struct CLKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Use Clock Unit 0"] + #[inline(always)] + pub fn clk0(self) -> &'a mut W { + self.variant(CLKSEL_A::CLK0) + } + #[doc = "Use Clock Unit 1"] + #[inline(always)] + pub fn clk1(self) -> &'a mut W { + self.variant(CLKSEL_A::CLK1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Data Slot Formatting Adjust\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLOTADJ_A { + #[doc = "0: Data is right adjusted in slot"] + RIGHT = 0, + #[doc = "1: Data is left adjusted in slot"] + LEFT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLOTADJ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLOTADJ` reader - Data Slot Formatting Adjust"] +pub struct SLOTADJ_R(crate::FieldReader); +impl SLOTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTADJ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLOTADJ_A { + match self.bits { + false => SLOTADJ_A::RIGHT, + true => SLOTADJ_A::LEFT, + } + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + **self == SLOTADJ_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + **self == SLOTADJ_A::LEFT + } +} +impl core::ops::Deref for SLOTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTADJ` writer - Data Slot Formatting Adjust"] +pub struct SLOTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTADJ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLOTADJ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Data is right adjusted in slot"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(SLOTADJ_A::RIGHT) + } + #[doc = "Data is left adjusted in slot"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(SLOTADJ_A::LEFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Data Word Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DATASIZE_A { + #[doc = "0: 32 bits"] + _32 = 0, + #[doc = "1: 24 bits"] + _24 = 1, + #[doc = "2: 20 bits"] + _20 = 2, + #[doc = "3: 18 bits"] + _18 = 3, + #[doc = "4: 16 bits"] + _16 = 4, + #[doc = "5: 16 bits compact stereo"] + _16C = 5, + #[doc = "6: 8 bits"] + _8 = 6, + #[doc = "7: 8 bits compact stereo"] + _8C = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATASIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DATASIZE` reader - Data Word Size"] +pub struct DATASIZE_R(crate::FieldReader); +impl DATASIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATASIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATASIZE_A { + match self.bits { + 0 => DATASIZE_A::_32, + 1 => DATASIZE_A::_24, + 2 => DATASIZE_A::_20, + 3 => DATASIZE_A::_18, + 4 => DATASIZE_A::_16, + 5 => DATASIZE_A::_16C, + 6 => DATASIZE_A::_8, + 7 => DATASIZE_A::_8C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == DATASIZE_A::_32 + } + #[doc = "Checks if the value of the field is `_24`"] + #[inline(always)] + pub fn is_24(&self) -> bool { + **self == DATASIZE_A::_24 + } + #[doc = "Checks if the value of the field is `_20`"] + #[inline(always)] + pub fn is_20(&self) -> bool { + **self == DATASIZE_A::_20 + } + #[doc = "Checks if the value of the field is `_18`"] + #[inline(always)] + pub fn is_18(&self) -> bool { + **self == DATASIZE_A::_18 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == DATASIZE_A::_16 + } + #[doc = "Checks if the value of the field is `_16C`"] + #[inline(always)] + pub fn is_16c(&self) -> bool { + **self == DATASIZE_A::_16C + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == DATASIZE_A::_8 + } + #[doc = "Checks if the value of the field is `_8C`"] + #[inline(always)] + pub fn is_8c(&self) -> bool { + **self == DATASIZE_A::_8C + } +} +impl core::ops::Deref for DATASIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATASIZE` writer - Data Word Size"] +pub struct DATASIZE_W<'a> { + w: &'a mut W, +} +impl<'a> DATASIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATASIZE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(DATASIZE_A::_32) + } + #[doc = "24 bits"] + #[inline(always)] + pub fn _24(self) -> &'a mut W { + self.variant(DATASIZE_A::_24) + } + #[doc = "20 bits"] + #[inline(always)] + pub fn _20(self) -> &'a mut W { + self.variant(DATASIZE_A::_20) + } + #[doc = "18 bits"] + #[inline(always)] + pub fn _18(self) -> &'a mut W { + self.variant(DATASIZE_A::_18) + } + #[doc = "16 bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(DATASIZE_A::_16) + } + #[doc = "16 bits compact stereo"] + #[inline(always)] + pub fn _16c(self) -> &'a mut W { + self.variant(DATASIZE_A::_16C) + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(DATASIZE_A::_8) + } + #[doc = "8 bits compact stereo"] + #[inline(always)] + pub fn _8c(self) -> &'a mut W { + self.variant(DATASIZE_A::_8C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Data Word Formatting Adjust\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WORDADJ_A { + #[doc = "0: Data is right adjusted in word"] + RIGHT = 0, + #[doc = "1: Data is left adjusted in word"] + LEFT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WORDADJ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WORDADJ` reader - Data Word Formatting Adjust"] +pub struct WORDADJ_R(crate::FieldReader); +impl WORDADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WORDADJ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WORDADJ_A { + match self.bits { + false => WORDADJ_A::RIGHT, + true => WORDADJ_A::LEFT, + } + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + **self == WORDADJ_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + **self == WORDADJ_A::LEFT + } +} +impl core::ops::Deref for WORDADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WORDADJ` writer - Data Word Formatting Adjust"] +pub struct WORDADJ_W<'a> { + w: &'a mut W, +} +impl<'a> WORDADJ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WORDADJ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Data is right adjusted in word"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(WORDADJ_A::RIGHT) + } + #[doc = "Data is left adjusted in word"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(WORDADJ_A::LEFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Data Formatting Bit Extension\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EXTEND_A { + #[doc = "0: Extend with zeroes"] + ZERO = 0, + #[doc = "1: Extend with ones"] + ONE = 1, + #[doc = "2: Extend with Most Significant Bit"] + MSBIT = 2, + #[doc = "3: Extend with Least Significant Bit"] + LSBIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EXTEND_A) -> Self { + variant as _ + } +} +#[doc = "Field `EXTEND` reader - Data Formatting Bit Extension"] +pub struct EXTEND_R(crate::FieldReader); +impl EXTEND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EXTEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EXTEND_A { + match self.bits { + 0 => EXTEND_A::ZERO, + 1 => EXTEND_A::ONE, + 2 => EXTEND_A::MSBIT, + 3 => EXTEND_A::LSBIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == EXTEND_A::ZERO + } + #[doc = "Checks if the value of the field is `ONE`"] + #[inline(always)] + pub fn is_one(&self) -> bool { + **self == EXTEND_A::ONE + } + #[doc = "Checks if the value of the field is `MSBIT`"] + #[inline(always)] + pub fn is_msbit(&self) -> bool { + **self == EXTEND_A::MSBIT + } + #[doc = "Checks if the value of the field is `LSBIT`"] + #[inline(always)] + pub fn is_lsbit(&self) -> bool { + **self == EXTEND_A::LSBIT + } +} +impl core::ops::Deref for EXTEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTEND` writer - Data Formatting Bit Extension"] +pub struct EXTEND_W<'a> { + w: &'a mut W, +} +impl<'a> EXTEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EXTEND_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Extend with zeroes"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(EXTEND_A::ZERO) + } + #[doc = "Extend with ones"] + #[inline(always)] + pub fn one(self) -> &'a mut W { + self.variant(EXTEND_A::ONE) + } + #[doc = "Extend with Most Significant Bit"] + #[inline(always)] + pub fn msbit(self) -> &'a mut W { + self.variant(EXTEND_A::MSBIT) + } + #[doc = "Extend with Least Significant Bit"] + #[inline(always)] + pub fn lsbit(self) -> &'a mut W { + self.variant(EXTEND_A::LSBIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Data Formatting Bit Reverse\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BITREV_A { + #[doc = "0: Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)"] + MSBIT = 0, + #[doc = "1: Transfer Data Least Significant Bit (LSB) first"] + LSBIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BITREV_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BITREV` reader - Data Formatting Bit Reverse"] +pub struct BITREV_R(crate::FieldReader); +impl BITREV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BITREV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BITREV_A { + match self.bits { + false => BITREV_A::MSBIT, + true => BITREV_A::LSBIT, + } + } + #[doc = "Checks if the value of the field is `MSBIT`"] + #[inline(always)] + pub fn is_msbit(&self) -> bool { + **self == BITREV_A::MSBIT + } + #[doc = "Checks if the value of the field is `LSBIT`"] + #[inline(always)] + pub fn is_lsbit(&self) -> bool { + **self == BITREV_A::LSBIT + } +} +impl core::ops::Deref for BITREV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITREV` writer - Data Formatting Bit Reverse"] +pub struct BITREV_W<'a> { + w: &'a mut W, +} +impl<'a> BITREV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BITREV_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)"] + #[inline(always)] + pub fn msbit(self) -> &'a mut W { + self.variant(BITREV_A::MSBIT) + } + #[doc = "Transfer Data Least Significant Bit (LSB) first"] + #[inline(always)] + pub fn lsbit(self) -> &'a mut W { + self.variant(BITREV_A::LSBIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `SLOTDIS0` reader - Slot 0 Disabled for this Serializer"] +pub struct SLOTDIS0_R(crate::FieldReader); +impl SLOTDIS0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS0` writer - Slot 0 Disabled for this Serializer"] +pub struct SLOTDIS0_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `SLOTDIS1` reader - Slot 1 Disabled for this Serializer"] +pub struct SLOTDIS1_R(crate::FieldReader); +impl SLOTDIS1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS1` writer - Slot 1 Disabled for this Serializer"] +pub struct SLOTDIS1_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `SLOTDIS2` reader - Slot 2 Disabled for this Serializer"] +pub struct SLOTDIS2_R(crate::FieldReader); +impl SLOTDIS2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS2` writer - Slot 2 Disabled for this Serializer"] +pub struct SLOTDIS2_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SLOTDIS3` reader - Slot 3 Disabled for this Serializer"] +pub struct SLOTDIS3_R(crate::FieldReader); +impl SLOTDIS3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS3` writer - Slot 3 Disabled for this Serializer"] +pub struct SLOTDIS3_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SLOTDIS4` reader - Slot 4 Disabled for this Serializer"] +pub struct SLOTDIS4_R(crate::FieldReader); +impl SLOTDIS4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS4` writer - Slot 4 Disabled for this Serializer"] +pub struct SLOTDIS4_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `SLOTDIS5` reader - Slot 5 Disabled for this Serializer"] +pub struct SLOTDIS5_R(crate::FieldReader); +impl SLOTDIS5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS5` writer - Slot 5 Disabled for this Serializer"] +pub struct SLOTDIS5_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `SLOTDIS6` reader - Slot 6 Disabled for this Serializer"] +pub struct SLOTDIS6_R(crate::FieldReader); +impl SLOTDIS6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS6` writer - Slot 6 Disabled for this Serializer"] +pub struct SLOTDIS6_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SLOTDIS7` reader - Slot 7 Disabled for this Serializer"] +pub struct SLOTDIS7_R(crate::FieldReader); +impl SLOTDIS7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS7` writer - Slot 7 Disabled for this Serializer"] +pub struct SLOTDIS7_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Mono Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MONO_A { + #[doc = "0: Normal mode"] + STEREO = 0, + #[doc = "1: Left channel data is duplicated to right channel"] + MONO = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MONO_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MONO` reader - Mono Mode"] +pub struct MONO_R(crate::FieldReader); +impl MONO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MONO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MONO_A { + match self.bits { + false => MONO_A::STEREO, + true => MONO_A::MONO, + } + } + #[doc = "Checks if the value of the field is `STEREO`"] + #[inline(always)] + pub fn is_stereo(&self) -> bool { + **self == MONO_A::STEREO + } + #[doc = "Checks if the value of the field is `MONO`"] + #[inline(always)] + pub fn is_mono(&self) -> bool { + **self == MONO_A::MONO + } +} +impl core::ops::Deref for MONO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONO` writer - Mono Mode"] +pub struct MONO_W<'a> { + w: &'a mut W, +} +impl<'a> MONO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MONO_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Normal mode"] + #[inline(always)] + pub fn stereo(self) -> &'a mut W { + self.variant(MONO_A::STEREO) + } + #[doc = "Left channel data is duplicated to right channel"] + #[inline(always)] + pub fn mono(self) -> &'a mut W { + self.variant(MONO_A::MONO) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Single or Multiple DMA Channels\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DMA_A { + #[doc = "0: Single DMA channel"] + SINGLE = 0, + #[doc = "1: One DMA channel per data channel"] + MULTIPLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA` reader - Single or Multiple DMA Channels"] +pub struct DMA_R(crate::FieldReader); +impl DMA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_A { + match self.bits { + false => DMA_A::SINGLE, + true => DMA_A::MULTIPLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == DMA_A::SINGLE + } + #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[inline(always)] + pub fn is_multiple(&self) -> bool { + **self == DMA_A::MULTIPLE + } +} +impl core::ops::Deref for DMA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMA` writer - Single or Multiple DMA Channels"] +pub struct DMA_W<'a> { + w: &'a mut W, +} +impl<'a> DMA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Single DMA channel"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(DMA_A::SINGLE) + } + #[doc = "One DMA channel per data channel"] + #[inline(always)] + pub fn multiple(self) -> &'a mut W { + self.variant(DMA_A::MULTIPLE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `RXLOOP` reader - Loop-back Test Mode"] +pub struct RXLOOP_R(crate::FieldReader); +impl RXLOOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXLOOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXLOOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXLOOP` writer - Loop-back Test Mode"] +pub struct RXLOOP_W<'a> { + w: &'a mut W, +} +impl<'a> RXLOOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Serializer Mode"] + #[inline(always)] + pub fn sermode(&self) -> SERMODE_R { + SERMODE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Line Default Line when Slot Disabled"] + #[inline(always)] + pub fn txdefault(&self) -> TXDEFAULT_R { + TXDEFAULT_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - Transmit Data when Underrun"] + #[inline(always)] + pub fn txsame(&self) -> TXSAME_R { + TXSAME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Clock Unit Selection"] + #[inline(always)] + pub fn clksel(&self) -> CLKSEL_R { + CLKSEL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Data Slot Formatting Adjust"] + #[inline(always)] + pub fn slotadj(&self) -> SLOTADJ_R { + SLOTADJ_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Data Word Size"] + #[inline(always)] + pub fn datasize(&self) -> DATASIZE_R { + DATASIZE_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Data Word Formatting Adjust"] + #[inline(always)] + pub fn wordadj(&self) -> WORDADJ_R { + WORDADJ_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:14 - Data Formatting Bit Extension"] + #[inline(always)] + pub fn extend(&self) -> EXTEND_R { + EXTEND_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Data Formatting Bit Reverse"] + #[inline(always)] + pub fn bitrev(&self) -> BITREV_R { + BITREV_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Slot 0 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis0(&self) -> SLOTDIS0_R { + SLOTDIS0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Slot 1 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis1(&self) -> SLOTDIS1_R { + SLOTDIS1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Slot 2 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis2(&self) -> SLOTDIS2_R { + SLOTDIS2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Slot 3 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis3(&self) -> SLOTDIS3_R { + SLOTDIS3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Slot 4 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis4(&self) -> SLOTDIS4_R { + SLOTDIS4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Slot 5 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis5(&self) -> SLOTDIS5_R { + SLOTDIS5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Slot 6 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis6(&self) -> SLOTDIS6_R { + SLOTDIS6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slot 7 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis7(&self) -> SLOTDIS7_R { + SLOTDIS7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Mono Mode"] + #[inline(always)] + pub fn mono(&self) -> MONO_R { + MONO_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Single or Multiple DMA Channels"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Loop-back Test Mode"] + #[inline(always)] + pub fn rxloop(&self) -> RXLOOP_R { + RXLOOP_R::new(((self.bits >> 26) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Serializer Mode"] + #[inline(always)] + pub fn sermode(&mut self) -> SERMODE_W { + SERMODE_W { w: self } + } + #[doc = "Bits 2:3 - Line Default Line when Slot Disabled"] + #[inline(always)] + pub fn txdefault(&mut self) -> TXDEFAULT_W { + TXDEFAULT_W { w: self } + } + #[doc = "Bit 4 - Transmit Data when Underrun"] + #[inline(always)] + pub fn txsame(&mut self) -> TXSAME_W { + TXSAME_W { w: self } + } + #[doc = "Bit 5 - Clock Unit Selection"] + #[inline(always)] + pub fn clksel(&mut self) -> CLKSEL_W { + CLKSEL_W { w: self } + } + #[doc = "Bit 7 - Data Slot Formatting Adjust"] + #[inline(always)] + pub fn slotadj(&mut self) -> SLOTADJ_W { + SLOTADJ_W { w: self } + } + #[doc = "Bits 8:10 - Data Word Size"] + #[inline(always)] + pub fn datasize(&mut self) -> DATASIZE_W { + DATASIZE_W { w: self } + } + #[doc = "Bit 12 - Data Word Formatting Adjust"] + #[inline(always)] + pub fn wordadj(&mut self) -> WORDADJ_W { + WORDADJ_W { w: self } + } + #[doc = "Bits 13:14 - Data Formatting Bit Extension"] + #[inline(always)] + pub fn extend(&mut self) -> EXTEND_W { + EXTEND_W { w: self } + } + #[doc = "Bit 15 - Data Formatting Bit Reverse"] + #[inline(always)] + pub fn bitrev(&mut self) -> BITREV_W { + BITREV_W { w: self } + } + #[doc = "Bit 16 - Slot 0 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis0(&mut self) -> SLOTDIS0_W { + SLOTDIS0_W { w: self } + } + #[doc = "Bit 17 - Slot 1 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis1(&mut self) -> SLOTDIS1_W { + SLOTDIS1_W { w: self } + } + #[doc = "Bit 18 - Slot 2 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis2(&mut self) -> SLOTDIS2_W { + SLOTDIS2_W { w: self } + } + #[doc = "Bit 19 - Slot 3 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis3(&mut self) -> SLOTDIS3_W { + SLOTDIS3_W { w: self } + } + #[doc = "Bit 20 - Slot 4 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis4(&mut self) -> SLOTDIS4_W { + SLOTDIS4_W { w: self } + } + #[doc = "Bit 21 - Slot 5 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis5(&mut self) -> SLOTDIS5_W { + SLOTDIS5_W { w: self } + } + #[doc = "Bit 22 - Slot 6 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis6(&mut self) -> SLOTDIS6_W { + SLOTDIS6_W { w: self } + } + #[doc = "Bit 23 - Slot 7 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis7(&mut self) -> SLOTDIS7_W { + SLOTDIS7_W { w: self } + } + #[doc = "Bit 24 - Mono Mode"] + #[inline(always)] + pub fn mono(&mut self) -> MONO_W { + MONO_W { w: self } + } + #[doc = "Bit 25 - Single or Multiple DMA Channels"] + #[inline(always)] + pub fn dma(&mut self) -> DMA_W { + DMA_W { w: self } + } + #[doc = "Bit 26 - Loop-back Test Mode"] + #[inline(always)] + pub fn rxloop(&mut self) -> RXLOOP_W { + RXLOOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Serializer n Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [serctrl](index.html) module"] +pub struct SERCTRL_SPEC; +impl crate::RegisterSpec for SERCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [serctrl::R](R) reader structure"] +impl crate::Readable for SERCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [serctrl::W](W) writer structure"] +impl crate::Writable for SERCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SERCTRL[%s] +to value 0"] +impl crate::Resettable for SERCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/i2s/syncbusy.rs b/pac/atsamda1g/src/i2s/syncbusy.rs new file mode 100644 index 00000000000..46ae5a0c282 --- /dev/null +++ b/pac/atsamda1g/src/i2s/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Status"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN0` reader - Clock Unit 0 Enable Synchronization Status"] +pub struct CKEN0_R(crate::FieldReader); +impl CKEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN1` reader - Clock Unit 1 Enable Synchronization Status"] +pub struct CKEN1_R(crate::FieldReader); +impl CKEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN0` reader - Serializer 0 Enable Synchronization Status"] +pub struct SEREN0_R(crate::FieldReader); +impl SEREN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN1` reader - Serializer 1 Enable Synchronization Status"] +pub struct SEREN1_R(crate::FieldReader); +impl SEREN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA0` reader - Data 0 Synchronization Status"] +pub struct DATA0_R(crate::FieldReader); +impl DATA0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA1` reader - Data 1 Synchronization Status"] +pub struct DATA1_R(crate::FieldReader); +impl DATA1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Status"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Unit 0 Enable Synchronization Status"] + #[inline(always)] + pub fn cken0(&self) -> CKEN0_R { + CKEN0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Unit 1 Enable Synchronization Status"] + #[inline(always)] + pub fn cken1(&self) -> CKEN1_R { + CKEN1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Serializer 0 Enable Synchronization Status"] + #[inline(always)] + pub fn seren0(&self) -> SEREN0_R { + SEREN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Serializer 1 Enable Synchronization Status"] + #[inline(always)] + pub fn seren1(&self) -> SEREN1_R { + SEREN1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Data 0 Synchronization Status"] + #[inline(always)] + pub fn data0(&self) -> DATA0_R { + DATA0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Data 1 Synchronization Status"] + #[inline(always)] + pub fn data1(&self) -> DATA1_R { + DATA1_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/lib.rs b/pac/atsamda1g/src/lib.rs new file mode 100644 index 00000000000..21fc97ef946 --- /dev/null +++ b/pac/atsamda1g/src/lib.rs @@ -0,0 +1,1452 @@ +#![doc = "Peripheral access API for ATSAMDA1G microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn PM(); + fn SYSCTRL(); + fn WDT(); + fn RTC(); + fn EIC(); + fn NVMCTRL(); + fn DMAC(); + fn USB(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn SERCOM4(); + fn SERCOM5(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC3(); + fn TC4(); + fn TC5(); + fn TC6(); + fn TC7(); + fn ADC(); + fn AC(); + fn DAC(); + fn PTC(); + fn I2S(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 28] = [ + Vector { _handler: PM }, + Vector { _handler: SYSCTRL }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: USB }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _handler: SERCOM4 }, + Vector { _handler: SERCOM5 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: TC5 }, + Vector { _handler: TC6 }, + Vector { _handler: TC7 }, + Vector { _handler: ADC }, + Vector { _handler: AC }, + Vector { _handler: DAC }, + Vector { _handler: PTC }, + Vector { _handler: I2S }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - PM"] + PM = 0, + #[doc = "1 - SYSCTRL"] + SYSCTRL = 1, + #[doc = "2 - WDT"] + WDT = 2, + #[doc = "3 - RTC"] + RTC = 3, + #[doc = "4 - EIC"] + EIC = 4, + #[doc = "5 - NVMCTRL"] + NVMCTRL = 5, + #[doc = "6 - DMAC"] + DMAC = 6, + #[doc = "7 - USB"] + USB = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "13 - SERCOM4"] + SERCOM4 = 13, + #[doc = "14 - SERCOM5"] + SERCOM5 = 14, + #[doc = "15 - TCC0"] + TCC0 = 15, + #[doc = "16 - TCC1"] + TCC1 = 16, + #[doc = "17 - TCC2"] + TCC2 = 17, + #[doc = "18 - TC3"] + TC3 = 18, + #[doc = "19 - TC4"] + TC4 = 19, + #[doc = "20 - TC5"] + TC5 = 20, + #[doc = "21 - TC6"] + TC6 = 21, + #[doc = "22 - TC7"] + TC7 = 22, + #[doc = "23 - ADC"] + ADC = 23, + #[doc = "24 - AC"] + AC = 24, + #[doc = "25 - DAC"] + DAC = 25, + #[doc = "26 - PTC"] + PTC = 26, + #[doc = "27 - I2S"] + I2S = 27, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc; +#[doc = "Digital Analog Converter"] +pub struct DAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC {} +impl DAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC { + type Target = dac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC").finish() + } +} +#[doc = "Digital Analog Converter"] +pub mod dac; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct SBMATRIX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SBMATRIX {} +impl SBMATRIX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sbmatrix::RegisterBlock = 0x4100_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sbmatrix::RegisterBlock { + Self::PTR + } +} +impl Deref for SBMATRIX { + type Target = sbmatrix::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SBMATRIX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SBMATRIX").finish() + } +} +#[doc = "HSB Matrix"] +pub mod sbmatrix; +#[doc = "Inter-IC Sound Interface"] +pub struct I2S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S {} +impl I2S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s::RegisterBlock { + Self::PTR + } +} +impl Deref for I2S { + type Target = i2s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S").finish() + } +} +#[doc = "Inter-IC Sound Interface"] +pub mod i2s; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC0 {} +impl PAC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC0 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC0").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac0; +#[doc = "Peripheral Access Controller"] +pub struct PAC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC1 {} +impl PAC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC1 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC1").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub use pac0 as pac1; +#[doc = "Peripheral Access Controller"] +pub struct PAC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC2 {} +impl PAC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC2 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC2").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub use pac0 as pac2; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Serial Communication Interface"] +pub struct SERCOM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM4 {} +impl SERCOM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM4 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM4").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom4; +#[doc = "Serial Communication Interface"] +pub struct SERCOM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM5 {} +impl SERCOM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM5 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM5").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom5; +#[doc = "System Control"] +pub struct SYSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCTRL {} +impl SYSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysctrl::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSCTRL { + type Target = sysctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSCTRL").finish() + } +} +#[doc = "System Control"] +pub mod sysctrl; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc4; +#[doc = "Basic Timer Counter"] +pub struct TC5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC5 {} +impl TC5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC5 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC5").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc5; +#[doc = "Basic Timer Counter"] +pub struct TC6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC6 {} +impl TC6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC6 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC6").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc6; +#[doc = "Basic Timer Counter"] +pub struct TC7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC7 {} +impl TC7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC7 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC7").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc7; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Universal Serial Bus"] +pub struct USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB {} +impl USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb::RegisterBlock = 0x4100_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb::RegisterBlock { + Self::PTR + } +} +impl Deref for USB { + type Target = usb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB").finish() + } +} +#[doc = "Universal Serial Bus"] +pub mod usb; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "DAC"] + pub DAC: DAC, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "SBMATRIX"] + pub SBMATRIX: SBMATRIX, + #[doc = "I2S"] + pub I2S: I2S, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "PAC0"] + pub PAC0: PAC0, + #[doc = "PAC1"] + pub PAC1: PAC1, + #[doc = "PAC2"] + pub PAC2: PAC2, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SERCOM4"] + pub SERCOM4: SERCOM4, + #[doc = "SERCOM5"] + pub SERCOM5: SERCOM5, + #[doc = "SYSCTRL"] + pub SYSCTRL: SYSCTRL, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TC5"] + pub TC5: TC5, + #[doc = "TC6"] + pub TC6: TC6, + #[doc = "TC7"] + pub TC7: TC7, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "USB"] + pub USB: USB, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC: ADC { + _marker: PhantomData, + }, + DAC: DAC { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + SBMATRIX: SBMATRIX { + _marker: PhantomData, + }, + I2S: I2S { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + PAC0: PAC0 { + _marker: PhantomData, + }, + PAC1: PAC1 { + _marker: PhantomData, + }, + PAC2: PAC2 { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SERCOM4: SERCOM4 { + _marker: PhantomData, + }, + SERCOM5: SERCOM5 { + _marker: PhantomData, + }, + SYSCTRL: SYSCTRL { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TC5: TC5 { + _marker: PhantomData, + }, + TC6: TC6 { + _marker: PhantomData, + }, + TC7: TC7 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + USB: USB { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamda1g/src/mtb.rs b/pac/atsamda1g/src/mtb.rs new file mode 100644 index 00000000000..45d81bbf944 --- /dev/null +++ b/pac/atsamda1g/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - CoreSight"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - CoreSight"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - CoreSight"] + pub pid6: crate::Reg, + #[doc = "0xfdc - CoreSight"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - CoreSight"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - CoreSight"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - CoreSight"] + pub pid2: crate::Reg, + #[doc = "0xfec - CoreSight"] + pub pid3: crate::Reg, + #[doc = "0xff0 - CoreSight"] + pub cid0: crate::Reg, + #[doc = "0xff4 - CoreSight"] + pub cid1: crate::Reg, + #[doc = "0xff8 - CoreSight"] + pub cid2: crate::Reg, + #[doc = "0xffc - CoreSight"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid3; diff --git a/pac/atsamda1g/src/mtb/authstatus.rs b/pac/atsamda1g/src/mtb/authstatus.rs new file mode 100644 index 00000000000..6fe441e0554 --- /dev/null +++ b/pac/atsamda1g/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/base.rs b/pac/atsamda1g/src/mtb/base.rs new file mode 100644 index 00000000000..f59b5a97a39 --- /dev/null +++ b/pac/atsamda1g/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/cid0.rs b/pac/atsamda1g/src/mtb/cid0.rs new file mode 100644 index 00000000000..c4b0c0a2f5e --- /dev/null +++ b/pac/atsamda1g/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/cid1.rs b/pac/atsamda1g/src/mtb/cid1.rs new file mode 100644 index 00000000000..628785fae59 --- /dev/null +++ b/pac/atsamda1g/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/cid2.rs b/pac/atsamda1g/src/mtb/cid2.rs new file mode 100644 index 00000000000..cf5be1dab2f --- /dev/null +++ b/pac/atsamda1g/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/cid3.rs b/pac/atsamda1g/src/mtb/cid3.rs new file mode 100644 index 00000000000..f8d299b02a6 --- /dev/null +++ b/pac/atsamda1g/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/claimclr.rs b/pac/atsamda1g/src/mtb/claimclr.rs new file mode 100644 index 00000000000..7d0fa5d487b --- /dev/null +++ b/pac/atsamda1g/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/claimset.rs b/pac/atsamda1g/src/mtb/claimset.rs new file mode 100644 index 00000000000..d5e8ffaa484 --- /dev/null +++ b/pac/atsamda1g/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/devarch.rs b/pac/atsamda1g/src/mtb/devarch.rs new file mode 100644 index 00000000000..b79480753d5 --- /dev/null +++ b/pac/atsamda1g/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/devid.rs b/pac/atsamda1g/src/mtb/devid.rs new file mode 100644 index 00000000000..21c15d95203 --- /dev/null +++ b/pac/atsamda1g/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/devtype.rs b/pac/atsamda1g/src/mtb/devtype.rs new file mode 100644 index 00000000000..c00d66b98a2 --- /dev/null +++ b/pac/atsamda1g/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/flow.rs b/pac/atsamda1g/src/mtb/flow.rs new file mode 100644 index 00000000000..1b94efdb89b --- /dev/null +++ b/pac/atsamda1g/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/itctrl.rs b/pac/atsamda1g/src/mtb/itctrl.rs new file mode 100644 index 00000000000..a48364e0b06 --- /dev/null +++ b/pac/atsamda1g/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/lockaccess.rs b/pac/atsamda1g/src/mtb/lockaccess.rs new file mode 100644 index 00000000000..0400690bead --- /dev/null +++ b/pac/atsamda1g/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/lockstatus.rs b/pac/atsamda1g/src/mtb/lockstatus.rs new file mode 100644 index 00000000000..0c68410c694 --- /dev/null +++ b/pac/atsamda1g/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/master.rs b/pac/atsamda1g/src/mtb/master.rs new file mode 100644 index 00000000000..0190ca1ce90 --- /dev/null +++ b/pac/atsamda1g/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid0.rs b/pac/atsamda1g/src/mtb/pid0.rs new file mode 100644 index 00000000000..a4daa474849 --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid1.rs b/pac/atsamda1g/src/mtb/pid1.rs new file mode 100644 index 00000000000..37353582c84 --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid2.rs b/pac/atsamda1g/src/mtb/pid2.rs new file mode 100644 index 00000000000..c4e6a4b9c2a --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid3.rs b/pac/atsamda1g/src/mtb/pid3.rs new file mode 100644 index 00000000000..be0caeaeb51 --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid4.rs b/pac/atsamda1g/src/mtb/pid4.rs new file mode 100644 index 00000000000..83e65c1f64f --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid5.rs b/pac/atsamda1g/src/mtb/pid5.rs new file mode 100644 index 00000000000..eeffcc6e22a --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid6.rs b/pac/atsamda1g/src/mtb/pid6.rs new file mode 100644 index 00000000000..c3a4bdcb875 --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/pid7.rs b/pac/atsamda1g/src/mtb/pid7.rs new file mode 100644 index 00000000000..c47e91f7717 --- /dev/null +++ b/pac/atsamda1g/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/mtb/position.rs b/pac/atsamda1g/src/mtb/position.rs new file mode 100644 index 00000000000..4bab0425b14 --- /dev/null +++ b/pac/atsamda1g/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl.rs b/pac/atsamda1g/src/nvmctrl.rs new file mode 100644 index 00000000000..0c4b2717337 --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl.rs @@ -0,0 +1,63 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; diff --git a/pac/atsamda1g/src/nvmctrl/addr.rs b/pac/atsamda1g/src/nvmctrl/addr.rs new file mode 100644 index 00000000000..74ed27736da --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/ctrla.rs b/pac/atsamda1g/src/nvmctrl/ctrla.rs new file mode 100644 index 00000000000..89f175771e4 --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/ctrlb.rs b/pac/atsamda1g/src/nvmctrl/ctrlb.rs new file mode 100644 index 00000000000..169445752da --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/ctrlb.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/intenclr.rs b/pac/atsamda1g/src/nvmctrl/intenclr.rs new file mode 100644 index 00000000000..6e7db4b52c9 --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/intenset.rs b/pac/atsamda1g/src/nvmctrl/intenset.rs new file mode 100644 index 00000000000..ba8698e86c3 --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/intflag.rs b/pac/atsamda1g/src/nvmctrl/intflag.rs new file mode 100644 index 00000000000..1b30cdddf25 --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/lock.rs b/pac/atsamda1g/src/nvmctrl/lock.rs new file mode 100644 index 00000000000..dbcf37a8107 --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/param.rs b/pac/atsamda1g/src/nvmctrl/param.rs new file mode 100644 index 00000000000..d9197cf16de --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/nvmctrl/status.rs b/pac/atsamda1g/src/nvmctrl/status.rs new file mode 100644 index 00000000000..ce849015560 --- /dev/null +++ b/pac/atsamda1g/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pac0.rs b/pac/atsamda1g/src/pac0.rs new file mode 100644 index 00000000000..e6ae6be9ca4 --- /dev/null +++ b/pac/atsamda1g/src/pac0.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write Protection Clear"] + pub wpclr: crate::Reg, + #[doc = "0x04 - Write Protection Set"] + pub wpset: crate::Reg, +} +#[doc = "WPCLR register accessor: an alias for `Reg`"] +pub type WPCLR = crate::Reg; +#[doc = "Write Protection Clear"] +pub mod wpclr; +#[doc = "WPSET register accessor: an alias for `Reg`"] +pub type WPSET = crate::Reg; +#[doc = "Write Protection Set"] +pub mod wpset; diff --git a/pac/atsamda1g/src/pac0/wpclr.rs b/pac/atsamda1g/src/pac0/wpclr.rs new file mode 100644 index 00000000000..e6bb7309f42 --- /dev/null +++ b/pac/atsamda1g/src/pac0/wpclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WPCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WPCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WP` reader - Write Protection Clear"] +pub struct WP_R(crate::FieldReader); +impl WP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WP` writer - Write Protection Clear"] +pub struct WP_W<'a> { + w: &'a mut W, +} +impl<'a> WP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff_ffff << 1)) | ((value as u32 & 0x7fff_ffff) << 1); + self.w + } +} +impl R { + #[doc = "Bits 1:31 - Write Protection Clear"] + #[inline(always)] + pub fn wp(&self) -> WP_R { + WP_R::new(((self.bits >> 1) & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 1:31 - Write Protection Clear"] + #[inline(always)] + pub fn wp(&mut self) -> WP_W { + WP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Protection Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpclr](index.html) module"] +pub struct WPCLR_SPEC; +impl crate::RegisterSpec for WPCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wpclr::R](R) reader structure"] +impl crate::Readable for WPCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wpclr::W](W) writer structure"] +impl crate::Writable for WPCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WPCLR to value 0"] +impl crate::Resettable for WPCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pac0/wpset.rs b/pac/atsamda1g/src/pac0/wpset.rs new file mode 100644 index 00000000000..5a85aae2aad --- /dev/null +++ b/pac/atsamda1g/src/pac0/wpset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WPSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WPSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WP` reader - Write Protection Set"] +pub struct WP_R(crate::FieldReader); +impl WP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WP` writer - Write Protection Set"] +pub struct WP_W<'a> { + w: &'a mut W, +} +impl<'a> WP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff_ffff << 1)) | ((value as u32 & 0x7fff_ffff) << 1); + self.w + } +} +impl R { + #[doc = "Bits 1:31 - Write Protection Set"] + #[inline(always)] + pub fn wp(&self) -> WP_R { + WP_R::new(((self.bits >> 1) & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 1:31 - Write Protection Set"] + #[inline(always)] + pub fn wp(&mut self) -> WP_W { + WP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Protection Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpset](index.html) module"] +pub struct WPSET_SPEC; +impl crate::RegisterSpec for WPSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wpset::R](R) reader structure"] +impl crate::Readable for WPSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wpset::W](W) writer structure"] +impl crate::Writable for WPSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WPSET to value 0"] +impl crate::Resettable for WPSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm.rs b/pac/atsamda1g/src/pm.rs new file mode 100644 index 00000000000..2a5e9b74e89 --- /dev/null +++ b/pac/atsamda1g/src/pm.rs @@ -0,0 +1,98 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Sleep Mode"] + pub sleep: crate::Reg, + #[doc = "0x02 - External Reset Controller"] + pub extctrl: crate::Reg, + _reserved3: [u8; 0x05], + #[doc = "0x08 - CPU Clock Select"] + pub cpusel: crate::Reg, + #[doc = "0x09 - APBA Clock Select"] + pub apbasel: crate::Reg, + #[doc = "0x0a - APBB Clock Select"] + pub apbbsel: crate::Reg, + #[doc = "0x0b - APBC Clock Select"] + pub apbcsel: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0x14 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x18 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x1c - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x20 - APBC Mask"] + pub apbcmask: crate::Reg, + _reserved11: [u8; 0x10], + #[doc = "0x34 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x35 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x36 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved14: [u8; 0x01], + #[doc = "0x38 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SLEEP register accessor: an alias for `Reg`"] +pub type SLEEP = crate::Reg; +#[doc = "Sleep Mode"] +pub mod sleep; +#[doc = "EXTCTRL register accessor: an alias for `Reg`"] +pub type EXTCTRL = crate::Reg; +#[doc = "External Reset Controller"] +pub mod extctrl; +#[doc = "CPUSEL register accessor: an alias for `Reg`"] +pub type CPUSEL = crate::Reg; +#[doc = "CPU Clock Select"] +pub mod cpusel; +#[doc = "APBASEL register accessor: an alias for `Reg`"] +pub type APBASEL = crate::Reg; +#[doc = "APBA Clock Select"] +pub mod apbasel; +#[doc = "APBBSEL register accessor: an alias for `Reg`"] +pub type APBBSEL = crate::Reg; +#[doc = "APBB Clock Select"] +pub mod apbbsel; +#[doc = "APBCSEL register accessor: an alias for `Reg`"] +pub type APBCSEL = crate::Reg; +#[doc = "APBC Clock Select"] +pub mod apbcsel; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamda1g/src/pm/ahbmask.rs b/pac/atsamda1g/src/pm/ahbmask.rs new file mode 100644 index 00000000000..4a45a8dcdd6 --- /dev/null +++ b/pac/atsamda1g/src/pm/ahbmask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `USB_` reader - USB AHB Clock Mask"] +pub struct USB__R(crate::FieldReader); +impl USB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USB_` writer - USB AHB Clock Mask"] +pub struct USB__W<'a> { + w: &'a mut W, +} +impl<'a> USB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - USB AHB Clock Mask"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 6 - USB AHB Clock Mask"] + #[inline(always)] + pub fn usb_(&mut self) -> USB__W { + USB__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x7f"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1g/src/pm/apbamask.rs b/pac/atsamda1g/src/pm/apbamask.rs new file mode 100644 index 00000000000..857ab4989c6 --- /dev/null +++ b/pac/atsamda1g/src/pm/apbamask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC0_` reader - PAC0 APB Clock Enable"] +pub struct PAC0__R(crate::FieldReader); +impl PAC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC0_` writer - PAC0 APB Clock Enable"] +pub struct PAC0__W<'a> { + w: &'a mut W, +} +impl<'a> PAC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYSCTRL_` reader - SYSCTRL APB Clock Enable"] +pub struct SYSCTRL__R(crate::FieldReader); +impl SYSCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSCTRL_` writer - SYSCTRL APB Clock Enable"] +pub struct SYSCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> SYSCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC0 APB Clock Enable"] + #[inline(always)] + pub fn pac0_(&self) -> PAC0__R { + PAC0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SYSCTRL APB Clock Enable"] + #[inline(always)] + pub fn sysctrl_(&self) -> SYSCTRL__R { + SYSCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC0 APB Clock Enable"] + #[inline(always)] + pub fn pac0_(&mut self) -> PAC0__W { + PAC0__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - SYSCTRL APB Clock Enable"] + #[inline(always)] + pub fn sysctrl_(&mut self) -> SYSCTRL__W { + SYSCTRL__W { w: self } + } + #[doc = "Bit 3 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 4 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 5 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 6 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x7f"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1g/src/pm/apbasel.rs b/pac/atsamda1g/src/pm/apbasel.rs new file mode 100644 index 00000000000..494b59e7e3a --- /dev/null +++ b/pac/atsamda1g/src/pm/apbasel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBASEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBASEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBA Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBADIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBADIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBADIV` reader - APBA Prescaler Selection"] +pub struct APBADIV_R(crate::FieldReader); +impl APBADIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBADIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBADIV_A { + match self.bits { + 0 => APBADIV_A::DIV1, + 1 => APBADIV_A::DIV2, + 2 => APBADIV_A::DIV4, + 3 => APBADIV_A::DIV8, + 4 => APBADIV_A::DIV16, + 5 => APBADIV_A::DIV32, + 6 => APBADIV_A::DIV64, + 7 => APBADIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBADIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBADIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBADIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBADIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBADIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBADIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBADIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBADIV_A::DIV128 + } +} +impl core::ops::Deref for APBADIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBADIV` writer - APBA Prescaler Selection"] +pub struct APBADIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBADIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBADIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBADIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBADIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBADIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBADIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBADIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBADIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBADIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBADIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBA Prescaler Selection"] + #[inline(always)] + pub fn apbadiv(&self) -> APBADIV_R { + APBADIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBA Prescaler Selection"] + #[inline(always)] + pub fn apbadiv(&mut self) -> APBADIV_W { + APBADIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbasel](index.html) module"] +pub struct APBASEL_SPEC; +impl crate::RegisterSpec for APBASEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbasel::R](R) reader structure"] +impl crate::Readable for APBASEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbasel::W](W) writer structure"] +impl crate::Writable for APBASEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBASEL to value 0"] +impl crate::Resettable for APBASEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/apbbmask.rs b/pac/atsamda1g/src/pm/apbbmask.rs new file mode 100644 index 00000000000..92e2c404c22 --- /dev/null +++ b/pac/atsamda1g/src/pm/apbbmask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC1_` reader - PAC1 APB Clock Enable"] +pub struct PAC1__R(crate::FieldReader); +impl PAC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC1_` writer - PAC1 APB Clock Enable"] +pub struct PAC1__W<'a> { + w: &'a mut W, +} +impl<'a> PAC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Clock Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC APB Clock Enable"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `USB_` reader - USB APB Clock Enable"] +pub struct USB__R(crate::FieldReader); +impl USB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USB_` writer - USB APB Clock Enable"] +pub struct USB__W<'a> { + w: &'a mut W, +} +impl<'a> USB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HMATRIX_` reader - HMATRIX APB Clock Enable"] +pub struct HMATRIX__R(crate::FieldReader); +impl HMATRIX__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIX__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIX__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIX_` writer - HMATRIX APB Clock Enable"] +pub struct HMATRIX__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIX__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC1 APB Clock Enable"] + #[inline(always)] + pub fn pac1_(&self) -> PAC1__R { + PAC1__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DMAC APB Clock Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - USB APB Clock Enable"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HMATRIX APB Clock Enable"] + #[inline(always)] + pub fn hmatrix_(&self) -> HMATRIX__R { + HMATRIX__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC1 APB Clock Enable"] + #[inline(always)] + pub fn pac1_(&mut self) -> PAC1__W { + PAC1__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 4 - DMAC APB Clock Enable"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 5 - USB APB Clock Enable"] + #[inline(always)] + pub fn usb_(&mut self) -> USB__W { + USB__W { w: self } + } + #[doc = "Bit 6 - HMATRIX APB Clock Enable"] + #[inline(always)] + pub fn hmatrix_(&mut self) -> HMATRIX__W { + HMATRIX__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x7f"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1g/src/pm/apbbsel.rs b/pac/atsamda1g/src/pm/apbbsel.rs new file mode 100644 index 00000000000..a935873b629 --- /dev/null +++ b/pac/atsamda1g/src/pm/apbbsel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBBSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBB Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBBDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBBDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBBDIV` reader - APBB Prescaler Selection"] +pub struct APBBDIV_R(crate::FieldReader); +impl APBBDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBBDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBBDIV_A { + match self.bits { + 0 => APBBDIV_A::DIV1, + 1 => APBBDIV_A::DIV2, + 2 => APBBDIV_A::DIV4, + 3 => APBBDIV_A::DIV8, + 4 => APBBDIV_A::DIV16, + 5 => APBBDIV_A::DIV32, + 6 => APBBDIV_A::DIV64, + 7 => APBBDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBBDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBBDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBBDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBBDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBBDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBBDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBBDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBBDIV_A::DIV128 + } +} +impl core::ops::Deref for APBBDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBBDIV` writer - APBB Prescaler Selection"] +pub struct APBBDIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBBDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBBDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBB Prescaler Selection"] + #[inline(always)] + pub fn apbbdiv(&self) -> APBBDIV_R { + APBBDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBB Prescaler Selection"] + #[inline(always)] + pub fn apbbdiv(&mut self) -> APBBDIV_W { + APBBDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbsel](index.html) module"] +pub struct APBBSEL_SPEC; +impl crate::RegisterSpec for APBBSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbbsel::R](R) reader structure"] +impl crate::Readable for APBBSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbsel::W](W) writer structure"] +impl crate::Writable for APBBSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBSEL to value 0"] +impl crate::Resettable for APBBSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/apbcmask.rs b/pac/atsamda1g/src/pm/apbcmask.rs new file mode 100644 index 00000000000..78a1439181f --- /dev/null +++ b/pac/atsamda1g/src/pm/apbcmask.rs @@ -0,0 +1,1053 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC2_` reader - PAC2 APB Clock Enable"] +pub struct PAC2__R(crate::FieldReader); +impl PAC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC2_` writer - PAC2 APB Clock Enable"] +pub struct PAC2__W<'a> { + w: &'a mut W, +} +impl<'a> PAC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5 APB Clock Enable"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5 APB Clock Enable"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6 APB Clock Enable"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6 APB Clock Enable"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7 APB Clock Enable"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7 APB Clock Enable"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADC_` reader - ADC APB Clock Enable"] +pub struct ADC__R(crate::FieldReader); +impl ADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_` writer - ADC APB Clock Enable"] +pub struct ADC__W<'a> { + w: &'a mut W, +} +impl<'a> ADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `I2S_` reader - I2S APB Clock Enable"] +pub struct I2S__R(crate::FieldReader); +impl I2S__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2S__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2S__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2S_` writer - I2S APB Clock Enable"] +pub struct I2S__W<'a> { + w: &'a mut W, +} +impl<'a> I2S__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC2 APB Clock Enable"] + #[inline(always)] + pub fn pac2_(&self) -> PAC2__R { + PAC2__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - ADC APB Clock Enable"] + #[inline(always)] + pub fn adc_(&self) -> ADC__R { + ADC__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - I2S APB Clock Enable"] + #[inline(always)] + pub fn i2s_(&self) -> I2S__R { + I2S__R::new(((self.bits >> 20) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC2 APB Clock Enable"] + #[inline(always)] + pub fn pac2_(&mut self) -> PAC2__W { + PAC2__W { w: self } + } + #[doc = "Bit 1 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 2 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 3 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 4 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 5 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 6 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 7 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 8 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 9 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 10 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 12 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 13 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 14 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 15 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Bit 16 - ADC APB Clock Enable"] + #[inline(always)] + pub fn adc_(&mut self) -> ADC__W { + ADC__W { w: self } + } + #[doc = "Bit 17 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 18 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 19 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 20 - I2S APB Clock Enable"] + #[inline(always)] + pub fn i2s_(&mut self) -> I2S__W { + I2S__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0x0001_0000"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0001_0000 + } +} diff --git a/pac/atsamda1g/src/pm/apbcsel.rs b/pac/atsamda1g/src/pm/apbcsel.rs new file mode 100644 index 00000000000..7669148bc17 --- /dev/null +++ b/pac/atsamda1g/src/pm/apbcsel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBCSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBC Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBCDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBCDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBCDIV` reader - APBC Prescaler Selection"] +pub struct APBCDIV_R(crate::FieldReader); +impl APBCDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBCDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBCDIV_A { + match self.bits { + 0 => APBCDIV_A::DIV1, + 1 => APBCDIV_A::DIV2, + 2 => APBCDIV_A::DIV4, + 3 => APBCDIV_A::DIV8, + 4 => APBCDIV_A::DIV16, + 5 => APBCDIV_A::DIV32, + 6 => APBCDIV_A::DIV64, + 7 => APBCDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBCDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBCDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBCDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBCDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBCDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBCDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBCDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBCDIV_A::DIV128 + } +} +impl core::ops::Deref for APBCDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBCDIV` writer - APBC Prescaler Selection"] +pub struct APBCDIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBCDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBCDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBC Prescaler Selection"] + #[inline(always)] + pub fn apbcdiv(&self) -> APBCDIV_R { + APBCDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBC Prescaler Selection"] + #[inline(always)] + pub fn apbcdiv(&mut self) -> APBCDIV_W { + APBCDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcsel](index.html) module"] +pub struct APBCSEL_SPEC; +impl crate::RegisterSpec for APBCSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbcsel::R](R) reader structure"] +impl crate::Readable for APBCSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcsel::W](W) writer structure"] +impl crate::Writable for APBCSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCSEL to value 0"] +impl crate::Resettable for APBCSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/cpusel.rs b/pac/atsamda1g/src/pm/cpusel.rs new file mode 100644 index 00000000000..5637b22ba7a --- /dev/null +++ b/pac/atsamda1g/src/pm/cpusel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Prescaler Selection"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPUDIV_A { + match self.bits { + 0 => CPUDIV_A::DIV1, + 1 => CPUDIV_A::DIV2, + 2 => CPUDIV_A::DIV4, + 3 => CPUDIV_A::DIV8, + 4 => CPUDIV_A::DIV16, + 5 => CPUDIV_A::DIV32, + 6 => CPUDIV_A::DIV64, + 7 => CPUDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Prescaler Selection"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - CPU Prescaler Selection"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - CPU Prescaler Selection"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpusel](index.html) module"] +pub struct CPUSEL_SPEC; +impl crate::RegisterSpec for CPUSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpusel::R](R) reader structure"] +impl crate::Readable for CPUSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpusel::W](W) writer structure"] +impl crate::Writable for CPUSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUSEL to value 0"] +impl crate::Resettable for CPUSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/ctrl.rs b/pac/atsamda1g/src/pm/ctrl.rs new file mode 100644 index 00000000000..bde0e70a237 --- /dev/null +++ b/pac/atsamda1g/src/pm/ctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/extctrl.rs b/pac/atsamda1g/src/pm/extctrl.rs new file mode 100644 index 00000000000..c4f97eedac5 --- /dev/null +++ b/pac/atsamda1g/src/pm/extctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EXTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SETDIS` reader - External Reset Disable"] +pub struct SETDIS_R(crate::FieldReader); +impl SETDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SETDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SETDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SETDIS` writer - External Reset Disable"] +pub struct SETDIS_W<'a> { + w: &'a mut W, +} +impl<'a> SETDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Reset Disable"] + #[inline(always)] + pub fn setdis(&self) -> SETDIS_R { + SETDIS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Reset Disable"] + #[inline(always)] + pub fn setdis(&mut self) -> SETDIS_W { + SETDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Reset Controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extctrl](index.html) module"] +pub struct EXTCTRL_SPEC; +impl crate::RegisterSpec for EXTCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [extctrl::R](R) reader structure"] +impl crate::Readable for EXTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [extctrl::W](W) writer structure"] +impl crate::Writable for EXTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EXTCTRL to value 0"] +impl crate::Resettable for EXTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/intenclr.rs b/pac/atsamda1g/src/pm/intenclr.rs new file mode 100644 index 00000000000..14feb632dbb --- /dev/null +++ b/pac/atsamda1g/src/pm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/intenset.rs b/pac/atsamda1g/src/pm/intenset.rs new file mode 100644 index 00000000000..f01fcc316d9 --- /dev/null +++ b/pac/atsamda1g/src/pm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/intflag.rs b/pac/atsamda1g/src/pm/intflag.rs new file mode 100644 index 00000000000..b5294af3d9d --- /dev/null +++ b/pac/atsamda1g/src/pm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/pm/rcause.rs b/pac/atsamda1g/src/pm/rcause.rs new file mode 100644 index 00000000000..dd192bbc19a --- /dev/null +++ b/pac/atsamda1g/src/pm/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD12` reader - Brown Out 12 Detector Reset"] +pub struct BOD12_R(crate::FieldReader); +impl BOD12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33` reader - Brown Out 33 Detector Reset"] +pub struct BOD33_R(crate::FieldReader); +impl BOD33_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out 12 Detector Reset"] + #[inline(always)] + pub fn bod12(&self) -> BOD12_R { + BOD12_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out 33 Detector Reset"] + #[inline(always)] + pub fn bod33(&self) -> BOD33_R { + BOD33_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0x01"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1g/src/pm/sleep.rs b/pac/atsamda1g/src/pm/sleep.rs new file mode 100644 index 00000000000..c30b443bde1 --- /dev/null +++ b/pac/atsamda1g/src/pm/sleep.rs @@ -0,0 +1,165 @@ +#[doc = "Register `SLEEP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Idle Mode Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDLE_A { + #[doc = "0: The CPU clock domain is stopped"] + CPU = 0, + #[doc = "1: The CPU and AHB clock domains are stopped"] + AHB = 1, + #[doc = "2: The CPU, AHB and APB clock domains are stopped"] + APB = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDLE_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDLE` reader - Idle Mode Configuration"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(IDLE_A::CPU), + 1 => Some(IDLE_A::AHB), + 2 => Some(IDLE_A::APB), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CPU`"] + #[inline(always)] + pub fn is_cpu(&self) -> bool { + **self == IDLE_A::CPU + } + #[doc = "Checks if the value of the field is `AHB`"] + #[inline(always)] + pub fn is_ahb(&self) -> bool { + **self == IDLE_A::AHB + } + #[doc = "Checks if the value of the field is `APB`"] + #[inline(always)] + pub fn is_apb(&self) -> bool { + **self == IDLE_A::APB + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` writer - Idle Mode Configuration"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDLE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The CPU clock domain is stopped"] + #[inline(always)] + pub fn cpu(self) -> &'a mut W { + self.variant(IDLE_A::CPU) + } + #[doc = "The CPU and AHB clock domains are stopped"] + #[inline(always)] + pub fn ahb(self) -> &'a mut W { + self.variant(IDLE_A::AHB) + } + #[doc = "The CPU, AHB and APB clock domains are stopped"] + #[inline(always)] + pub fn apb(self) -> &'a mut W { + self.variant(IDLE_A::APB) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Idle Mode Configuration"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Idle Mode Configuration"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleep](index.html) module"] +pub struct SLEEP_SPEC; +impl crate::RegisterSpec for SLEEP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleep::R](R) reader structure"] +impl crate::Readable for SLEEP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleep::W](W) writer structure"] +impl crate::Writable for SLEEP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEP to value 0"] +impl crate::Resettable for SLEEP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port.rs b/pac/atsamda1g/src/port.rs new file mode 100644 index 00000000000..cd5062cacbd --- /dev/null +++ b/pac/atsamda1g/src/port.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + _reserved11: [u8; 0x04], + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamda1g/src/port/group.rs b/pac/atsamda1g/src/port/group.rs new file mode 100644 index 00000000000..42529765a8d --- /dev/null +++ b/pac/atsamda1g/src/port/group.rs @@ -0,0 +1,52 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamda1g/src/port/group/ctrl.rs b/pac/atsamda1g/src/port/group/ctrl.rs new file mode 100644 index 00000000000..4b57cd6fcd2 --- /dev/null +++ b/pac/atsamda1g/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/dir.rs b/pac/atsamda1g/src/port/group/dir.rs new file mode 100644 index 00000000000..36f642e3c16 --- /dev/null +++ b/pac/atsamda1g/src/port/group/dir.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Port Data Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Port Data Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/dirclr.rs b/pac/atsamda1g/src/port/group/dirclr.rs new file mode 100644 index 00000000000..9d125c964aa --- /dev/null +++ b/pac/atsamda1g/src/port/group/dirclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRCLR` reader - Port Data Direction Clear"] +pub struct DIRCLR_R(crate::FieldReader); +impl DIRCLR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRCLR` writer - Port Data Direction Clear"] +pub struct DIRCLR_W<'a> { + w: &'a mut W, +} +impl<'a> DIRCLR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Clear"] + #[inline(always)] + pub fn dirclr(&self) -> DIRCLR_R { + DIRCLR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Clear"] + #[inline(always)] + pub fn dirclr(&mut self) -> DIRCLR_W { + DIRCLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/dirset.rs b/pac/atsamda1g/src/port/group/dirset.rs new file mode 100644 index 00000000000..f0a4679db6b --- /dev/null +++ b/pac/atsamda1g/src/port/group/dirset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRSET` reader - Port Data Direction Set"] +pub struct DIRSET_R(crate::FieldReader); +impl DIRSET_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRSET` writer - Port Data Direction Set"] +pub struct DIRSET_W<'a> { + w: &'a mut W, +} +impl<'a> DIRSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Set"] + #[inline(always)] + pub fn dirset(&self) -> DIRSET_R { + DIRSET_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Set"] + #[inline(always)] + pub fn dirset(&mut self) -> DIRSET_W { + DIRSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/dirtgl.rs b/pac/atsamda1g/src/port/group/dirtgl.rs new file mode 100644 index 00000000000..37339d76c54 --- /dev/null +++ b/pac/atsamda1g/src/port/group/dirtgl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRTGL` reader - Port Data Direction Toggle"] +pub struct DIRTGL_R(crate::FieldReader); +impl DIRTGL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRTGL` writer - Port Data Direction Toggle"] +pub struct DIRTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DIRTGL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Toggle"] + #[inline(always)] + pub fn dirtgl(&self) -> DIRTGL_R { + DIRTGL_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Toggle"] + #[inline(always)] + pub fn dirtgl(&mut self) -> DIRTGL_W { + DIRTGL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/in_.rs b/pac/atsamda1g/src/port/group/in_.rs new file mode 100644 index 00000000000..1e84f070091 --- /dev/null +++ b/pac/atsamda1g/src/port/group/in_.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IN` reader - Port Data Input Value"] +pub struct IN_R(crate::FieldReader); +impl IN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Input Value"] + #[inline(always)] + pub fn in_(&self) -> IN_R { + IN_R::new(self.bits as u32) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/out.rs b/pac/atsamda1g/src/port/group/out.rs new file mode 100644 index 00000000000..48ecaa2358e --- /dev/null +++ b/pac/atsamda1g/src/port/group/out.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUT` reader - Port Data Output Value"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Port Data Output Value"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/outclr.rs b/pac/atsamda1g/src/port/group/outclr.rs new file mode 100644 index 00000000000..3ea8c378ed4 --- /dev/null +++ b/pac/atsamda1g/src/port/group/outclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTCLR` reader - Port Data Output Value Clear"] +pub struct OUTCLR_R(crate::FieldReader); +impl OUTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTCLR` writer - Port Data Output Value Clear"] +pub struct OUTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> OUTCLR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Clear"] + #[inline(always)] + pub fn outclr(&self) -> OUTCLR_R { + OUTCLR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Clear"] + #[inline(always)] + pub fn outclr(&mut self) -> OUTCLR_W { + OUTCLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/outset.rs b/pac/atsamda1g/src/port/group/outset.rs new file mode 100644 index 00000000000..e905e4508b2 --- /dev/null +++ b/pac/atsamda1g/src/port/group/outset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTSET` reader - Port Data Output Value Set"] +pub struct OUTSET_R(crate::FieldReader); +impl OUTSET_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTSET` writer - Port Data Output Value Set"] +pub struct OUTSET_W<'a> { + w: &'a mut W, +} +impl<'a> OUTSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Set"] + #[inline(always)] + pub fn outset(&self) -> OUTSET_R { + OUTSET_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Set"] + #[inline(always)] + pub fn outset(&mut self) -> OUTSET_W { + OUTSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/outtgl.rs b/pac/atsamda1g/src/port/group/outtgl.rs new file mode 100644 index 00000000000..437b7f6681d --- /dev/null +++ b/pac/atsamda1g/src/port/group/outtgl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTTGL` reader - Port Data Output Value Toggle"] +pub struct OUTTGL_R(crate::FieldReader); +impl OUTTGL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTTGL` writer - Port Data Output Value Toggle"] +pub struct OUTTGL_W<'a> { + w: &'a mut W, +} +impl<'a> OUTTGL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Toggle"] + #[inline(always)] + pub fn outtgl(&self) -> OUTTGL_R { + OUTTGL_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Toggle"] + #[inline(always)] + pub fn outtgl(&mut self) -> OUTTGL_W { + OUTTGL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/pincfg.rs b/pac/atsamda1g/src/port/group/pincfg.rs new file mode 100644 index 00000000000..215e64ba226 --- /dev/null +++ b/pac/atsamda1g/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Peripheral Multiplexer Enable"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Peripheral Multiplexer Enable"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/pmux.rs b/pac/atsamda1g/src/port/group/pmux.rs new file mode 100644 index 00000000000..98cf2bbec5b --- /dev/null +++ b/pac/atsamda1g/src/port/group/pmux.rs @@ -0,0 +1,395 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Peripheral Multiplexing Even\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PMUXE_A { + #[doc = "0: Peripheral function A selected"] + A = 0, + #[doc = "1: Peripheral function B selected"] + B = 1, + #[doc = "2: Peripheral function C selected"] + C = 2, + #[doc = "3: Peripheral function D selected"] + D = 3, + #[doc = "4: Peripheral function E selected"] + E = 4, + #[doc = "5: Peripheral function F selected"] + F = 5, + #[doc = "6: Peripheral function G selected"] + G = 6, + #[doc = "7: Peripheral function H selected"] + H = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PMUXE_A) -> Self { + variant as _ + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing Even"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PMUXE_A::A), + 1 => Some(PMUXE_A::B), + 2 => Some(PMUXE_A::C), + 3 => Some(PMUXE_A::D), + 4 => Some(PMUXE_A::E), + 5 => Some(PMUXE_A::F), + 6 => Some(PMUXE_A::G), + 7 => Some(PMUXE_A::H), + _ => None, + } + } + #[doc = "Checks if the value of the field is `A`"] + #[inline(always)] + pub fn is_a(&self) -> bool { + **self == PMUXE_A::A + } + #[doc = "Checks if the value of the field is `B`"] + #[inline(always)] + pub fn is_b(&self) -> bool { + **self == PMUXE_A::B + } + #[doc = "Checks if the value of the field is `C`"] + #[inline(always)] + pub fn is_c(&self) -> bool { + **self == PMUXE_A::C + } + #[doc = "Checks if the value of the field is `D`"] + #[inline(always)] + pub fn is_d(&self) -> bool { + **self == PMUXE_A::D + } + #[doc = "Checks if the value of the field is `E`"] + #[inline(always)] + pub fn is_e(&self) -> bool { + **self == PMUXE_A::E + } + #[doc = "Checks if the value of the field is `F`"] + #[inline(always)] + pub fn is_f(&self) -> bool { + **self == PMUXE_A::F + } + #[doc = "Checks if the value of the field is `G`"] + #[inline(always)] + pub fn is_g(&self) -> bool { + **self == PMUXE_A::G + } + #[doc = "Checks if the value of the field is `H`"] + #[inline(always)] + pub fn is_h(&self) -> bool { + **self == PMUXE_A::H + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing Even"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMUXE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral function A selected"] + #[inline(always)] + pub fn a(self) -> &'a mut W { + self.variant(PMUXE_A::A) + } + #[doc = "Peripheral function B selected"] + #[inline(always)] + pub fn b(self) -> &'a mut W { + self.variant(PMUXE_A::B) + } + #[doc = "Peripheral function C selected"] + #[inline(always)] + pub fn c(self) -> &'a mut W { + self.variant(PMUXE_A::C) + } + #[doc = "Peripheral function D selected"] + #[inline(always)] + pub fn d(self) -> &'a mut W { + self.variant(PMUXE_A::D) + } + #[doc = "Peripheral function E selected"] + #[inline(always)] + pub fn e(self) -> &'a mut W { + self.variant(PMUXE_A::E) + } + #[doc = "Peripheral function F selected"] + #[inline(always)] + pub fn f(self) -> &'a mut W { + self.variant(PMUXE_A::F) + } + #[doc = "Peripheral function G selected"] + #[inline(always)] + pub fn g(self) -> &'a mut W { + self.variant(PMUXE_A::G) + } + #[doc = "Peripheral function H selected"] + #[inline(always)] + pub fn h(self) -> &'a mut W { + self.variant(PMUXE_A::H) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Peripheral Multiplexing Odd\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PMUXO_A { + #[doc = "0: Peripheral function A selected"] + A = 0, + #[doc = "1: Peripheral function B selected"] + B = 1, + #[doc = "2: Peripheral function C selected"] + C = 2, + #[doc = "3: Peripheral function D selected"] + D = 3, + #[doc = "4: Peripheral function E selected"] + E = 4, + #[doc = "5: Peripheral function F selected"] + F = 5, + #[doc = "6: Peripheral function G selected"] + G = 6, + #[doc = "7: Peripheral function H selected"] + H = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PMUXO_A) -> Self { + variant as _ + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing Odd"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PMUXO_A::A), + 1 => Some(PMUXO_A::B), + 2 => Some(PMUXO_A::C), + 3 => Some(PMUXO_A::D), + 4 => Some(PMUXO_A::E), + 5 => Some(PMUXO_A::F), + 6 => Some(PMUXO_A::G), + 7 => Some(PMUXO_A::H), + _ => None, + } + } + #[doc = "Checks if the value of the field is `A`"] + #[inline(always)] + pub fn is_a(&self) -> bool { + **self == PMUXO_A::A + } + #[doc = "Checks if the value of the field is `B`"] + #[inline(always)] + pub fn is_b(&self) -> bool { + **self == PMUXO_A::B + } + #[doc = "Checks if the value of the field is `C`"] + #[inline(always)] + pub fn is_c(&self) -> bool { + **self == PMUXO_A::C + } + #[doc = "Checks if the value of the field is `D`"] + #[inline(always)] + pub fn is_d(&self) -> bool { + **self == PMUXO_A::D + } + #[doc = "Checks if the value of the field is `E`"] + #[inline(always)] + pub fn is_e(&self) -> bool { + **self == PMUXO_A::E + } + #[doc = "Checks if the value of the field is `F`"] + #[inline(always)] + pub fn is_f(&self) -> bool { + **self == PMUXO_A::F + } + #[doc = "Checks if the value of the field is `G`"] + #[inline(always)] + pub fn is_g(&self) -> bool { + **self == PMUXO_A::G + } + #[doc = "Checks if the value of the field is `H`"] + #[inline(always)] + pub fn is_h(&self) -> bool { + **self == PMUXO_A::H + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing Odd"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMUXO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral function A selected"] + #[inline(always)] + pub fn a(self) -> &'a mut W { + self.variant(PMUXO_A::A) + } + #[doc = "Peripheral function B selected"] + #[inline(always)] + pub fn b(self) -> &'a mut W { + self.variant(PMUXO_A::B) + } + #[doc = "Peripheral function C selected"] + #[inline(always)] + pub fn c(self) -> &'a mut W { + self.variant(PMUXO_A::C) + } + #[doc = "Peripheral function D selected"] + #[inline(always)] + pub fn d(self) -> &'a mut W { + self.variant(PMUXO_A::D) + } + #[doc = "Peripheral function E selected"] + #[inline(always)] + pub fn e(self) -> &'a mut W { + self.variant(PMUXO_A::E) + } + #[doc = "Peripheral function F selected"] + #[inline(always)] + pub fn f(self) -> &'a mut W { + self.variant(PMUXO_A::F) + } + #[doc = "Peripheral function G selected"] + #[inline(always)] + pub fn g(self) -> &'a mut W { + self.variant(PMUXO_A::G) + } + #[doc = "Peripheral function H selected"] + #[inline(always)] + pub fn h(self) -> &'a mut W { + self.variant(PMUXO_A::H) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing Even"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing Odd"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing Even"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing Odd"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/port/group/wrconfig.rs b/pac/atsamda1g/src/port/group/wrconfig.rs new file mode 100644 index 00000000000..67177b9fa53 --- /dev/null +++ b/pac/atsamda1g/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Peripheral Multiplexer Enable"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc.rs b/pac/atsamda1g/src/rtc.rs new file mode 100644 index 00000000000..47c627343b6 --- /dev/null +++ b/pac/atsamda1g/src/rtc.rs @@ -0,0 +1,123 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x1d], +} +impl RegisterBlock { + #[doc = "0x00..0x1d - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x1c - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x1c - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x18 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x14 - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x18 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x18 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x1c - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamda1g/src/rtc/mode0.rs b/pac/atsamda1g/src/rtc/mode0.rs new file mode 100644 index 00000000000..8dc0e3eea44 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0.rs @@ -0,0 +1,44 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE0 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamda1g/src/rtc/mode0/comp.rs b/pac/atsamda1g/src/rtc/mode0/comp.rs new file mode 100644 index 00000000000..a909d3cea2d --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/count.rs b/pac/atsamda1g/src/rtc/mode0/count.rs new file mode 100644 index 00000000000..cf880b5e77a --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/ctrl.rs b/pac/atsamda1g/src/rtc/mode0/ctrl.rs new file mode 100644 index 00000000000..e32ff1ab1dc --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/ctrl.rs @@ -0,0 +1,509 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/dbgctrl.rs b/pac/atsamda1g/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/evctrl.rs b/pac/atsamda1g/src/rtc/mode0/evctrl.rs new file mode 100644 index 00000000000..e06b491ad66 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/freqcorr.rs b/pac/atsamda1g/src/rtc/mode0/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/intenclr.rs b/pac/atsamda1g/src/rtc/mode0/intenclr.rs new file mode 100644 index 00000000000..3b44cce826b --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/intenset.rs b/pac/atsamda1g/src/rtc/mode0/intenset.rs new file mode 100644 index 00000000000..46c47783336 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/intflag.rs b/pac/atsamda1g/src/rtc/mode0/intflag.rs new file mode 100644 index 00000000000..991f5424f3f --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/readreq.rs b/pac/atsamda1g/src/rtc/mode0/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1g/src/rtc/mode0/status.rs b/pac/atsamda1g/src/rtc/mode0/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode0/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1.rs b/pac/atsamda1g/src/rtc/mode1.rs new file mode 100644 index 00000000000..4582204fc4a --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1.rs @@ -0,0 +1,48 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE1 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamda1g/src/rtc/mode1/comp.rs b/pac/atsamda1g/src/rtc/mode1/comp.rs new file mode 100644 index 00000000000..6935385840f --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/count.rs b/pac/atsamda1g/src/rtc/mode1/count.rs new file mode 100644 index 00000000000..2c41937b189 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/ctrl.rs b/pac/atsamda1g/src/rtc/mode1/ctrl.rs new file mode 100644 index 00000000000..6d513fa447d --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/ctrl.rs @@ -0,0 +1,462 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/dbgctrl.rs b/pac/atsamda1g/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/evctrl.rs b/pac/atsamda1g/src/rtc/mode1/evctrl.rs new file mode 100644 index 00000000000..28fad144acf --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/freqcorr.rs b/pac/atsamda1g/src/rtc/mode1/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/intenclr.rs b/pac/atsamda1g/src/rtc/mode1/intenclr.rs new file mode 100644 index 00000000000..69074385c72 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/intenset.rs b/pac/atsamda1g/src/rtc/mode1/intenset.rs new file mode 100644 index 00000000000..c3751bcd1c5 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/intflag.rs b/pac/atsamda1g/src/rtc/mode1/intflag.rs new file mode 100644 index 00000000000..f138167c02f --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/per.rs b/pac/atsamda1g/src/rtc/mode1/per.rs new file mode 100644 index 00000000000..c09b31fa30d --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/readreq.rs b/pac/atsamda1g/src/rtc/mode1/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1g/src/rtc/mode1/status.rs b/pac/atsamda1g/src/rtc/mode1/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode1/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2.rs b/pac/atsamda1g/src/rtc/mode2.rs new file mode 100644 index 00000000000..1d505a71021 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2.rs @@ -0,0 +1,48 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE2 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamda1g/src/rtc/mode2/alarm.rs b/pac/atsamda1g/src/rtc/mode2/alarm.rs new file mode 100644 index 00000000000..1242477ea69 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/clock.rs b/pac/atsamda1g/src/rtc/mode2/clock.rs new file mode 100644 index 00000000000..3f364ff8e57 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/ctrl.rs b/pac/atsamda1g/src/rtc/mode2/ctrl.rs new file mode 100644 index 00000000000..a66d90c2afa --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/ctrl.rs @@ -0,0 +1,556 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/dbgctrl.rs b/pac/atsamda1g/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/evctrl.rs b/pac/atsamda1g/src/rtc/mode2/evctrl.rs new file mode 100644 index 00000000000..1d66be29f63 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/freqcorr.rs b/pac/atsamda1g/src/rtc/mode2/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/intenclr.rs b/pac/atsamda1g/src/rtc/mode2/intenclr.rs new file mode 100644 index 00000000000..b7fc6efcaeb --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/intenset.rs b/pac/atsamda1g/src/rtc/mode2/intenset.rs new file mode 100644 index 00000000000..c21bec8514d --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/intflag.rs b/pac/atsamda1g/src/rtc/mode2/intflag.rs new file mode 100644 index 00000000000..651fb283181 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/mask.rs b/pac/atsamda1g/src/rtc/mode2/mask.rs new file mode 100644 index 00000000000..53e0bb491a6 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/readreq.rs b/pac/atsamda1g/src/rtc/mode2/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1g/src/rtc/mode2/status.rs b/pac/atsamda1g/src/rtc/mode2/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1g/src/rtc/mode2/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sbmatrix.rs b/pac/atsamda1g/src/sbmatrix.rs new file mode 100644 index 00000000000..460bbc3fab0 --- /dev/null +++ b/pac/atsamda1g/src/sbmatrix.rs @@ -0,0 +1,25 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x80], + #[doc = "0x80..0x100 - PRS\\[%s\\]"] + pub prs: [PRS; 16], + _reserved1: [u8; 0x10], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamda1g/src/sbmatrix/prs.rs b/pac/atsamda1g/src/sbmatrix/prs.rs new file mode 100644 index 00000000000..0313f3c4fc2 --- /dev/null +++ b/pac/atsamda1g/src/sbmatrix/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamda1g/src/sbmatrix/prs/pras.rs b/pac/atsamda1g/src/sbmatrix/prs/pras.rs new file mode 100644 index 00000000000..9c009454899 --- /dev/null +++ b/pac/atsamda1g/src/sbmatrix/prs/pras.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sbmatrix/prs/prbs.rs b/pac/atsamda1g/src/sbmatrix/prs/prbs.rs new file mode 100644 index 00000000000..b92922b5d85 --- /dev/null +++ b/pac/atsamda1g/src/sbmatrix/prs/prbs.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sbmatrix/sfr.rs b/pac/atsamda1g/src/sbmatrix/sfr.rs new file mode 100644 index 00000000000..0a7e024f73c --- /dev/null +++ b/pac/atsamda1g/src/sbmatrix/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0.rs b/pac/atsamda1g/src/sercom0.rs new file mode 100644 index 00000000000..41bcdc65741 --- /dev/null +++ b/pac/atsamda1g/src/sercom0.rs @@ -0,0 +1,325 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + _reserved_2_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved4: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + _reserved_2_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved4: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamda1g/src/sercom0/i2cm.rs b/pac/atsamda1g/src/sercom0/i2cm.rs new file mode 100644 index 00000000000..8aa217da8b1 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1g/src/sercom0/i2cm/addr.rs b/pac/atsamda1g/src/sercom0/i2cm/addr.rs new file mode 100644 index 00000000000..4efd19e824c --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/baud.rs b/pac/atsamda1g/src/sercom0/i2cm/baud.rs new file mode 100644 index 00000000000..7c98d3b5b0d --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/ctrla.rs b/pac/atsamda1g/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 00000000000..34fa668b796 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/ctrlb.rs b/pac/atsamda1g/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 00000000000..ce534463c0d --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/data.rs b/pac/atsamda1g/src/sercom0/i2cm/data.rs new file mode 100644 index 00000000000..cf204596d3a --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamda1g/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 00000000000..0fffdb4c6e3 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/intenclr.rs b/pac/atsamda1g/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 00000000000..17f067a5565 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/intenset.rs b/pac/atsamda1g/src/sercom0/i2cm/intenset.rs new file mode 100644 index 00000000000..a0cbf96b3aa --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/intflag.rs b/pac/atsamda1g/src/sercom0/i2cm/intflag.rs new file mode 100644 index 00000000000..0fb0d2b9060 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/status.rs b/pac/atsamda1g/src/sercom0/i2cm/status.rs new file mode 100644 index 00000000000..95af23673ec --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cm/syncbusy.rs b/pac/atsamda1g/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 00000000000..87dd418d1cd --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs.rs b/pac/atsamda1g/src/sercom0/i2cs.rs new file mode 100644 index 00000000000..baf9513c6cc --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamda1g/src/sercom0/i2cs/addr.rs b/pac/atsamda1g/src/sercom0/i2cs/addr.rs new file mode 100644 index 00000000000..c1b69ee2289 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/ctrla.rs b/pac/atsamda1g/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 00000000000..ec93812b004 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/ctrlb.rs b/pac/atsamda1g/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 00000000000..b20f48581ed --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/data.rs b/pac/atsamda1g/src/sercom0/i2cs/data.rs new file mode 100644 index 00000000000..d8bfe070431 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/intenclr.rs b/pac/atsamda1g/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 00000000000..49f5191c8d6 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/intenset.rs b/pac/atsamda1g/src/sercom0/i2cs/intenset.rs new file mode 100644 index 00000000000..97ea784d747 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/intflag.rs b/pac/atsamda1g/src/sercom0/i2cs/intflag.rs new file mode 100644 index 00000000000..2eee333e4e5 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/status.rs b/pac/atsamda1g/src/sercom0/i2cs/status.rs new file mode 100644 index 00000000000..b3f6d218fa6 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/i2cs/syncbusy.rs b/pac/atsamda1g/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 00000000000..38e2509d966 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim.rs b/pac/atsamda1g/src/sercom0/spim.rs new file mode 100644 index 00000000000..528e38e1b81 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1g/src/sercom0/spim/addr.rs b/pac/atsamda1g/src/sercom0/spim/addr.rs new file mode 100644 index 00000000000..7c25cd522ea --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/baud.rs b/pac/atsamda1g/src/sercom0/spim/baud.rs new file mode 100644 index 00000000000..6bec9ca7435 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/ctrla.rs b/pac/atsamda1g/src/sercom0/spim/ctrla.rs new file mode 100644 index 00000000000..44028f8cbdd --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/ctrlb.rs b/pac/atsamda1g/src/sercom0/spim/ctrlb.rs new file mode 100644 index 00000000000..3d94f824ce8 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/data.rs b/pac/atsamda1g/src/sercom0/spim/data.rs new file mode 100644 index 00000000000..dc9cd020d2a --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/dbgctrl.rs b/pac/atsamda1g/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 00000000000..d9aa7495940 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/intenclr.rs b/pac/atsamda1g/src/sercom0/spim/intenclr.rs new file mode 100644 index 00000000000..ccab3de4348 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/intenset.rs b/pac/atsamda1g/src/sercom0/spim/intenset.rs new file mode 100644 index 00000000000..d9779cf897c --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/intflag.rs b/pac/atsamda1g/src/sercom0/spim/intflag.rs new file mode 100644 index 00000000000..e9bc10c271b --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/status.rs b/pac/atsamda1g/src/sercom0/spim/status.rs new file mode 100644 index 00000000000..9919460bf0e --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spim/syncbusy.rs b/pac/atsamda1g/src/sercom0/spim/syncbusy.rs new file mode 100644 index 00000000000..bee13adf708 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis.rs b/pac/atsamda1g/src/sercom0/spis.rs new file mode 100644 index 00000000000..eed10c90c46 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1g/src/sercom0/spis/addr.rs b/pac/atsamda1g/src/sercom0/spis/addr.rs new file mode 100644 index 00000000000..5fca0a698bf --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/baud.rs b/pac/atsamda1g/src/sercom0/spis/baud.rs new file mode 100644 index 00000000000..eeee4cf633e --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/ctrla.rs b/pac/atsamda1g/src/sercom0/spis/ctrla.rs new file mode 100644 index 00000000000..6151433a852 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/ctrlb.rs b/pac/atsamda1g/src/sercom0/spis/ctrlb.rs new file mode 100644 index 00000000000..ccb70582cf3 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/data.rs b/pac/atsamda1g/src/sercom0/spis/data.rs new file mode 100644 index 00000000000..4edf8089b29 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/dbgctrl.rs b/pac/atsamda1g/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 00000000000..ec36bbd2605 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/intenclr.rs b/pac/atsamda1g/src/sercom0/spis/intenclr.rs new file mode 100644 index 00000000000..e4c9ee0d506 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/intenset.rs b/pac/atsamda1g/src/sercom0/spis/intenset.rs new file mode 100644 index 00000000000..99582a624eb --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/intflag.rs b/pac/atsamda1g/src/sercom0/spis/intflag.rs new file mode 100644 index 00000000000..589e73c2329 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/status.rs b/pac/atsamda1g/src/sercom0/spis/status.rs new file mode 100644 index 00000000000..55c39c1a709 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/spis/syncbusy.rs b/pac/atsamda1g/src/sercom0/spis/syncbusy.rs new file mode 100644 index 00000000000..ac2f2e2c27e --- /dev/null +++ b/pac/atsamda1g/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext.rs b/pac/atsamda1g/src/sercom0/usart_ext.rs new file mode 100644 index 00000000000..09204a683ce --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1g/src/sercom0/usart_ext/baud.rs b/pac/atsamda1g/src/sercom0/usart_ext/baud.rs new file mode 100644 index 00000000000..9558a8e1a52 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamda1g/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 00000000000..d7cdd4570e2 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamda1g/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 00000000000..c1dc5080767 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamda1g/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 00000000000..8d4db16e024 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/ctrla.rs b/pac/atsamda1g/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 00000000000..bb4db0ad4db --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1256 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + PAD0 = 0, + #[doc = "1: PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + PAD1 = 1, + #[doc = "2: PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + PAD2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD1), + 2 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == TXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(TXPO_A::PAD1) + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Sample Adjustment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPA_A { + #[doc = "0: 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + ADJ0 = 0, + #[doc = "1: 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + ADJ1 = 1, + #[doc = "2: 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + ADJ2 = 2, + #[doc = "3: 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + ADJ3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPA_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SAMPA_A { + match self.bits { + 0 => SAMPA_A::ADJ0, + 1 => SAMPA_A::ADJ1, + 2 => SAMPA_A::ADJ2, + 3 => SAMPA_A::ADJ3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ADJ0`"] + #[inline(always)] + pub fn is_adj0(&self) -> bool { + **self == SAMPA_A::ADJ0 + } + #[doc = "Checks if the value of the field is `ADJ1`"] + #[inline(always)] + pub fn is_adj1(&self) -> bool { + **self == SAMPA_A::ADJ1 + } + #[doc = "Checks if the value of the field is `ADJ2`"] + #[inline(always)] + pub fn is_adj2(&self) -> bool { + **self == SAMPA_A::ADJ2 + } + #[doc = "Checks if the value of the field is `ADJ3`"] + #[inline(always)] + pub fn is_adj3(&self) -> bool { + **self == SAMPA_A::ADJ3 + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPA_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + #[inline(always)] + pub fn adj0(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ0) + } + #[doc = "16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + #[inline(always)] + pub fn adj1(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ1) + } + #[doc = "16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + #[inline(always)] + pub fn adj2(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ2) + } + #[doc = "16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + #[inline(always)] + pub fn adj3(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamda1g/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 00000000000..b821c8eb783 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,614 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/data.rs b/pac/atsamda1g/src/sercom0/usart_ext/data.rs new file mode 100644 index 00000000000..a54152c9571 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamda1g/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 00000000000..6c844f3fe40 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/intenclr.rs b/pac/atsamda1g/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 00000000000..a815553ce66 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/intenset.rs b/pac/atsamda1g/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 00000000000..e800681cf42 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/intflag.rs b/pac/atsamda1g/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 00000000000..4b0be279a9a --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/rxpl.rs b/pac/atsamda1g/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 00000000000..174464dc16b --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/status.rs b/pac/atsamda1g/src/sercom0/usart_ext/status.rs new file mode 100644 index 00000000000..a0c50c1bc2c --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamda1g/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 00000000000..7c3b817bbb0 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int.rs b/pac/atsamda1g/src/sercom0/usart_int.rs new file mode 100644 index 00000000000..d19ecaceea5 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1g/src/sercom0/usart_int/baud.rs b/pac/atsamda1g/src/sercom0/usart_int/baud.rs new file mode 100644 index 00000000000..a82df20712b --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamda1g/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 00000000000..b9c7fa4c4b2 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamda1g/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 00000000000..0671db99cc9 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamda1g/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 00000000000..b49a7ef5b84 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/ctrla.rs b/pac/atsamda1g/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 00000000000..76aed2866aa --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1256 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + PAD0 = 0, + #[doc = "1: PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + PAD1 = 1, + #[doc = "2: PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + PAD2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD1), + 2 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == TXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(TXPO_A::PAD1) + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Sample Adjustment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPA_A { + #[doc = "0: 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + ADJ0 = 0, + #[doc = "1: 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + ADJ1 = 1, + #[doc = "2: 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + ADJ2 = 2, + #[doc = "3: 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + ADJ3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPA_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SAMPA_A { + match self.bits { + 0 => SAMPA_A::ADJ0, + 1 => SAMPA_A::ADJ1, + 2 => SAMPA_A::ADJ2, + 3 => SAMPA_A::ADJ3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ADJ0`"] + #[inline(always)] + pub fn is_adj0(&self) -> bool { + **self == SAMPA_A::ADJ0 + } + #[doc = "Checks if the value of the field is `ADJ1`"] + #[inline(always)] + pub fn is_adj1(&self) -> bool { + **self == SAMPA_A::ADJ1 + } + #[doc = "Checks if the value of the field is `ADJ2`"] + #[inline(always)] + pub fn is_adj2(&self) -> bool { + **self == SAMPA_A::ADJ2 + } + #[doc = "Checks if the value of the field is `ADJ3`"] + #[inline(always)] + pub fn is_adj3(&self) -> bool { + **self == SAMPA_A::ADJ3 + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPA_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + #[inline(always)] + pub fn adj0(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ0) + } + #[doc = "16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + #[inline(always)] + pub fn adj1(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ1) + } + #[doc = "16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + #[inline(always)] + pub fn adj2(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ2) + } + #[doc = "16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + #[inline(always)] + pub fn adj3(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/ctrlb.rs b/pac/atsamda1g/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 00000000000..5c6cc4e67ee --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,614 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/data.rs b/pac/atsamda1g/src/sercom0/usart_int/data.rs new file mode 100644 index 00000000000..19d74c337d4 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamda1g/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 00000000000..0ac5b9c7b90 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/intenclr.rs b/pac/atsamda1g/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 00000000000..5ad23ad1563 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/intenset.rs b/pac/atsamda1g/src/sercom0/usart_int/intenset.rs new file mode 100644 index 00000000000..457f440e13e --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/intflag.rs b/pac/atsamda1g/src/sercom0/usart_int/intflag.rs new file mode 100644 index 00000000000..a6a26321b8c --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/rxpl.rs b/pac/atsamda1g/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 00000000000..324cbac371c --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/status.rs b/pac/atsamda1g/src/sercom0/usart_int/status.rs new file mode 100644 index 00000000000..1a92018a359 --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sercom0/usart_int/syncbusy.rs b/pac/atsamda1g/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 00000000000..5dea9a5a7ba --- /dev/null +++ b/pac/atsamda1g/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sys_tick.rs b/pac/atsamda1g/src/sys_tick.rs new file mode 100644 index 00000000000..b0fe7a59e5e --- /dev/null +++ b/pac/atsamda1g/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamda1g/src/sys_tick/calib.rs b/pac/atsamda1g/src/sys_tick/calib.rs new file mode 100644 index 00000000000..df7fd80f773 --- /dev/null +++ b/pac/atsamda1g/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sys_tick/csr.rs b/pac/atsamda1g/src/sys_tick/csr.rs new file mode 100644 index 00000000000..872d637f5a8 --- /dev/null +++ b/pac/atsamda1g/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamda1g/src/sys_tick/cvr.rs b/pac/atsamda1g/src/sys_tick/cvr.rs new file mode 100644 index 00000000000..8a40b5f43b3 --- /dev/null +++ b/pac/atsamda1g/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sys_tick/rvr.rs b/pac/atsamda1g/src/sys_tick/rvr.rs new file mode 100644 index 00000000000..ac023ff75f3 --- /dev/null +++ b/pac/atsamda1g/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl.rs b/pac/atsamda1g/src/sysctrl.rs new file mode 100644 index 00000000000..91255f3491a --- /dev/null +++ b/pac/atsamda1g/src/sysctrl.rs @@ -0,0 +1,132 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub pclksr: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xosc: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + _reserved6: [u8; 0x02], + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x20 - 8MHz Internal Oscillator (OSC8M) Control"] + pub osc8m: crate::Reg, + #[doc = "0x24 - DFLL48M Control"] + pub dfllctrl: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x28 - DFLL48M Value"] + pub dfllval: crate::Reg, + #[doc = "0x2c - DFLL48M Multiplier"] + pub dfllmul: crate::Reg, + #[doc = "0x30 - DFLL48M Synchronization"] + pub dfllsync: crate::Reg, + _reserved13: [u8; 0x03], + #[doc = "0x34 - 3.3V Brown-Out Detector (BOD33) Control"] + pub bod33: crate::Reg, + _reserved14: [u8; 0x04], + #[doc = "0x3c - Voltage Regulator System (VREG) Control"] + pub vreg: crate::Reg, + _reserved15: [u8; 0x02], + #[doc = "0x40 - Voltage References System (VREF) Control"] + pub vref: crate::Reg, + #[doc = "0x44 - DPLL Control A"] + pub dpllctrla: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x48 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x4c - DPLL Control B"] + pub dpllctrlb: crate::Reg, + #[doc = "0x50 - DPLL Status"] + pub dpllstatus: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "PCLKSR register accessor: an alias for `Reg`"] +pub type PCLKSR = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod pclksr; +#[doc = "XOSC register accessor: an alias for `Reg`"] +pub type XOSC = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xosc; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; +#[doc = "OSC8M register accessor: an alias for `Reg`"] +pub type OSC8M = crate::Reg; +#[doc = "8MHz Internal Oscillator (OSC8M) Control"] +pub mod osc8m; +#[doc = "DFLLCTRL register accessor: an alias for `Reg`"] +pub type DFLLCTRL = crate::Reg; +#[doc = "DFLL48M Control"] +pub mod dfllctrl; +#[doc = "DFLLVAL register accessor: an alias for `Reg`"] +pub type DFLLVAL = crate::Reg; +#[doc = "DFLL48M Value"] +pub mod dfllval; +#[doc = "DFLLMUL register accessor: an alias for `Reg`"] +pub type DFLLMUL = crate::Reg; +#[doc = "DFLL48M Multiplier"] +pub mod dfllmul; +#[doc = "DFLLSYNC register accessor: an alias for `Reg`"] +pub type DFLLSYNC = crate::Reg; +#[doc = "DFLL48M Synchronization"] +pub mod dfllsync; +#[doc = "BOD33 register accessor: an alias for `Reg`"] +pub type BOD33 = crate::Reg; +#[doc = "3.3V Brown-Out Detector (BOD33) Control"] +pub mod bod33; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "Voltage Regulator System (VREG) Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "Voltage References System (VREF) Control"] +pub mod vref; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control A"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "DPLL Control B"] +pub mod dpllctrlb; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; diff --git a/pac/atsamda1g/src/sysctrl/bod33.rs b/pac/atsamda1g/src/sysctrl/bod33.rs new file mode 100644 index 00000000000..f4678865a1f --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/bod33.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BOD33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOD33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "BOD33 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BOD33 generates a reset"] + RESET = 1, + #[doc = "2: The BOD33 generates an interrupt"] + INTERRUPT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - BOD33 Action"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INTERRUPT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INTERRUPT`"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + **self == ACTION_A::INTERRUPT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - BOD33 Action"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BOD33 generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BOD33 generates an interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut W { + self.variant(ACTION_A::INTERRUPT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MODE` reader - Operation Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operation Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CEN` reader - Clock Enable"] +pub struct CEN_R(crate::FieldReader); +impl CEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CEN` writer - Clock Enable"] +pub struct CEN_W<'a> { + w: &'a mut W, +} +impl<'a> CEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1K = 9, + #[doc = "10: Divide clock by 2048"] + DIV2K = 10, + #[doc = "11: Divide clock by 4096"] + DIV4K = 11, + #[doc = "12: Divide clock by 8192"] + DIV8K = 12, + #[doc = "13: Divide clock by 16384"] + DIV16K = 13, + #[doc = "14: Divide clock by 32768"] + DIV32K = 14, + #[doc = "15: Divide clock by 65536"] + DIV64K = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1K, + 10 => PSEL_A::DIV2K, + 11 => PSEL_A::DIV4K, + 12 => PSEL_A::DIV8K, + 13 => PSEL_A::DIV16K, + 14 => PSEL_A::DIV32K, + 15 => PSEL_A::DIV64K, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1K`"] + #[inline(always)] + pub fn is_div1k(&self) -> bool { + **self == PSEL_A::DIV1K + } + #[doc = "Checks if the value of the field is `DIV2K`"] + #[inline(always)] + pub fn is_div2k(&self) -> bool { + **self == PSEL_A::DIV2K + } + #[doc = "Checks if the value of the field is `DIV4K`"] + #[inline(always)] + pub fn is_div4k(&self) -> bool { + **self == PSEL_A::DIV4K + } + #[doc = "Checks if the value of the field is `DIV8K`"] + #[inline(always)] + pub fn is_div8k(&self) -> bool { + **self == PSEL_A::DIV8K + } + #[doc = "Checks if the value of the field is `DIV16K`"] + #[inline(always)] + pub fn is_div16k(&self) -> bool { + **self == PSEL_A::DIV16K + } + #[doc = "Checks if the value of the field is `DIV32K`"] + #[inline(always)] + pub fn is_div32k(&self) -> bool { + **self == PSEL_A::DIV32K + } + #[doc = "Checks if the value of the field is `DIV64K`"] + #[inline(always)] + pub fn is_div64k(&self) -> bool { + **self == PSEL_A::DIV64K + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1k(self) -> &'a mut W { + self.variant(PSEL_A::DIV1K) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2k(self) -> &'a mut W { + self.variant(PSEL_A::DIV2K) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4k(self) -> &'a mut W { + self.variant(PSEL_A::DIV4K) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8k(self) -> &'a mut W { + self.variant(PSEL_A::DIV8K) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16k(self) -> &'a mut W { + self.variant(PSEL_A::DIV16K) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32k(self) -> &'a mut W { + self.variant(PSEL_A::DIV32K) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div64k(self) -> &'a mut W { + self.variant(PSEL_A::DIV64K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - BOD33 Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - BOD33 Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - BOD33 Action"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Operation Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Clock Enable"] + #[inline(always)] + pub fn cen(&self) -> CEN_R { + CEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - BOD33 Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - BOD33 Action"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Operation Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 9 - Clock Enable"] + #[inline(always)] + pub fn cen(&mut self) -> CEN_W { + CEN_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - BOD33 Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "3.3V Brown-Out Detector (BOD33) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bod33](index.html) module"] +pub struct BOD33_SPEC; +impl crate::RegisterSpec for BOD33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bod33::R](R) reader structure"] +impl crate::Readable for BOD33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bod33::W](W) writer structure"] +impl crate::Writable for BOD33_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BOD33 to value 0"] +impl crate::Resettable for BOD33_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dfllctrl.rs b/pac/atsamda1g/src/sysctrl/dfllctrl.rs new file mode 100644 index 00000000000..0e0c6d5be2b --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dfllctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `DFLLCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - DFLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - DFLL Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MODE` reader - Operating Mode Selection"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode Selection"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STABLE` reader - Stable DFLL Frequency"] +pub struct STABLE_R(crate::FieldReader); +impl STABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STABLE` writer - Stable DFLL Frequency"] +pub struct STABLE_W<'a> { + w: &'a mut W, +} +impl<'a> STABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `LLAW` reader - Lose Lock After Wake"] +pub struct LLAW_R(crate::FieldReader); +impl LLAW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LLAW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LLAW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LLAW` writer - Lose Lock After Wake"] +pub struct LLAW_W<'a> { + w: &'a mut W, +} +impl<'a> LLAW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `USBCRM` reader - USB Clock Recovery Mode"] +pub struct USBCRM_R(crate::FieldReader); +impl USBCRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USBCRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USBCRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USBCRM` writer - USB Clock Recovery Mode"] +pub struct USBCRM_W<'a> { + w: &'a mut W, +} +impl<'a> USBCRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CCDIS` reader - Chill Cycle Disable"] +pub struct CCDIS_R(crate::FieldReader); +impl CCDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCDIS` writer - Chill Cycle Disable"] +pub struct CCDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CCDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QLDIS` reader - Quick Lock Disable"] +pub struct QLDIS_R(crate::FieldReader); +impl QLDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QLDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QLDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QLDIS` writer - Quick Lock Disable"] +pub struct QLDIS_W<'a> { + w: &'a mut W, +} +impl<'a> QLDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BPLCKC` reader - Bypass Coarse Lock"] +pub struct BPLCKC_R(crate::FieldReader); +impl BPLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BPLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BPLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BPLCKC` writer - Bypass Coarse Lock"] +pub struct BPLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> BPLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `WAITLOCK` reader - Wait Lock"] +pub struct WAITLOCK_R(crate::FieldReader); +impl WAITLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITLOCK` writer - Wait Lock"] +pub struct WAITLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WAITLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + pub fn stable(&self) -> STABLE_R { + STABLE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + pub fn llaw(&self) -> LLAW_R { + LLAW_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + pub fn usbcrm(&self) -> USBCRM_R { + USBCRM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + pub fn ccdis(&self) -> CCDIS_R { + CCDIS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + pub fn qldis(&self) -> QLDIS_R { + QLDIS_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + pub fn bplckc(&self) -> BPLCKC_R { + BPLCKC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + pub fn waitlock(&self) -> WAITLOCK_R { + WAITLOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + pub fn stable(&mut self) -> STABLE_W { + STABLE_W { w: self } + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + pub fn llaw(&mut self) -> LLAW_W { + LLAW_W { w: self } + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + pub fn usbcrm(&mut self) -> USBCRM_W { + USBCRM_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + pub fn ccdis(&mut self) -> CCDIS_W { + CCDIS_W { w: self } + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + pub fn qldis(&mut self) -> QLDIS_W { + QLDIS_W { w: self } + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + pub fn bplckc(&mut self) -> BPLCKC_W { + BPLCKC_W { w: self } + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + pub fn waitlock(&mut self) -> WAITLOCK_W { + WAITLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllctrl](index.html) module"] +pub struct DFLLCTRL_SPEC; +impl crate::RegisterSpec for DFLLCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [dfllctrl::R](R) reader structure"] +impl crate::Readable for DFLLCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllctrl::W](W) writer structure"] +impl crate::Writable for DFLLCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLCTRL to value 0x80"] +impl crate::Resettable for DFLLCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dfllmul.rs b/pac/atsamda1g/src/sysctrl/dfllmul.rs new file mode 100644 index 00000000000..a7f8b3e47ed --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dfllmul.rs @@ -0,0 +1,177 @@ +#[doc = "Register `DFLLMUL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLMUL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MUL` reader - DFLL Multiply Factor"] +pub struct MUL_R(crate::FieldReader); +impl MUL_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MUL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MUL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUL` writer - DFLL Multiply Factor"] +pub struct MUL_W<'a> { + w: &'a mut W, +} +impl<'a> MUL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `FSTEP` reader - Fine Maximum Step"] +pub struct FSTEP_R(crate::FieldReader); +impl FSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSTEP` writer - Fine Maximum Step"] +pub struct FSTEP_W<'a> { + w: &'a mut W, +} +impl<'a> FSTEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 16)) | ((value as u32 & 0x03ff) << 16); + self.w + } +} +#[doc = "Field `CSTEP` reader - Coarse Maximum Step"] +pub struct CSTEP_R(crate::FieldReader); +impl CSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSTEP` writer - Coarse Maximum Step"] +pub struct CSTEP_W<'a> { + w: &'a mut W, +} +impl<'a> CSTEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + pub fn mul(&self) -> MUL_R { + MUL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + pub fn fstep(&self) -> FSTEP_R { + FSTEP_R::new(((self.bits >> 16) & 0x03ff) as u16) + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + pub fn cstep(&self) -> CSTEP_R { + CSTEP_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + pub fn mul(&mut self) -> MUL_W { + MUL_W { w: self } + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + pub fn fstep(&mut self) -> FSTEP_W { + FSTEP_W { w: self } + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + pub fn cstep(&mut self) -> CSTEP_W { + CSTEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Multiplier\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllmul](index.html) module"] +pub struct DFLLMUL_SPEC; +impl crate::RegisterSpec for DFLLMUL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllmul::R](R) reader structure"] +impl crate::Readable for DFLLMUL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllmul::W](W) writer structure"] +impl crate::Writable for DFLLMUL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLMUL to value 0"] +impl crate::Resettable for DFLLMUL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dfllsync.rs b/pac/atsamda1g/src/sysctrl/dfllsync.rs new file mode 100644 index 00000000000..ab2d44b3a57 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dfllsync.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DFLLSYNC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLSYNC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READREQ` reader - Read Request"] +pub struct READREQ_R(crate::FieldReader); +impl READREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READREQ` writer - Read Request"] +pub struct READREQ_W<'a> { + w: &'a mut W, +} +impl<'a> READREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Read Request"] + #[inline(always)] + pub fn readreq(&self) -> READREQ_R { + READREQ_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Read Request"] + #[inline(always)] + pub fn readreq(&mut self) -> READREQ_W { + READREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Synchronization\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllsync](index.html) module"] +pub struct DFLLSYNC_SPEC; +impl crate::RegisterSpec for DFLLSYNC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dfllsync::R](R) reader structure"] +impl crate::Readable for DFLLSYNC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllsync::W](W) writer structure"] +impl crate::Writable for DFLLSYNC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLSYNC to value 0"] +impl crate::Resettable for DFLLSYNC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dfllval.rs b/pac/atsamda1g/src/sysctrl/dfllval.rs new file mode 100644 index 00000000000..9098c660072 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dfllval.rs @@ -0,0 +1,177 @@ +#[doc = "Register `DFLLVAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLVAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FINE` reader - Fine Value"] +pub struct FINE_R(crate::FieldReader); +impl FINE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FINE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FINE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FINE` writer - Fine Value"] +pub struct FINE_W<'a> { + w: &'a mut W, +} +impl<'a> FINE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03ff) | (value as u32 & 0x03ff); + self.w + } +} +#[doc = "Field `COARSE` reader - Coarse Value"] +pub struct COARSE_R(crate::FieldReader); +impl COARSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COARSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COARSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COARSE` writer - Coarse Value"] +pub struct COARSE_W<'a> { + w: &'a mut W, +} +impl<'a> COARSE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 10)) | ((value as u32 & 0x3f) << 10); + self.w + } +} +#[doc = "Field `DIFF` reader - Multiplication Ratio Difference"] +pub struct DIFF_R(crate::FieldReader); +impl DIFF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFF` writer - Multiplication Ratio Difference"] +pub struct DIFF_W<'a> { + w: &'a mut W, +} +impl<'a> DIFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + pub fn fine(&self) -> FINE_R { + FINE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + pub fn coarse(&self) -> COARSE_R { + COARSE_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:31 - Multiplication Ratio Difference"] + #[inline(always)] + pub fn diff(&self) -> DIFF_R { + DIFF_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + pub fn fine(&mut self) -> FINE_W { + FINE_W { w: self } + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + pub fn coarse(&mut self) -> COARSE_W { + COARSE_W { w: self } + } + #[doc = "Bits 16:31 - Multiplication Ratio Difference"] + #[inline(always)] + pub fn diff(&mut self) -> DIFF_W { + DIFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllval](index.html) module"] +pub struct DFLLVAL_SPEC; +impl crate::RegisterSpec for DFLLVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllval::R](R) reader structure"] +impl crate::Readable for DFLLVAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllval::W](W) writer structure"] +impl crate::Writable for DFLLVAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLVAL to value 0"] +impl crate::Resettable for DFLLVAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dpllctrla.rs b/pac/atsamda1g/src/sysctrl/dpllctrla.rs new file mode 100644 index 00000000000..c0600c21f16 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - DPLL Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Clock Activation"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Clock Activation"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Clock Activation"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - DPLL Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Clock Activation"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dpllctrlb.rs b/pac/atsamda1g/src/sysctrl/dpllctrlb.rs new file mode 100644 index 00000000000..968579fc693 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: CLK_DPLL_REF0 clock reference"] + REF0 = 0, + #[doc = "1: CLK_DPLL_REF1 clock reference"] + REF1 = 1, + #[doc = "2: GCLK_DPLL clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::REF0), + 1 => Some(REFCLK_A::REF1), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `REF0`"] + #[inline(always)] + pub fn is_ref0(&self) -> bool { + **self == REFCLK_A::REF0 + } + #[doc = "Checks if the value of the field is `REF1`"] + #[inline(always)] + pub fn is_ref1(&self) -> bool { + **self == REFCLK_A::REF1 + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_DPLL_REF0 clock reference"] + #[inline(always)] + pub fn ref0(self) -> &'a mut W { + self.variant(REFCLK_A::REF0) + } + #[doc = "CLK_DPLL_REF1 clock reference"] + #[inline(always)] + pub fn ref1(self) -> &'a mut W { + self.variant(REFCLK_A::REF1) + } + #[doc = "GCLK_DPLL clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out"] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8 ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9 ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10 ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11 ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8 ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9 ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10 ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11 ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dpllratio.rs b/pac/atsamda1g/src/sysctrl/dpllratio.rs new file mode 100644 index 00000000000..93b39e30f1a --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/dpllstatus.rs b/pac/atsamda1g/src/sysctrl/dpllstatus.rs new file mode 100644 index 00000000000..70499131cff --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/dpllstatus.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - Output Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` reader - Divider Enable"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Divider Enable"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/intenclr.rs b/pac/atsamda1g/src/sysctrl/intenclr.rs new file mode 100644 index 00000000000..bf0a746e23a --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/intenclr.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/intenset.rs b/pac/atsamda1g/src/sysctrl/intenset.rs new file mode 100644 index 00000000000..39276ad4015 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/intenset.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/intflag.rs b/pac/atsamda1g/src/sysctrl/intflag.rs new file mode 100644 index 00000000000..0902e3120a1 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/intflag.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/osc32k.rs b/pac/atsamda1g/src/sysctrl/osc32k.rs new file mode 100644 index 00000000000..aa32cb287aa --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamda1g/src/sysctrl/osc8m.rs b/pac/atsamda1g/src/sysctrl/osc8m.rs new file mode 100644 index 00000000000..24f058d3ed1 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/osc8m.rs @@ -0,0 +1,468 @@ +#[doc = "Register `OSC8M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC8M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Prescaler\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: `0`"] + _0 = 0, + #[doc = "1: `1`"] + _1 = 1, + #[doc = "2: `10`"] + _2 = 2, + #[doc = "3: `11`"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Oscillator Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESC_A { + match self.bits { + 0 => PRESC_A::_0, + 1 => PRESC_A::_1, + 2 => PRESC_A::_2, + 3 => PRESC_A::_3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PRESC_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PRESC_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PRESC_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PRESC_A::_3 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Oscillator Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(PRESC_A::_0) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(PRESC_A::_1) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(PRESC_A::_2) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(PRESC_A::_3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 16)) | ((value as u32 & 0x0fff) << 16); + self.w + } +} +#[doc = "Oscillator Frequency Range\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FRANGE_A { + #[doc = "0: 4 to 6MHz"] + _0 = 0, + #[doc = "1: 6 to 8MHz"] + _1 = 1, + #[doc = "2: 8 to 11MHz"] + _2 = 2, + #[doc = "3: 11 to 15MHz"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FRANGE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FRANGE` reader - Oscillator Frequency Range"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRANGE_A { + match self.bits { + 0 => FRANGE_A::_0, + 1 => FRANGE_A::_1, + 2 => FRANGE_A::_2, + 3 => FRANGE_A::_3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FRANGE_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FRANGE_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FRANGE_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == FRANGE_A::_3 + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Oscillator Frequency Range"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FRANGE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "4 to 6MHz"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(FRANGE_A::_0) + } + #[doc = "6 to 8MHz"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(FRANGE_A::_1) + } + #[doc = "8 to 11MHz"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(FRANGE_A::_2) + } + #[doc = "11 to 15MHz"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(FRANGE_A::_3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Oscillator Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:27 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x0fff) as u16) + } + #[doc = "Bits 30:31 - Oscillator Frequency Range"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:9 - Oscillator Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Bits 16:27 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bits 30:31 - Oscillator Frequency Range"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "8MHz Internal Oscillator (OSC8M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc8m](index.html) module"] +pub struct OSC8M_SPEC; +impl crate::RegisterSpec for OSC8M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc8m::R](R) reader structure"] +impl crate::Readable for OSC8M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc8m::W](W) writer structure"] +impl crate::Writable for OSC8M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC8M to value 0x8707_0382"] +impl crate::Resettable for OSC8M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8707_0382 + } +} diff --git a/pac/atsamda1g/src/sysctrl/osculp32k.rs b/pac/atsamda1g/src/sysctrl/osculp32k.rs new file mode 100644 index 00000000000..b7baa4236c5 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u8 & 0x1f); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0x1f"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1f + } +} diff --git a/pac/atsamda1g/src/sysctrl/pclksr.rs b/pac/atsamda1g/src/sysctrl/pclksr.rs new file mode 100644 index 00000000000..0298891e5f6 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/pclksr.rs @@ -0,0 +1,333 @@ +#[doc = "Register `PCLKSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pclksr](index.html) module"] +pub struct PCLKSR_SPEC; +impl crate::RegisterSpec for PCLKSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pclksr::R](R) reader structure"] +impl crate::Readable for PCLKSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PCLKSR to value 0"] +impl crate::Resettable for PCLKSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/vref.rs b/pac/atsamda1g/src/sysctrl/vref.rs new file mode 100644 index 00000000000..ecdfa1cc05a --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/vref.rs @@ -0,0 +1,197 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BGOUTEN` reader - Bandgap Output Enable"] +pub struct BGOUTEN_R(crate::FieldReader); +impl BGOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BGOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BGOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BGOUTEN` writer - Bandgap Output Enable"] +pub struct BGOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> BGOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CALIB` reader - Bandgap Voltage Generator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Bandgap Voltage Generator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bandgap Output Enable"] + #[inline(always)] + pub fn bgouten(&self) -> BGOUTEN_R { + BGOUTEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Bandgap Voltage Generator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Bandgap Output Enable"] + #[inline(always)] + pub fn bgouten(&mut self) -> BGOUTEN_W { + BGOUTEN_W { w: self } + } + #[doc = "Bits 16:26 - Bandgap Voltage Generator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Voltage References System (VREF) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/vreg.rs b/pac/atsamda1g/src/sysctrl/vreg.rs new file mode 100644 index 00000000000..42de242a11c --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `FORCELDO` reader - Force LDO Voltage Regulator"] +pub struct FORCELDO_R(crate::FieldReader); +impl FORCELDO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FORCELDO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FORCELDO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORCELDO` writer - Force LDO Voltage Regulator"] +pub struct FORCELDO_W<'a> { + w: &'a mut W, +} +impl<'a> FORCELDO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 13 - Force LDO Voltage Regulator"] + #[inline(always)] + pub fn forceldo(&self) -> FORCELDO_R { + FORCELDO_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 13 - Force LDO Voltage Regulator"] + #[inline(always)] + pub fn forceldo(&mut self) -> FORCELDO_W { + FORCELDO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Voltage Regulator System (VREG) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/sysctrl/xosc.rs b/pac/atsamda1g/src/sysctrl/xosc.rs new file mode 100644 index 00000000000..d1237a54e28 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/xosc.rs @@ -0,0 +1,694 @@ +#[doc = "Register `XOSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2MHz"] + _0 = 0, + #[doc = "1: 4MHz"] + _1 = 1, + #[doc = "2: 8MHz"] + _2 = 2, + #[doc = "3: 16MHz"] + _3 = 3, + #[doc = "4: 30MHz"] + _4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::_0), + 1 => Some(GAIN_A::_1), + 2 => Some(GAIN_A::_2), + 3 => Some(GAIN_A::_3), + 4 => Some(GAIN_A::_4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == GAIN_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == GAIN_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == GAIN_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == GAIN_A::_3 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == GAIN_A::_4 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2MHz"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(GAIN_A::_0) + } + #[doc = "4MHz"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(GAIN_A::_1) + } + #[doc = "8MHz"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(GAIN_A::_2) + } + #[doc = "16MHz"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(GAIN_A::_3) + } + #[doc = "30MHz"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(GAIN_A::_4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc](index.html) module"] +pub struct XOSC_SPEC; +impl crate::RegisterSpec for XOSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc::R](R) reader structure"] +impl crate::Readable for XOSC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc::W](W) writer structure"] +impl crate::Writable for XOSC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC to value 0x80"] +impl crate::Resettable for XOSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1g/src/sysctrl/xosc32k.rs b/pac/atsamda1g/src/sysctrl/xosc32k.rs new file mode 100644 index 00000000000..6a13602dfc9 --- /dev/null +++ b/pac/atsamda1g/src/sysctrl/xosc32k.rs @@ -0,0 +1,606 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `AAMPEN` reader - Automatic Amplitude Control Enable"] +pub struct AAMPEN_R(crate::FieldReader); +impl AAMPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AAMPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AAMPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AAMPEN` writer - Automatic Amplitude Control Enable"] +pub struct AAMPEN_W<'a> { + w: &'a mut W, +} +impl<'a> AAMPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.592 ms"] + CYCLE2048 = 2, + #[doc = "3: 125.092 ms"] + CYCLE4096 = 3, + #[doc = "4: 500.092 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000.092 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000.092 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000.092 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.592 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125.092 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500.092 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000.092 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000.092 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000.092 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Automatic Amplitude Control Enable"] + #[inline(always)] + pub fn aampen(&self) -> AAMPEN_R { + AAMPEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 5 - Automatic Amplitude Control Enable"] + #[inline(always)] + pub fn aampen(&mut self) -> AAMPEN_W { + AAMPEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1g/src/system_control.rs b/pac/atsamda1g/src/system_control.rs new file mode 100644 index 00000000000..4894b22b258 --- /dev/null +++ b/pac/atsamda1g/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamda1g/src/system_control/aircr.rs b/pac/atsamda1g/src/system_control/aircr.rs new file mode 100644 index 00000000000..9453cc6f30b --- /dev/null +++ b/pac/atsamda1g/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/system_control/ccr.rs b/pac/atsamda1g/src/system_control/ccr.rs new file mode 100644 index 00000000000..62516a7b60c --- /dev/null +++ b/pac/atsamda1g/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamda1g/src/system_control/cpuid.rs b/pac/atsamda1g/src/system_control/cpuid.rs new file mode 100644 index 00000000000..4157d7a94e9 --- /dev/null +++ b/pac/atsamda1g/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamda1g/src/system_control/dfsr.rs b/pac/atsamda1g/src/system_control/dfsr.rs new file mode 100644 index 00000000000..948899af090 --- /dev/null +++ b/pac/atsamda1g/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/system_control/icsr.rs b/pac/atsamda1g/src/system_control/icsr.rs new file mode 100644 index 00000000000..7fe5fd41211 --- /dev/null +++ b/pac/atsamda1g/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/system_control/scr.rs b/pac/atsamda1g/src/system_control/scr.rs new file mode 100644 index 00000000000..db9c54fe6f6 --- /dev/null +++ b/pac/atsamda1g/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/system_control/shcsr.rs b/pac/atsamda1g/src/system_control/shcsr.rs new file mode 100644 index 00000000000..bfba26ac06a --- /dev/null +++ b/pac/atsamda1g/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/system_control/shpr2.rs b/pac/atsamda1g/src/system_control/shpr2.rs new file mode 100644 index 00000000000..5665d6a5e8a --- /dev/null +++ b/pac/atsamda1g/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/system_control/shpr3.rs b/pac/atsamda1g/src/system_control/shpr3.rs new file mode 100644 index 00000000000..cb5a92c5350 --- /dev/null +++ b/pac/atsamda1g/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/system_control/vtor.rs b/pac/atsamda1g/src/system_control/vtor.rs new file mode 100644 index 00000000000..0ee4c781781 --- /dev/null +++ b/pac/atsamda1g/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3.rs b/pac/atsamda1g/src/tc3.rs new file mode 100644 index 00000000000..6465deb3413 --- /dev/null +++ b/pac/atsamda1g/src/tc3.rs @@ -0,0 +1,133 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x20], +} +impl RegisterBlock { + #[doc = "0x00..0x20 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x1c - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x1a - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT8 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x14 - COUNT8 Period Value"] + pub per: crate::Reg, + _reserved13: [u8; 0x03], + #[doc = "0x18 - COUNT8 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT16 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x06], + #[doc = "0x18 - COUNT16 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT32 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x04], + #[doc = "0x18..0x20 - COUNT32 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamda1g/src/tc3/count16.rs b/pac/atsamda1g/src/tc3/count16.rs new file mode 100644 index 00000000000..c184879d148 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16.rs @@ -0,0 +1,52 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Counter Value"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1g/src/tc3/count16/cc.rs b/pac/atsamda1g/src/tc3/count16/cc.rs new file mode 100644 index 00000000000..ca78398c970 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/count.rs b/pac/atsamda1g/src/tc3/count16/count.rs new file mode 100644 index 00000000000..421dff4311a --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Count Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Count Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Count Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Count Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/ctrla.rs b/pac/atsamda1g/src/tc3/count16/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/ctrlbclr.rs b/pac/atsamda1g/src/tc3/count16/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/ctrlbset.rs b/pac/atsamda1g/src/tc3/count16/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/ctrlc.rs b/pac/atsamda1g/src/tc3/count16/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/dbgctrl.rs b/pac/atsamda1g/src/tc3/count16/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/evctrl.rs b/pac/atsamda1g/src/tc3/count16/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/intenclr.rs b/pac/atsamda1g/src/tc3/count16/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/intenset.rs b/pac/atsamda1g/src/tc3/count16/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/intflag.rs b/pac/atsamda1g/src/tc3/count16/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/readreq.rs b/pac/atsamda1g/src/tc3/count16/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count16/status.rs b/pac/atsamda1g/src/tc3/count16/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count16/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1g/src/tc3/count32.rs b/pac/atsamda1g/src/tc3/count32.rs new file mode 100644 index 00000000000..aeb206f527b --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32.rs @@ -0,0 +1,52 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Counter Value"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1g/src/tc3/count32/cc.rs b/pac/atsamda1g/src/tc3/count32/cc.rs new file mode 100644 index 00000000000..d9cafa8cf2a --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/count.rs b/pac/atsamda1g/src/tc3/count32/count.rs new file mode 100644 index 00000000000..80e47741321 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Count Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Count Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Count Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Count Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/ctrla.rs b/pac/atsamda1g/src/tc3/count32/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/ctrlbclr.rs b/pac/atsamda1g/src/tc3/count32/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/ctrlbset.rs b/pac/atsamda1g/src/tc3/count32/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/ctrlc.rs b/pac/atsamda1g/src/tc3/count32/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/dbgctrl.rs b/pac/atsamda1g/src/tc3/count32/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/evctrl.rs b/pac/atsamda1g/src/tc3/count32/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/intenclr.rs b/pac/atsamda1g/src/tc3/count32/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/intenset.rs b/pac/atsamda1g/src/tc3/count32/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/intflag.rs b/pac/atsamda1g/src/tc3/count32/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/readreq.rs b/pac/atsamda1g/src/tc3/count32/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count32/status.rs b/pac/atsamda1g/src/tc3/count32/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count32/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1g/src/tc3/count8.rs b/pac/atsamda1g/src/tc3/count8.rs new file mode 100644 index 00000000000..c25911542ec --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period Value"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1g/src/tc3/count8/cc.rs b/pac/atsamda1g/src/tc3/count8/cc.rs new file mode 100644 index 00000000000..02ab7eb2bf7 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/count.rs b/pac/atsamda1g/src/tc3/count8/count.rs new file mode 100644 index 00000000000..203d066a2e2 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/ctrla.rs b/pac/atsamda1g/src/tc3/count8/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/ctrlbclr.rs b/pac/atsamda1g/src/tc3/count8/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/ctrlbset.rs b/pac/atsamda1g/src/tc3/count8/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/ctrlc.rs b/pac/atsamda1g/src/tc3/count8/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/dbgctrl.rs b/pac/atsamda1g/src/tc3/count8/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/evctrl.rs b/pac/atsamda1g/src/tc3/count8/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/intenclr.rs b/pac/atsamda1g/src/tc3/count8/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/intenset.rs b/pac/atsamda1g/src/tc3/count8/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/intflag.rs b/pac/atsamda1g/src/tc3/count8/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/per.rs b/pac/atsamda1g/src/tc3/count8/per.rs new file mode 100644 index 00000000000..27a157b4646 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamda1g/src/tc3/count8/readreq.rs b/pac/atsamda1g/src/tc3/count8/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tc3/count8/status.rs b/pac/atsamda1g/src/tc3/count8/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1g/src/tc3/count8/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1g/src/tcc0.rs b/pac/atsamda1g/src/tcc0.rs new file mode 100644 index 00000000000..32249343331 --- /dev/null +++ b/pac/atsamda1g/src/tcc0.rs @@ -0,0 +1,365 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattb: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x68 - Waveform Control Buffer"] + pub waveb: crate::Reg, + _reserved_21_perb: [u8; 0x04], + _reserved_22_ccb: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTB register accessor: an alias for `Reg`"] +pub type PATTB = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattb; +#[doc = "WAVEB register accessor: an alias for `Reg`"] +pub type WAVEB = crate::Reg; +#[doc = "Waveform Control Buffer"] +pub mod waveb; +#[doc = "PERB register accessor: an alias for `Reg`"] +pub type PERB = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb; +#[doc = "PERB_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith4_mode; +#[doc = "PERB_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith5_mode; +#[doc = "PERB_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith6_mode; +#[doc = "CCB register accessor: an alias for `Reg`"] +pub type CCB = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb; +#[doc = "CCB_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith4_mode; +#[doc = "CCB_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith5_mode; +#[doc = "CCB_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith6_mode; diff --git a/pac/atsamda1g/src/tcc0/cc.rs b/pac/atsamda1g/src/tcc0/cc.rs new file mode 100644 index 00000000000..c4d6df7a9a2 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/cc_dith4_mode.rs b/pac/atsamda1g/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 00000000000..f386ab1bdd8 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/cc_dith5_mode.rs b/pac/atsamda1g/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 00000000000..88749a75cb3 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/cc_dith6_mode.rs b/pac/atsamda1g/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 00000000000..a315f193152 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/ccb.rs b/pac/atsamda1g/src/tcc0/ccb.rs new file mode 100644 index 00000000000..3ccab84b34c --- /dev/null +++ b/pac/atsamda1g/src/tcc0/ccb.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCB[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb](index.html) module"] +pub struct CCB_SPEC; +impl crate::RegisterSpec for CCB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb::R](R) reader structure"] +impl crate::Readable for CCB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb::W](W) writer structure"] +impl crate::Writable for CCB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB[%s] +to value 0"] +impl crate::Resettable for CCB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/ccb_dith4_mode.rs b/pac/atsamda1g/src/tcc0/ccb_dith4_mode.rs new file mode 100644 index 00000000000..bece549a8d7 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/ccb_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith4_mode](index.html) module"] +pub struct CCB_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/ccb_dith5_mode.rs b/pac/atsamda1g/src/tcc0/ccb_dith5_mode.rs new file mode 100644 index 00000000000..71235fa105b --- /dev/null +++ b/pac/atsamda1g/src/tcc0/ccb_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith5_mode](index.html) module"] +pub struct CCB_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/ccb_dith6_mode.rs b/pac/atsamda1g/src/tcc0/ccb_dith6_mode.rs new file mode 100644 index 00000000000..f7aa63650de --- /dev/null +++ b/pac/atsamda1g/src/tcc0/ccb_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith6_mode](index.html) module"] +pub struct CCB_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/count.rs b/pac/atsamda1g/src/tcc0/count.rs new file mode 100644 index 00000000000..7628f2c0d5e --- /dev/null +++ b/pac/atsamda1g/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/count_dith4_mode.rs b/pac/atsamda1g/src/tcc0/count_dith4_mode.rs new file mode 100644 index 00000000000..fc058ae5efd --- /dev/null +++ b/pac/atsamda1g/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/count_dith5_mode.rs b/pac/atsamda1g/src/tcc0/count_dith5_mode.rs new file mode 100644 index 00000000000..e66e2031072 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/count_dith6_mode.rs b/pac/atsamda1g/src/tcc0/count_dith6_mode.rs new file mode 100644 index 00000000000..5410fc6c945 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/ctrla.rs b/pac/atsamda1g/src/tcc0/ctrla.rs new file mode 100644 index 00000000000..ce94f627db2 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/ctrla.rs @@ -0,0 +1,817 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/ctrlbclr.rs b/pac/atsamda1g/src/tcc0/ctrlbclr.rs new file mode 100644 index 00000000000..39a196da677 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/ctrlbclr.rs @@ -0,0 +1,444 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update of double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/ctrlbset.rs b/pac/atsamda1g/src/tcc0/ctrlbset.rs new file mode 100644 index 00000000000..a02c4d5e1ee --- /dev/null +++ b/pac/atsamda1g/src/tcc0/ctrlbset.rs @@ -0,0 +1,444 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update of double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/dbgctrl.rs b/pac/atsamda1g/src/tcc0/dbgctrl.rs new file mode 100644 index 00000000000..313ebe3f5c1 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/drvctrl.rs b/pac/atsamda1g/src/tcc0/drvctrl.rs new file mode 100644 index 00000000000..316041e1e3b --- /dev/null +++ b/pac/atsamda1g/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/evctrl.rs b/pac/atsamda1g/src/tcc0/evctrl.rs new file mode 100644 index 00000000000..5eaba702e34 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/evctrl.rs @@ -0,0 +1,1198 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT0_A::OFF), + 1 => Some(EVACT0_A::RETRIGGER), + 2 => Some(EVACT0_A::COUNTEV), + 3 => Some(EVACT0_A::START), + 4 => Some(EVACT0_A::INC), + 5 => Some(EVACT0_A::COUNT), + 7 => Some(EVACT0_A::FAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/fctrla.rs b/pac/atsamda1g/src/tcc0/fctrla.rs new file mode 100644 index 00000000000..e55d54575a4 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/fctrla.rs @@ -0,0 +1,880 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: No blanking applied"] + NONE = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::NONE, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == BLANK_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No blanking applied"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BLANK_A::NONE) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTURE_A::DISABLE), + 1 => Some(CAPTURE_A::CAPT), + 2 => Some(CAPTURE_A::CAPTMIN), + 3 => Some(CAPTURE_A::CAPTMAX), + 4 => Some(CAPTURE_A::LOCMIN), + 5 => Some(CAPTURE_A::LOCMAX), + 6 => Some(CAPTURE_A::DERIV0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/fctrlb.rs b/pac/atsamda1g/src/tcc0/fctrlb.rs new file mode 100644 index 00000000000..2dd88cc1904 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/fctrlb.rs @@ -0,0 +1,880 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: No blanking applied"] + NONE = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::NONE, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == BLANK_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No blanking applied"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BLANK_A::NONE) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTURE_A::DISABLE), + 1 => Some(CAPTURE_A::CAPT), + 2 => Some(CAPTURE_A::CAPTMIN), + 3 => Some(CAPTURE_A::CAPTMAX), + 4 => Some(CAPTURE_A::LOCMIN), + 5 => Some(CAPTURE_A::LOCMAX), + 6 => Some(CAPTURE_A::DERIV0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/intenclr.rs b/pac/atsamda1g/src/tcc0/intenclr.rs new file mode 100644 index 00000000000..bd054b6cbbd --- /dev/null +++ b/pac/atsamda1g/src/tcc0/intenclr.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/intenset.rs b/pac/atsamda1g/src/tcc0/intenset.rs new file mode 100644 index 00000000000..1be03869328 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/intenset.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/intflag.rs b/pac/atsamda1g/src/tcc0/intflag.rs new file mode 100644 index 00000000000..7106718fd29 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/intflag.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/patt.rs b/pac/atsamda1g/src/tcc0/patt.rs new file mode 100644 index 00000000000..ea458642b18 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/pattb.rs b/pac/atsamda1g/src/tcc0/pattb.rs new file mode 100644 index 00000000000..04190b1d35d --- /dev/null +++ b/pac/atsamda1g/src/tcc0/pattb.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattb](index.html) module"] +pub struct PATTB_SPEC; +impl crate::RegisterSpec for PATTB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattb::R](R) reader structure"] +impl crate::Readable for PATTB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattb::W](W) writer structure"] +impl crate::Writable for PATTB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTB to value 0"] +impl crate::Resettable for PATTB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/per.rs b/pac/atsamda1g/src/tcc0/per.rs new file mode 100644 index 00000000000..9d861863165 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/per_dith4_mode.rs b/pac/atsamda1g/src/tcc0/per_dith4_mode.rs new file mode 100644 index 00000000000..6e8d857e483 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/per_dith5_mode.rs b/pac/atsamda1g/src/tcc0/per_dith5_mode.rs new file mode 100644 index 00000000000..06337b7b91c --- /dev/null +++ b/pac/atsamda1g/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/per_dith6_mode.rs b/pac/atsamda1g/src/tcc0/per_dith6_mode.rs new file mode 100644 index 00000000000..fcbe0f6e31c --- /dev/null +++ b/pac/atsamda1g/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/perb.rs b/pac/atsamda1g/src/tcc0/perb.rs new file mode 100644 index 00000000000..6d3eb30c82d --- /dev/null +++ b/pac/atsamda1g/src/tcc0/perb.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb](index.html) module"] +pub struct PERB_SPEC; +impl crate::RegisterSpec for PERB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb::R](R) reader structure"] +impl crate::Readable for PERB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb::W](W) writer structure"] +impl crate::Writable for PERB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB to value 0xffff_ffff"] +impl crate::Resettable for PERB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/perb_dith4_mode.rs b/pac/atsamda1g/src/tcc0/perb_dith4_mode.rs new file mode 100644 index 00000000000..7781d12d911 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/perb_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith4_mode](index.html) module"] +pub struct PERB_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/perb_dith5_mode.rs b/pac/atsamda1g/src/tcc0/perb_dith5_mode.rs new file mode 100644 index 00000000000..e7364029ce2 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/perb_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith5_mode](index.html) module"] +pub struct PERB_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/perb_dith6_mode.rs b/pac/atsamda1g/src/tcc0/perb_dith6_mode.rs new file mode 100644 index 00000000000..0a780ae5f55 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/perb_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith6_mode](index.html) module"] +pub struct PERB_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1g/src/tcc0/status.rs b/pac/atsamda1g/src/tcc0/status.rs new file mode 100644 index 00000000000..15ea2088d08 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBV` reader - Pattern Buffer Valid"] +pub struct PATTBV_R(crate::FieldReader); +impl PATTBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBV` writer - Pattern Buffer Valid"] +pub struct PATTBV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `WAVEBV` reader - Wave Buffer Valid"] +pub struct WAVEBV_R(crate::FieldReader); +impl WAVEBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVEBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVEBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEBV` writer - Wave Buffer Valid"] +pub struct WAVEBV_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PERBV` reader - Period Buffer Valid"] +pub struct PERBV_R(crate::FieldReader); +impl PERBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBV` writer - Period Buffer Valid"] +pub struct PERBV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBV0_R(crate::FieldReader); +impl CCBV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBV1_R(crate::FieldReader); +impl CCBV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBV2_R(crate::FieldReader); +impl CCBV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBV3_R(crate::FieldReader); +impl CCBV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbv(&self) -> PATTBV_R { + PATTBV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Buffer Valid"] + #[inline(always)] + pub fn wavebv(&self) -> WAVEBV_R { + WAVEBV_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbv(&self) -> PERBV_R { + PERBV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbv0(&self) -> CCBV0_R { + CCBV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbv1(&self) -> CCBV1_R { + CCBV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbv2(&self) -> CCBV2_R { + CCBV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbv3(&self) -> CCBV3_R { + CCBV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbv(&mut self) -> PATTBV_W { + PATTBV_W { w: self } + } + #[doc = "Bit 6 - Wave Buffer Valid"] + #[inline(always)] + pub fn wavebv(&mut self) -> WAVEBV_W { + WAVEBV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbv(&mut self) -> PERBV_W { + PERBV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbv0(&mut self) -> CCBV0_W { + CCBV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbv1(&mut self) -> CCBV1_W { + CCBV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbv2(&mut self) -> CCBV2_W { + CCBV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbv3(&mut self) -> CCBV3_W { + CCBV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1g/src/tcc0/syncbusy.rs b/pac/atsamda1g/src/tcc0/syncbusy.rs new file mode 100644 index 00000000000..92f751789fd --- /dev/null +++ b/pac/atsamda1g/src/tcc0/syncbusy.rs @@ -0,0 +1,413 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTB` reader - Pattern Buffer Busy"] +pub struct PATTB_R(crate::FieldReader); +impl PATTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEB` reader - Wave Buffer Busy"] +pub struct WAVEB_R(crate::FieldReader); +impl WAVEB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVEB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVEB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` reader - Period Buffer Busy"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB0` reader - Compare Channel Buffer 0 Busy"] +pub struct CCB0_R(crate::FieldReader); +impl CCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB1` reader - Compare Channel Buffer 1 Busy"] +pub struct CCB1_R(crate::FieldReader); +impl CCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB2` reader - Compare Channel Buffer 2 Busy"] +pub struct CCB2_R(crate::FieldReader); +impl CCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB3` reader - Compare Channel Buffer 3 Busy"] +pub struct CCB3_R(crate::FieldReader); +impl CCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Pattern Buffer Busy"] + #[inline(always)] + pub fn pattb(&self) -> PATTB_R { + PATTB_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Wave Buffer Busy"] + #[inline(always)] + pub fn waveb(&self) -> WAVEB_R { + WAVEB_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Period Buffer Busy"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel Buffer 0 Busy"] + #[inline(always)] + pub fn ccb0(&self) -> CCB0_R { + CCB0_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Compare Channel Buffer 1 Busy"] + #[inline(always)] + pub fn ccb1(&self) -> CCB1_R { + CCB1_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Compare Channel Buffer 2 Busy"] + #[inline(always)] + pub fn ccb2(&self) -> CCB2_R { + CCB2_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Compare Channel Buffer 3 Busy"] + #[inline(always)] + pub fn ccb3(&self) -> CCB3_R { + CCB3_R::new(((self.bits >> 22) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/wave.rs b/pac/atsamda1g/src/tcc0/wave.rs new file mode 100644 index 00000000000..30602a3a4c6 --- /dev/null +++ b/pac/atsamda1g/src/tcc0/wave.rs @@ -0,0 +1,927 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RAMP_A::RAMP1), + 1 => Some(RAMP_A::RAMP2A), + 2 => Some(RAMP_A::RAMP2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/waveb.rs b/pac/atsamda1g/src/tcc0/waveb.rs new file mode 100644 index 00000000000..bfad858fc8f --- /dev/null +++ b/pac/atsamda1g/src/tcc0/waveb.rs @@ -0,0 +1,927 @@ +#[doc = "Register `WAVEB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVEB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGENB_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGENB_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGENB` reader - Waveform Generation Buffer"] +pub struct WAVEGENB_R(crate::FieldReader); +impl WAVEGENB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGENB_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGENB_A::NFRQ), + 1 => Some(WAVEGENB_A::MFRQ), + 2 => Some(WAVEGENB_A::NPWM), + 4 => Some(WAVEGENB_A::DSCRITICAL), + 5 => Some(WAVEGENB_A::DSBOTTOM), + 6 => Some(WAVEGENB_A::DSBOTH), + 7 => Some(WAVEGENB_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGENB_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGENB_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGENB_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGENB_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGENB_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGENB_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGENB_A::DSTOP + } +} +impl core::ops::Deref for WAVEGENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGENB` writer - Waveform Generation Buffer"] +pub struct WAVEGENB_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGENB_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGENB_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGENB_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGENB_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGENB_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode Buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMPB_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMPB_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMPB` reader - Ramp Mode Buffer"] +pub struct RAMPB_R(crate::FieldReader); +impl RAMPB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMPB_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RAMPB_A::RAMP1), + 1 => Some(RAMPB_A::RAMP2A), + 2 => Some(RAMPB_A::RAMP2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMPB_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMPB_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMPB_A::RAMP2 + } +} +impl core::ops::Deref for RAMPB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPB` writer - Ramp Mode Buffer"] +pub struct RAMPB_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPB_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMPB_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPERENB` reader - Circular Period Enable Buffer"] +pub struct CIPERENB_R(crate::FieldReader); +impl CIPERENB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPERENB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPERENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPERENB` writer - Circular Period Enable Buffer"] +pub struct CIPERENB_W<'a> { + w: &'a mut W, +} +impl<'a> CIPERENB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCENB0` reader - Circular Channel 0 Enable Buffer"] +pub struct CICCENB0_R(crate::FieldReader); +impl CICCENB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB0` writer - Circular Channel 0 Enable Buffer"] +pub struct CICCENB0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCENB1` reader - Circular Channel 1 Enable Buffer"] +pub struct CICCENB1_R(crate::FieldReader); +impl CICCENB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB1` writer - Circular Channel 1 Enable Buffer"] +pub struct CICCENB1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCENB2` reader - Circular Channel 2 Enable Buffer"] +pub struct CICCENB2_R(crate::FieldReader); +impl CICCENB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB2` writer - Circular Channel 2 Enable Buffer"] +pub struct CICCENB2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCENB3` reader - Circular Channel 3 Enable Buffer"] +pub struct CICCENB3_R(crate::FieldReader); +impl CICCENB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB3` writer - Circular Channel 3 Enable Buffer"] +pub struct CICCENB3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POLB0` reader - Channel 0 Polarity Buffer"] +pub struct POLB0_R(crate::FieldReader); +impl POLB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB0` writer - Channel 0 Polarity Buffer"] +pub struct POLB0_W<'a> { + w: &'a mut W, +} +impl<'a> POLB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POLB1` reader - Channel 1 Polarity Buffer"] +pub struct POLB1_R(crate::FieldReader); +impl POLB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB1` writer - Channel 1 Polarity Buffer"] +pub struct POLB1_W<'a> { + w: &'a mut W, +} +impl<'a> POLB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POLB2` reader - Channel 2 Polarity Buffer"] +pub struct POLB2_R(crate::FieldReader); +impl POLB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB2` writer - Channel 2 Polarity Buffer"] +pub struct POLB2_W<'a> { + w: &'a mut W, +} +impl<'a> POLB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POLB3` reader - Channel 3 Polarity Buffer"] +pub struct POLB3_R(crate::FieldReader); +impl POLB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB3` writer - Channel 3 Polarity Buffer"] +pub struct POLB3_W<'a> { + w: &'a mut W, +} +impl<'a> POLB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAPB0` reader - Swap DTI Output Pair 0 Buffer"] +pub struct SWAPB0_R(crate::FieldReader); +impl SWAPB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB0` writer - Swap DTI Output Pair 0 Buffer"] +pub struct SWAPB0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAPB1` reader - Swap DTI Output Pair 1 Buffer"] +pub struct SWAPB1_R(crate::FieldReader); +impl SWAPB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB1` writer - Swap DTI Output Pair 1 Buffer"] +pub struct SWAPB1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAPB2` reader - Swap DTI Output Pair 2 Buffer"] +pub struct SWAPB2_R(crate::FieldReader); +impl SWAPB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB2` writer - Swap DTI Output Pair 2 Buffer"] +pub struct SWAPB2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAPB3` reader - Swap DTI Output Pair 3 Buffer"] +pub struct SWAPB3_R(crate::FieldReader); +impl SWAPB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB3` writer - Swap DTI Output Pair 3 Buffer"] +pub struct SWAPB3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation Buffer"] + #[inline(always)] + pub fn wavegenb(&self) -> WAVEGENB_R { + WAVEGENB_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode Buffer"] + #[inline(always)] + pub fn rampb(&self) -> RAMPB_R { + RAMPB_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular Period Enable Buffer"] + #[inline(always)] + pub fn ciperenb(&self) -> CIPERENB_R { + CIPERENB_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable Buffer"] + #[inline(always)] + pub fn ciccenb0(&self) -> CICCENB0_R { + CICCENB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable Buffer"] + #[inline(always)] + pub fn ciccenb1(&self) -> CICCENB1_R { + CICCENB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable Buffer"] + #[inline(always)] + pub fn ciccenb2(&self) -> CICCENB2_R { + CICCENB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable Buffer"] + #[inline(always)] + pub fn ciccenb3(&self) -> CICCENB3_R { + CICCENB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity Buffer"] + #[inline(always)] + pub fn polb0(&self) -> POLB0_R { + POLB0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity Buffer"] + #[inline(always)] + pub fn polb1(&self) -> POLB1_R { + POLB1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity Buffer"] + #[inline(always)] + pub fn polb2(&self) -> POLB2_R { + POLB2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity Buffer"] + #[inline(always)] + pub fn polb3(&self) -> POLB3_R { + POLB3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0 Buffer"] + #[inline(always)] + pub fn swapb0(&self) -> SWAPB0_R { + SWAPB0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1 Buffer"] + #[inline(always)] + pub fn swapb1(&self) -> SWAPB1_R { + SWAPB1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2 Buffer"] + #[inline(always)] + pub fn swapb2(&self) -> SWAPB2_R { + SWAPB2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3 Buffer"] + #[inline(always)] + pub fn swapb3(&self) -> SWAPB3_R { + SWAPB3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation Buffer"] + #[inline(always)] + pub fn wavegenb(&mut self) -> WAVEGENB_W { + WAVEGENB_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode Buffer"] + #[inline(always)] + pub fn rampb(&mut self) -> RAMPB_W { + RAMPB_W { w: self } + } + #[doc = "Bit 7 - Circular Period Enable Buffer"] + #[inline(always)] + pub fn ciperenb(&mut self) -> CIPERENB_W { + CIPERENB_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable Buffer"] + #[inline(always)] + pub fn ciccenb0(&mut self) -> CICCENB0_W { + CICCENB0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable Buffer"] + #[inline(always)] + pub fn ciccenb1(&mut self) -> CICCENB1_W { + CICCENB1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable Buffer"] + #[inline(always)] + pub fn ciccenb2(&mut self) -> CICCENB2_W { + CICCENB2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable Buffer"] + #[inline(always)] + pub fn ciccenb3(&mut self) -> CICCENB3_W { + CICCENB3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity Buffer"] + #[inline(always)] + pub fn polb0(&mut self) -> POLB0_W { + POLB0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity Buffer"] + #[inline(always)] + pub fn polb1(&mut self) -> POLB1_W { + POLB1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity Buffer"] + #[inline(always)] + pub fn polb2(&mut self) -> POLB2_W { + POLB2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity Buffer"] + #[inline(always)] + pub fn polb3(&mut self) -> POLB3_W { + POLB3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0 Buffer"] + #[inline(always)] + pub fn swapb0(&mut self) -> SWAPB0_W { + SWAPB0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1 Buffer"] + #[inline(always)] + pub fn swapb1(&mut self) -> SWAPB1_W { + SWAPB1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2 Buffer"] + #[inline(always)] + pub fn swapb2(&mut self) -> SWAPB2_W { + SWAPB2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3 Buffer"] + #[inline(always)] + pub fn swapb3(&mut self) -> SWAPB3_W { + SWAPB3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [waveb](index.html) module"] +pub struct WAVEB_SPEC; +impl crate::RegisterSpec for WAVEB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [waveb::R](R) reader structure"] +impl crate::Readable for WAVEB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [waveb::W](W) writer structure"] +impl crate::Writable for WAVEB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVEB to value 0"] +impl crate::Resettable for WAVEB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/tcc0/wexctrl.rs b/pac/atsamda1g/src/tcc0/wexctrl.rs new file mode 100644 index 00000000000..8eb0d29cbee --- /dev/null +++ b/pac/atsamda1g/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb.rs b/pac/atsamda1g/src/usb.rs new file mode 100644 index 00000000000..22f33e47394 --- /dev/null +++ b/pac/atsamda1g/src/usb.rs @@ -0,0 +1,155 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_host: [u8; 0x01ea], +} +impl RegisterBlock { + #[doc = "0x00..0x1ea - USB is Host"] + #[inline(always)] + pub fn host(&self) -> &HOST { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const HOST) } + } + #[doc = "0x00..0x1ea - USB is Device"] + #[inline(always)] + pub fn device(&self) -> &DEVICE { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const DEVICE) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct DEVICE { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x03 - USB Quality Of Service"] + pub qosctrl: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - DEVICE Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x0a - DEVICE Device Address"] + pub dadd: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x0c - DEVICE Status"] + pub status: crate::Reg, + #[doc = "0x0d - Finite State Machine Status"] + pub fsmstatus: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x10 - DEVICE Device Frame Number"] + pub fnum: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x14 - DEVICE Device Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x18 - DEVICE Device Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x1c - DEVICE Device Interrupt Flag"] + pub intflag: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x20 - DEVICE End Point Interrupt Summary"] + pub epintsmry: crate::Reg, + _reserved12: [u8; 0x02], + #[doc = "0x24 - Descriptor Address"] + pub descadd: crate::Reg, + #[doc = "0x28 - USB PAD Calibration"] + pub padcal: crate::Reg, + _reserved14: [u8; 0xd6], + #[doc = "0x100..0x10a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint0: self::device::DEVICE_ENDPOINT, + _reserved15: [u8; 0x16], + #[doc = "0x120..0x12a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint1: self::device::DEVICE_ENDPOINT, + _reserved16: [u8; 0x16], + #[doc = "0x140..0x14a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint2: self::device::DEVICE_ENDPOINT, + _reserved17: [u8; 0x16], + #[doc = "0x160..0x16a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint3: self::device::DEVICE_ENDPOINT, + _reserved18: [u8; 0x16], + #[doc = "0x180..0x18a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint4: self::device::DEVICE_ENDPOINT, + _reserved19: [u8; 0x16], + #[doc = "0x1a0..0x1aa - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint5: self::device::DEVICE_ENDPOINT, + _reserved20: [u8; 0x16], + #[doc = "0x1c0..0x1ca - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint6: self::device::DEVICE_ENDPOINT, + _reserved21: [u8; 0x16], + #[doc = "0x1e0..0x1ea - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint7: self::device::DEVICE_ENDPOINT, +} +#[doc = r"Register block"] +#[doc = "USB is Device"] +pub mod device; +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x03 - USB Quality Of Service"] + pub qosctrl: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - HOST Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x0a - HOST Host Start Of Frame Control"] + pub hsofc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x0c - HOST Status"] + pub status: crate::Reg, + #[doc = "0x0d - Finite State Machine Status"] + pub fsmstatus: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x10 - HOST Host Frame Number"] + pub fnum: crate::Reg, + #[doc = "0x12 - HOST Host Frame Length"] + pub flenhigh: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x14 - HOST Host Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x18 - HOST Host Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x1c - HOST Host Interrupt Flag"] + pub intflag: crate::Reg, + _reserved12: [u8; 0x02], + #[doc = "0x20 - HOST Pipe Interrupt Summary"] + pub pintsmry: crate::Reg, + _reserved13: [u8; 0x02], + #[doc = "0x24 - Descriptor Address"] + pub descadd: crate::Reg, + #[doc = "0x28 - USB PAD Calibration"] + pub padcal: crate::Reg, + _reserved15: [u8; 0xd6], + #[doc = "0x100..0x10a - HOST_PIPE\\[%s\\]"] + pub host_pipe0: self::host::HOST_PIPE, + _reserved16: [u8; 0x16], + #[doc = "0x120..0x12a - HOST_PIPE\\[%s\\]"] + pub host_pipe1: self::host::HOST_PIPE, + _reserved17: [u8; 0x16], + #[doc = "0x140..0x14a - HOST_PIPE\\[%s\\]"] + pub host_pipe2: self::host::HOST_PIPE, + _reserved18: [u8; 0x16], + #[doc = "0x160..0x16a - HOST_PIPE\\[%s\\]"] + pub host_pipe3: self::host::HOST_PIPE, + _reserved19: [u8; 0x16], + #[doc = "0x180..0x18a - HOST_PIPE\\[%s\\]"] + pub host_pipe4: self::host::HOST_PIPE, + _reserved20: [u8; 0x16], + #[doc = "0x1a0..0x1aa - HOST_PIPE\\[%s\\]"] + pub host_pipe5: self::host::HOST_PIPE, + _reserved21: [u8; 0x16], + #[doc = "0x1c0..0x1ca - HOST_PIPE\\[%s\\]"] + pub host_pipe6: self::host::HOST_PIPE, + _reserved22: [u8; 0x16], + #[doc = "0x1e0..0x1ea - HOST_PIPE\\[%s\\]"] + pub host_pipe7: self::host::HOST_PIPE, +} +#[doc = r"Register block"] +#[doc = "USB is Host"] +pub mod host; diff --git a/pac/atsamda1g/src/usb/device.rs b/pac/atsamda1g/src/usb/device.rs new file mode 100644 index 00000000000..e5bbbadc1ca --- /dev/null +++ b/pac/atsamda1g/src/usb/device.rs @@ -0,0 +1,78 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "USB Quality Of Service"] +pub mod qosctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "DEVICE Control B"] +pub mod ctrlb; +#[doc = "DADD register accessor: an alias for `Reg`"] +pub type DADD = crate::Reg; +#[doc = "DEVICE Device Address"] +pub mod dadd; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "DEVICE Status"] +pub mod status; +#[doc = "FSMSTATUS register accessor: an alias for `Reg`"] +pub type FSMSTATUS = crate::Reg; +#[doc = "Finite State Machine Status"] +pub mod fsmstatus; +#[doc = "FNUM register accessor: an alias for `Reg`"] +pub type FNUM = crate::Reg; +#[doc = "DEVICE Device Frame Number"] +pub mod fnum; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "DEVICE Device Interrupt Flag"] +pub mod intflag; +#[doc = "EPINTSMRY register accessor: an alias for `Reg`"] +pub type EPINTSMRY = crate::Reg; +#[doc = "DEVICE End Point Interrupt Summary"] +pub mod epintsmry; +#[doc = "DESCADD register accessor: an alias for `Reg`"] +pub type DESCADD = crate::Reg; +#[doc = "Descriptor Address"] +pub mod descadd; +#[doc = "PADCAL register accessor: an alias for `Reg`"] +pub type PADCAL = crate::Reg; +#[doc = "USB PAD Calibration"] +pub mod padcal; +#[doc = r"Register block"] +#[repr(C)] +pub struct DEVICE_ENDPOINT { + #[doc = "0x00 - DEVICE_ENDPOINT End Point Configuration"] + pub epcfg: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - DEVICE_ENDPOINT End Point Pipe Status Clear"] + pub epstatusclr: crate::Reg, + #[doc = "0x05 - DEVICE_ENDPOINT End Point Pipe Status Set"] + pub epstatusset: crate::Reg, + #[doc = "0x06 - DEVICE_ENDPOINT End Point Pipe Status"] + pub epstatus: crate::Reg, + #[doc = "0x07 - DEVICE_ENDPOINT End Point Interrupt Flag"] + pub epintflag: crate::Reg, + #[doc = "0x08 - DEVICE_ENDPOINT End Point Interrupt Clear Flag"] + pub epintenclr: crate::Reg, + #[doc = "0x09 - DEVICE_ENDPOINT End Point Interrupt Set Flag"] + pub epintenset: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "DEVICE_ENDPOINT\\[%s\\]"] +pub mod device_endpoint; diff --git a/pac/atsamda1g/src/usb/device/ctrla.rs b/pac/atsamda1g/src/usb/device/ctrla.rs new file mode 100644 index 00000000000..f29253092ce --- /dev/null +++ b/pac/atsamda1g/src/usb/device/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby Mode"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby Mode"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Device Mode"] + DEVICE = 0, + #[doc = "1: Host Mode"] + HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::DEVICE, + true => MODE_A::HOST, + } + } + #[doc = "Checks if the value of the field is `DEVICE`"] + #[inline(always)] + pub fn is_device(&self) -> bool { + **self == MODE_A::DEVICE + } + #[doc = "Checks if the value of the field is `HOST`"] + #[inline(always)] + pub fn is_host(&self) -> bool { + **self == MODE_A::HOST + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Device Mode"] + #[inline(always)] + pub fn device(self) -> &'a mut W { + self.variant(MODE_A::DEVICE) + } + #[doc = "Host Mode"] + #[inline(always)] + pub fn host(self) -> &'a mut W { + self.variant(MODE_A::HOST) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/ctrlb.rs b/pac/atsamda1g/src/usb/device/ctrlb.rs new file mode 100644 index 00000000000..8c076e89255 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/ctrlb.rs @@ -0,0 +1,666 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DETACH` reader - Detach"] +pub struct DETACH_R(crate::FieldReader); +impl DETACH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DETACH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DETACH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DETACH` writer - Detach"] +pub struct DETACH_W<'a> { + w: &'a mut W, +} +impl<'a> DETACH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPDCONF_A { + #[doc = "0: FS : Full Speed"] + FS = 0, + #[doc = "1: LS : Low Speed"] + LS = 1, + #[doc = "2: HS : High Speed capable"] + HS = 2, + #[doc = "3: HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + HSTM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPDCONF_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPDCONF` reader - Speed Configuration"] +pub struct SPDCONF_R(crate::FieldReader); +impl SPDCONF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPDCONF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SPDCONF_A { + match self.bits { + 0 => SPDCONF_A::FS, + 1 => SPDCONF_A::LS, + 2 => SPDCONF_A::HS, + 3 => SPDCONF_A::HSTM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPDCONF_A::FS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + **self == SPDCONF_A::LS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + **self == SPDCONF_A::HS + } + #[doc = "Checks if the value of the field is `HSTM`"] + #[inline(always)] + pub fn is_hstm(&self) -> bool { + **self == SPDCONF_A::HSTM + } +} +impl core::ops::Deref for SPDCONF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPDCONF` writer - Speed Configuration"] +pub struct SPDCONF_W<'a> { + w: &'a mut W, +} +impl<'a> SPDCONF_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPDCONF_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "FS : Full Speed"] + #[inline(always)] + pub fn fs(self) -> &'a mut W { + self.variant(SPDCONF_A::FS) + } + #[doc = "LS : Low Speed"] + #[inline(always)] + pub fn ls(self) -> &'a mut W { + self.variant(SPDCONF_A::LS) + } + #[doc = "HS : High Speed capable"] + #[inline(always)] + pub fn hs(self) -> &'a mut W { + self.variant(SPDCONF_A::HS) + } + #[doc = "HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + #[inline(always)] + pub fn hstm(self) -> &'a mut W { + self.variant(SPDCONF_A::HSTM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `NREPLY` reader - No Reply"] +pub struct NREPLY_R(crate::FieldReader); +impl NREPLY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NREPLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NREPLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NREPLY` writer - No Reply"] +pub struct NREPLY_W<'a> { + w: &'a mut W, +} +impl<'a> NREPLY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TSTJ` reader - Test mode J"] +pub struct TSTJ_R(crate::FieldReader); +impl TSTJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTJ` writer - Test mode J"] +pub struct TSTJ_W<'a> { + w: &'a mut W, +} +impl<'a> TSTJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTK` reader - Test mode K"] +pub struct TSTK_R(crate::FieldReader); +impl TSTK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTK` writer - Test mode K"] +pub struct TSTK_W<'a> { + w: &'a mut W, +} +impl<'a> TSTK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TSTPCKT` reader - Test packet mode"] +pub struct TSTPCKT_R(crate::FieldReader); +impl TSTPCKT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTPCKT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTPCKT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTPCKT` writer - Test packet mode"] +pub struct TSTPCKT_W<'a> { + w: &'a mut W, +} +impl<'a> TSTPCKT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPMODE2` reader - Specific Operational Mode"] +pub struct OPMODE2_R(crate::FieldReader); +impl OPMODE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPMODE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPMODE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPMODE2` writer - Specific Operational Mode"] +pub struct OPMODE2_W<'a> { + w: &'a mut W, +} +impl<'a> OPMODE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GNAK` reader - Global NAK"] +pub struct GNAK_R(crate::FieldReader); +impl GNAK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GNAK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GNAK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GNAK` writer - Global NAK"] +pub struct GNAK_W<'a> { + w: &'a mut W, +} +impl<'a> GNAK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Link Power Management Handshake\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LPMHDSK_A { + #[doc = "0: No handshake. LPM is not supported"] + NO = 0, + #[doc = "1: ACK"] + ACK = 1, + #[doc = "2: NYET"] + NYET = 2, + #[doc = "3: STALL"] + STALL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LPMHDSK_A) -> Self { + variant as _ + } +} +#[doc = "Field `LPMHDSK` reader - Link Power Management Handshake"] +pub struct LPMHDSK_R(crate::FieldReader); +impl LPMHDSK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LPMHDSK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LPMHDSK_A { + match self.bits { + 0 => LPMHDSK_A::NO, + 1 => LPMHDSK_A::ACK, + 2 => LPMHDSK_A::NYET, + 3 => LPMHDSK_A::STALL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO`"] + #[inline(always)] + pub fn is_no(&self) -> bool { + **self == LPMHDSK_A::NO + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == LPMHDSK_A::ACK + } + #[doc = "Checks if the value of the field is `NYET`"] + #[inline(always)] + pub fn is_nyet(&self) -> bool { + **self == LPMHDSK_A::NYET + } + #[doc = "Checks if the value of the field is `STALL`"] + #[inline(always)] + pub fn is_stall(&self) -> bool { + **self == LPMHDSK_A::STALL + } +} +impl core::ops::Deref for LPMHDSK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMHDSK` writer - Link Power Management Handshake"] +pub struct LPMHDSK_W<'a> { + w: &'a mut W, +} +impl<'a> LPMHDSK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LPMHDSK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No handshake. LPM is not supported"] + #[inline(always)] + pub fn no(self) -> &'a mut W { + self.variant(LPMHDSK_A::NO) + } + #[doc = "ACK"] + #[inline(always)] + pub fn ack(self) -> &'a mut W { + self.variant(LPMHDSK_A::ACK) + } + #[doc = "NYET"] + #[inline(always)] + pub fn nyet(self) -> &'a mut W { + self.variant(LPMHDSK_A::NYET) + } + #[doc = "STALL"] + #[inline(always)] + pub fn stall(self) -> &'a mut W { + self.variant(LPMHDSK_A::STALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u16 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + pub fn detach(&self) -> DETACH_R { + DETACH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + pub fn spdconf(&self) -> SPDCONF_R { + SPDCONF_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + pub fn nreply(&self) -> NREPLY_R { + NREPLY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&self) -> TSTJ_R { + TSTJ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&self) -> TSTK_R { + TSTK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + pub fn tstpckt(&self) -> TSTPCKT_R { + TSTPCKT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + pub fn opmode2(&self) -> OPMODE2_R { + OPMODE2_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + pub fn gnak(&self) -> GNAK_R { + GNAK_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + pub fn lpmhdsk(&self) -> LPMHDSK_R { + LPMHDSK_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + pub fn detach(&mut self) -> DETACH_W { + DETACH_W { w: self } + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + pub fn spdconf(&mut self) -> SPDCONF_W { + SPDCONF_W { w: self } + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + pub fn nreply(&mut self) -> NREPLY_W { + NREPLY_W { w: self } + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&mut self) -> TSTJ_W { + TSTJ_W { w: self } + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&mut self) -> TSTK_W { + TSTK_W { w: self } + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + pub fn tstpckt(&mut self) -> TSTPCKT_W { + TSTPCKT_W { w: self } + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + pub fn opmode2(&mut self) -> OPMODE2_W { + OPMODE2_W { w: self } + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + pub fn gnak(&mut self) -> GNAK_W { + GNAK_W { w: self } + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + pub fn lpmhdsk(&mut self) -> LPMHDSK_W { + LPMHDSK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x01"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1g/src/usb/device/dadd.rs b/pac/atsamda1g/src/usb/device/dadd.rs new file mode 100644 index 00000000000..36cc57b728b --- /dev/null +++ b/pac/atsamda1g/src/usb/device/dadd.rs @@ -0,0 +1,150 @@ +#[doc = "Register `DADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DADD` reader - Device Address"] +pub struct DADD_R(crate::FieldReader); +impl DADD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DADD` writer - Device Address"] +pub struct DADD_W<'a> { + w: &'a mut W, +} +impl<'a> DADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `ADDEN` reader - Device Address Enable"] +pub struct ADDEN_R(crate::FieldReader); +impl ADDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDEN` writer - Device Address Enable"] +pub struct ADDEN_W<'a> { + w: &'a mut W, +} +impl<'a> ADDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + pub fn dadd(&self) -> DADD_R { + DADD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + pub fn adden(&self) -> ADDEN_R { + ADDEN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + pub fn dadd(&mut self) -> DADD_W { + DADD_W { w: self } + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + pub fn adden(&mut self) -> ADDEN_W { + ADDEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dadd](index.html) module"] +pub struct DADD_SPEC; +impl crate::RegisterSpec for DADD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dadd::R](R) reader structure"] +impl crate::Readable for DADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dadd::W](W) writer structure"] +impl crate::Writable for DADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DADD to value 0"] +impl crate::Resettable for DADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/descadd.rs b/pac/atsamda1g/src/usb/device/descadd.rs new file mode 100644 index 00000000000..9fe18a8dcb2 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/descadd.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DESCADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DESCADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCADD` reader - Descriptor Address Value"] +pub struct DESCADD_R(crate::FieldReader); +impl DESCADD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCADD` writer - Descriptor Address Value"] +pub struct DESCADD_W<'a> { + w: &'a mut W, +} +impl<'a> DESCADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&self) -> DESCADD_R { + DESCADD_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&mut self) -> DESCADD_W { + DESCADD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [descadd](index.html) module"] +pub struct DESCADD_SPEC; +impl crate::RegisterSpec for DESCADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [descadd::R](R) reader structure"] +impl crate::Readable for DESCADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [descadd::W](W) writer structure"] +impl crate::Writable for DESCADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DESCADD to value 0"] +impl crate::Resettable for DESCADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/device_endpoint.rs b/pac/atsamda1g/src/usb/device/device_endpoint.rs new file mode 100644 index 00000000000..b0722149fb9 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint.rs @@ -0,0 +1,28 @@ +#[doc = "EPCFG register accessor: an alias for `Reg`"] +pub type EPCFG = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Configuration"] +pub mod epcfg; +#[doc = "EPSTATUSCLR register accessor: an alias for `Reg`"] +pub type EPSTATUSCLR = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Clear"] +pub mod epstatusclr; +#[doc = "EPSTATUSSET register accessor: an alias for `Reg`"] +pub type EPSTATUSSET = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Set"] +pub mod epstatusset; +#[doc = "EPSTATUS register accessor: an alias for `Reg`"] +pub type EPSTATUS = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status"] +pub mod epstatus; +#[doc = "EPINTFLAG register accessor: an alias for `Reg`"] +pub type EPINTFLAG = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Flag"] +pub mod epintflag; +#[doc = "EPINTENCLR register accessor: an alias for `Reg`"] +pub type EPINTENCLR = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Clear Flag"] +pub mod epintenclr; +#[doc = "EPINTENSET register accessor: an alias for `Reg`"] +pub type EPINTENSET = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Set Flag"] +pub mod epintenset; diff --git a/pac/atsamda1g/src/usb/device/device_endpoint/epcfg.rs b/pac/atsamda1g/src/usb/device/device_endpoint/epcfg.rs new file mode 100644 index 00000000000..08d635693e7 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint/epcfg.rs @@ -0,0 +1,187 @@ +#[doc = "Register `EPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EPTYPE0` reader - End Point Type0"] +pub struct EPTYPE0_R(crate::FieldReader); +impl EPTYPE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EPTYPE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPTYPE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPTYPE0` writer - End Point Type0"] +pub struct EPTYPE0_W<'a> { + w: &'a mut W, +} +impl<'a> EPTYPE0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `EPTYPE1` reader - End Point Type1"] +pub struct EPTYPE1_R(crate::FieldReader); +impl EPTYPE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EPTYPE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPTYPE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPTYPE1` writer - End Point Type1"] +pub struct EPTYPE1_W<'a> { + w: &'a mut W, +} +impl<'a> EPTYPE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +#[doc = "Field `NYETDIS` reader - NYET Token Disable"] +pub struct NYETDIS_R(crate::FieldReader); +impl NYETDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NYETDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NYETDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NYETDIS` writer - NYET Token Disable"] +pub struct NYETDIS_W<'a> { + w: &'a mut W, +} +impl<'a> NYETDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + pub fn eptype0(&self) -> EPTYPE0_R { + EPTYPE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + pub fn eptype1(&self) -> EPTYPE1_R { + EPTYPE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + pub fn nyetdis(&self) -> NYETDIS_R { + NYETDIS_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + pub fn eptype0(&mut self) -> EPTYPE0_W { + EPTYPE0_W { w: self } + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + pub fn eptype1(&mut self) -> EPTYPE1_W { + EPTYPE1_W { w: self } + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + pub fn nyetdis(&mut self) -> NYETDIS_W { + NYETDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epcfg](index.html) module"] +pub struct EPCFG_SPEC; +impl crate::RegisterSpec for EPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epcfg::R](R) reader structure"] +impl crate::Readable for EPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epcfg::W](W) writer structure"] +impl crate::Writable for EPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPCFG to value 0"] +impl crate::Resettable for EPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/device_endpoint/epintenclr.rs b/pac/atsamda1g/src/usb/device/device_endpoint/epintenclr.rs new file mode 100644 index 00000000000..50e8a9188e4 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint/epintenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Disable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Disable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Disable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Disable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Disable"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Disable"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Disable"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Disable"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Disable"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Disable"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/Out Interrupt Disable"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/Out Interrupt Disable"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/Out Interrupt Disable"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/Out Interrupt Disable"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Clear Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenclr](index.html) module"] +pub struct EPINTENCLR_SPEC; +impl crate::RegisterSpec for EPINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenclr::R](R) reader structure"] +impl crate::Readable for EPINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenclr::W](W) writer structure"] +impl crate::Writable for EPINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTENCLR to value 0"] +impl crate::Resettable for EPINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/device_endpoint/epintenset.rs b/pac/atsamda1g/src/usb/device/device_endpoint/epintenset.rs new file mode 100644 index 00000000000..1df6b33a143 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint/epintenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Enable"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Enable"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Enable"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Enable"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Enable"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Enable"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/out Interrupt enable"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/out Interrupt enable"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/out Interrupt enable"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/out Interrupt enable"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Set Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenset](index.html) module"] +pub struct EPINTENSET_SPEC; +impl crate::RegisterSpec for EPINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenset::R](R) reader structure"] +impl crate::Readable for EPINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenset::W](W) writer structure"] +impl crate::Writable for EPINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTENSET to value 0"] +impl crate::Resettable for EPINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/device_endpoint/epintflag.rs b/pac/atsamda1g/src/usb/device/device_endpoint/epintflag.rs new file mode 100644 index 00000000000..8af2f8266fd --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint/epintflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/out"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/out"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/out"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/out"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintflag](index.html) module"] +pub struct EPINTFLAG_SPEC; +impl crate::RegisterSpec for EPINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintflag::R](R) reader structure"] +impl crate::Readable for EPINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintflag::W](W) writer structure"] +impl crate::Writable for EPINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTFLAG to value 0"] +impl crate::Resettable for EPINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/device_endpoint/epstatus.rs b/pac/atsamda1g/src/usb/device/device_endpoint/epstatus.rs new file mode 100644 index 00000000000..e5c544090f1 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint/epstatus.rs @@ -0,0 +1,173 @@ +#[doc = "Register `EPSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DTGLOUT` reader - Data Toggle Out"] +pub struct DTGLOUT_R(crate::FieldReader); +impl DTGLOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGLOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGLOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTGLIN` reader - Data Toggle In"] +pub struct DTGLIN_R(crate::FieldReader); +impl DTGLIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGLIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGLIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURBK` reader - Current Bank"] +pub struct CURBK_R(crate::FieldReader); +impl CURBK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CURBK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURBK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLRQ0` reader - Stall 0 Request"] +pub struct STALLRQ0_R(crate::FieldReader); +impl STALLRQ0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLRQ0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLRQ0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLRQ1` reader - Stall 1 Request"] +pub struct STALLRQ1_R(crate::FieldReader); +impl STALLRQ1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLRQ1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLRQ1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK0RDY` reader - Bank 0 ready"] +pub struct BK0RDY_R(crate::FieldReader); +impl BK0RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK0RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK0RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK1RDY` reader - Bank 1 ready"] +pub struct BK1RDY_R(crate::FieldReader); +impl BK1RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK1RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK1RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Data Toggle Out"] + #[inline(always)] + pub fn dtglout(&self) -> DTGLOUT_R { + DTGLOUT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Toggle In"] + #[inline(always)] + pub fn dtglin(&self) -> DTGLIN_R { + DTGLIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Current Bank"] + #[inline(always)] + pub fn curbk(&self) -> CURBK_R { + CURBK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Stall 0 Request"] + #[inline(always)] + pub fn stallrq0(&self) -> STALLRQ0_R { + STALLRQ0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 1 Request"] + #[inline(always)] + pub fn stallrq1(&self) -> STALLRQ1_R { + STALLRQ1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Bank 0 ready"] + #[inline(always)] + pub fn bk0rdy(&self) -> BK0RDY_R { + BK0RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bank 1 ready"] + #[inline(always)] + pub fn bk1rdy(&self) -> BK1RDY_R { + BK1RDY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatus](index.html) module"] +pub struct EPSTATUS_SPEC; +impl crate::RegisterSpec for EPSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epstatus::R](R) reader structure"] +impl crate::Readable for EPSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPSTATUS to value 0"] +impl crate::Resettable for EPSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/device_endpoint/epstatusclr.rs b/pac/atsamda1g/src/usb/device/device_endpoint/epstatusclr.rs new file mode 100644 index 00000000000..1c6a8b11556 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint/epstatusclr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `EPSTATUSCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Clear"] +pub struct DTGLOUT_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DTGLIN` writer - Data Toggle IN Clear"] +pub struct DTGLIN_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CURBK` writer - Curren Bank Clear"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Clear"] +pub struct STALLRQ0_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Clear"] +pub struct STALLRQ1_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Clear"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Clear"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle OUT Clear"] + #[inline(always)] + pub fn dtglout(&mut self) -> DTGLOUT_W { + DTGLOUT_W { w: self } + } + #[doc = "Bit 1 - Data Toggle IN Clear"] + #[inline(always)] + pub fn dtglin(&mut self) -> DTGLIN_W { + DTGLIN_W { w: self } + } + #[doc = "Bit 2 - Curren Bank Clear"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Stall 0 Request Clear"] + #[inline(always)] + pub fn stallrq0(&mut self) -> STALLRQ0_W { + STALLRQ0_W { w: self } + } + #[doc = "Bit 5 - Stall 1 Request Clear"] + #[inline(always)] + pub fn stallrq1(&mut self) -> STALLRQ1_W { + STALLRQ1_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Clear"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Clear"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusclr](index.html) module"] +pub struct EPSTATUSCLR_SPEC; +impl crate::RegisterSpec for EPSTATUSCLR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusclr::W](W) writer structure"] +impl crate::Writable for EPSTATUSCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPSTATUSCLR to value 0"] +impl crate::Resettable for EPSTATUSCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/device_endpoint/epstatusset.rs b/pac/atsamda1g/src/usb/device/device_endpoint/epstatusset.rs new file mode 100644 index 00000000000..a5bfce5a635 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/device_endpoint/epstatusset.rs @@ -0,0 +1,234 @@ +#[doc = "Register `EPSTATUSSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Set"] +pub struct DTGLOUT_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DTGLIN` writer - Data Toggle IN Set"] +pub struct DTGLIN_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CURBK` writer - Current Bank Set"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Set"] +pub struct STALLRQ0_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Set"] +pub struct STALLRQ1_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Set"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Set"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle OUT Set"] + #[inline(always)] + pub fn dtglout(&mut self) -> DTGLOUT_W { + DTGLOUT_W { w: self } + } + #[doc = "Bit 1 - Data Toggle IN Set"] + #[inline(always)] + pub fn dtglin(&mut self) -> DTGLIN_W { + DTGLIN_W { w: self } + } + #[doc = "Bit 2 - Current Bank Set"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Stall 0 Request Set"] + #[inline(always)] + pub fn stallrq0(&mut self) -> STALLRQ0_W { + STALLRQ0_W { w: self } + } + #[doc = "Bit 5 - Stall 1 Request Set"] + #[inline(always)] + pub fn stallrq1(&mut self) -> STALLRQ1_W { + STALLRQ1_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Set"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Set"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusset](index.html) module"] +pub struct EPSTATUSSET_SPEC; +impl crate::RegisterSpec for EPSTATUSSET_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusset::W](W) writer structure"] +impl crate::Writable for EPSTATUSSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPSTATUSSET to value 0"] +impl crate::Resettable for EPSTATUSSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/epintsmry.rs b/pac/atsamda1g/src/usb/device/epintsmry.rs new file mode 100644 index 00000000000..9b62c194598 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/epintsmry.rs @@ -0,0 +1,193 @@ +#[doc = "Register `EPINTSMRY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPINT0` reader - End Point 0 Interrupt"] +pub struct EPINT0_R(crate::FieldReader); +impl EPINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT1` reader - End Point 1 Interrupt"] +pub struct EPINT1_R(crate::FieldReader); +impl EPINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT2` reader - End Point 2 Interrupt"] +pub struct EPINT2_R(crate::FieldReader); +impl EPINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT3` reader - End Point 3 Interrupt"] +pub struct EPINT3_R(crate::FieldReader); +impl EPINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT4` reader - End Point 4 Interrupt"] +pub struct EPINT4_R(crate::FieldReader); +impl EPINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT5` reader - End Point 5 Interrupt"] +pub struct EPINT5_R(crate::FieldReader); +impl EPINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT6` reader - End Point 6 Interrupt"] +pub struct EPINT6_R(crate::FieldReader); +impl EPINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT7` reader - End Point 7 Interrupt"] +pub struct EPINT7_R(crate::FieldReader); +impl EPINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - End Point 0 Interrupt"] + #[inline(always)] + pub fn epint0(&self) -> EPINT0_R { + EPINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - End Point 1 Interrupt"] + #[inline(always)] + pub fn epint1(&self) -> EPINT1_R { + EPINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - End Point 2 Interrupt"] + #[inline(always)] + pub fn epint2(&self) -> EPINT2_R { + EPINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End Point 3 Interrupt"] + #[inline(always)] + pub fn epint3(&self) -> EPINT3_R { + EPINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - End Point 4 Interrupt"] + #[inline(always)] + pub fn epint4(&self) -> EPINT4_R { + EPINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Point 5 Interrupt"] + #[inline(always)] + pub fn epint5(&self) -> EPINT5_R { + EPINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - End Point 6 Interrupt"] + #[inline(always)] + pub fn epint6(&self) -> EPINT6_R { + EPINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - End Point 7 Interrupt"] + #[inline(always)] + pub fn epint7(&self) -> EPINT7_R { + EPINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "DEVICE End Point Interrupt Summary\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintsmry](index.html) module"] +pub struct EPINTSMRY_SPEC; +impl crate::RegisterSpec for EPINTSMRY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [epintsmry::R](R) reader structure"] +impl crate::Readable for EPINTSMRY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPINTSMRY to value 0"] +impl crate::Resettable for EPINTSMRY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/fnum.rs b/pac/atsamda1g/src/usb/device/fnum.rs new file mode 100644 index 00000000000..761148868fc --- /dev/null +++ b/pac/atsamda1g/src/usb/device/fnum.rs @@ -0,0 +1,93 @@ +#[doc = "Register `FNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MFNUM` reader - Micro Frame Number"] +pub struct MFNUM_R(crate::FieldReader); +impl MFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNUM` reader - Frame Number"] +pub struct FNUM_R(crate::FieldReader); +impl FNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNCERR` reader - Frame Number CRC Error"] +pub struct FNCERR_R(crate::FieldReader); +impl FNCERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FNCERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNCERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&self) -> MFNUM_R { + MFNUM_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&self) -> FNUM_R { + FNUM_R::new(((self.bits >> 3) & 0x07ff) as u16) + } + #[doc = "Bit 15 - Frame Number CRC Error"] + #[inline(always)] + pub fn fncerr(&self) -> FNCERR_R { + FNCERR_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "DEVICE Device Frame Number\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fnum](index.html) module"] +pub struct FNUM_SPEC; +impl crate::RegisterSpec for FNUM_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [fnum::R](R) reader structure"] +impl crate::Readable for FNUM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FNUM to value 0"] +impl crate::Resettable for FNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/fsmstatus.rs b/pac/atsamda1g/src/usb/device/fsmstatus.rs new file mode 100644 index 00000000000..a89e8172c39 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/fsmstatus.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FSMSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Fine State Machine Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSMSTATE_A { + #[doc = "1: OFF (L3). It corresponds to the powered-off, disconnected, and disabled state"] + OFF = 1, + #[doc = "2: ON (L0). It corresponds to the Idle and Active states"] + ON = 2, + #[doc = "4: SUSPEND (L2)"] + SUSPEND = 4, + #[doc = "8: SLEEP (L1)"] + SLEEP = 8, + #[doc = "16: DNRESUME. Down Stream Resume."] + DNRESUME = 16, + #[doc = "32: UPRESUME. Up Stream Resume."] + UPRESUME = 32, + #[doc = "64: RESET. USB lines Reset."] + RESET = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSMSTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSMSTATE` reader - Fine State Machine Status"] +pub struct FSMSTATE_R(crate::FieldReader); +impl FSMSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSMSTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(FSMSTATE_A::OFF), + 2 => Some(FSMSTATE_A::ON), + 4 => Some(FSMSTATE_A::SUSPEND), + 8 => Some(FSMSTATE_A::SLEEP), + 16 => Some(FSMSTATE_A::DNRESUME), + 32 => Some(FSMSTATE_A::UPRESUME), + 64 => Some(FSMSTATE_A::RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FSMSTATE_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + **self == FSMSTATE_A::ON + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == FSMSTATE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `SLEEP`"] + #[inline(always)] + pub fn is_sleep(&self) -> bool { + **self == FSMSTATE_A::SLEEP + } + #[doc = "Checks if the value of the field is `DNRESUME`"] + #[inline(always)] + pub fn is_dnresume(&self) -> bool { + **self == FSMSTATE_A::DNRESUME + } + #[doc = "Checks if the value of the field is `UPRESUME`"] + #[inline(always)] + pub fn is_upresume(&self) -> bool { + **self == FSMSTATE_A::UPRESUME + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == FSMSTATE_A::RESET + } +} +impl core::ops::Deref for FSMSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Fine State Machine Status"] + #[inline(always)] + pub fn fsmstate(&self) -> FSMSTATE_R { + FSMSTATE_R::new((self.bits & 0x7f) as u8) + } +} +#[doc = "Finite State Machine Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmstatus](index.html) module"] +pub struct FSMSTATUS_SPEC; +impl crate::RegisterSpec for FSMSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fsmstatus::R](R) reader structure"] +impl crate::Readable for FSMSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FSMSTATUS to value 0x01"] +impl crate::Resettable for FSMSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1g/src/usb/device/intenclr.rs b/pac/atsamda1g/src/usb/device/intenclr.rs new file mode 100644 index 00000000000..feffea27e6f --- /dev/null +++ b/pac/atsamda1g/src/usb/device/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/intenset.rs b/pac/atsamda1g/src/usb/device/intenset.rs new file mode 100644 index 00000000000..3f525c20e6a --- /dev/null +++ b/pac/atsamda1g/src/usb/device/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/intflag.rs b/pac/atsamda1g/src/usb/device/intflag.rs new file mode 100644 index 00000000000..1b52bfae973 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/padcal.rs b/pac/atsamda1g/src/usb/device/padcal.rs new file mode 100644 index 00000000000..9b11d4fc687 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/padcal.rs @@ -0,0 +1,177 @@ +#[doc = "Register `PADCAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PADCAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRANSP` reader - USB Pad Transp calibration"] +pub struct TRANSP_R(crate::FieldReader); +impl TRANSP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSP` writer - USB Pad Transp calibration"] +pub struct TRANSP_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `TRANSN` reader - USB Pad Transn calibration"] +pub struct TRANSN_R(crate::FieldReader); +impl TRANSN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSN` writer - USB Pad Transn calibration"] +pub struct TRANSN_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 6)) | ((value as u16 & 0x1f) << 6); + self.w + } +} +#[doc = "Field `TRIM` reader - USB Pad Trim calibration"] +pub struct TRIM_R(crate::FieldReader); +impl TRIM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIM` writer - USB Pad Trim calibration"] +pub struct TRIM_W<'a> { + w: &'a mut W, +} +impl<'a> TRIM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u16 & 0x07) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&self) -> TRANSP_R { + TRANSP_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&self) -> TRANSN_R { + TRANSN_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 12) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&mut self) -> TRANSP_W { + TRANSP_W { w: self } + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&mut self) -> TRANSN_W { + TRANSN_W { w: self } + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&mut self) -> TRIM_W { + TRIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB PAD Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [padcal](index.html) module"] +pub struct PADCAL_SPEC; +impl crate::RegisterSpec for PADCAL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [padcal::R](R) reader structure"] +impl crate::Readable for PADCAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [padcal::W](W) writer structure"] +impl crate::Writable for PADCAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PADCAL to value 0"] +impl crate::Resettable for PADCAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/device/qosctrl.rs b/pac/atsamda1g/src/usb/device/qosctrl.rs new file mode 100644 index 00000000000..86b85a16067 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/qosctrl.rs @@ -0,0 +1,290 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Configuration Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `CQOS` reader - Configuration Quality of Service"] +pub struct CQOS_R(crate::FieldReader); +impl CQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CQOS_A { + match self.bits { + 0 => CQOS_A::DISABLE, + 1 => CQOS_A::LOW, + 2 => CQOS_A::MEDIUM, + 3 => CQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == CQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == CQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == CQOS_A::HIGH + } +} +impl core::ops::Deref for CQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CQOS` writer - Configuration Quality of Service"] +pub struct CQOS_W<'a> { + w: &'a mut W, +} +impl<'a> CQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(CQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(CQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(CQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Data Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&self) -> CQOS_R { + CQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&mut self) -> CQOS_W { + CQOS_W { w: self } + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB Quality Of Service\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x05"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1g/src/usb/device/status.rs b/pac/atsamda1g/src/usb/device/status.rs new file mode 100644 index 00000000000..ef62be58537 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/status.rs @@ -0,0 +1,157 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Speed Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Full-speed mode"] + FS = 0, + #[doc = "1: High-speed mode"] + HS = 1, + #[doc = "2: Low-speed mode"] + LS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Status"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::FS), + 1 => Some(SPEED_A::HS), + 2 => Some(SPEED_A::LS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPEED_A::FS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + **self == SPEED_A::HS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + **self == SPEED_A::LS + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "USB Line State Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LINESTATE_A { + #[doc = "0: SE0/RESET"] + _0 = 0, + #[doc = "1: FS-J or LS-K State"] + _1 = 1, + #[doc = "2: FS-K or LS-J State"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LINESTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `LINESTATE` reader - USB Line State Status"] +pub struct LINESTATE_R(crate::FieldReader); +impl LINESTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINESTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LINESTATE_A::_0), + 1 => Some(LINESTATE_A::_1), + 2 => Some(LINESTATE_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == LINESTATE_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == LINESTATE_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == LINESTATE_A::_2 + } +} +impl core::ops::Deref for LINESTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&self) -> LINESTATE_R { + LINESTATE_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "DEVICE Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x40"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x40 + } +} diff --git a/pac/atsamda1g/src/usb/device/syncbusy.rs b/pac/atsamda1g/src/usb/device/syncbusy.rs new file mode 100644 index 00000000000..5f22af98954 --- /dev/null +++ b/pac/atsamda1g/src/usb/device/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host.rs b/pac/atsamda1g/src/usb/host.rs new file mode 100644 index 00000000000..4f2a018f914 --- /dev/null +++ b/pac/atsamda1g/src/usb/host.rs @@ -0,0 +1,84 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "USB Quality Of Service"] +pub mod qosctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "HOST Control B"] +pub mod ctrlb; +#[doc = "HSOFC register accessor: an alias for `Reg`"] +pub type HSOFC = crate::Reg; +#[doc = "HOST Host Start Of Frame Control"] +pub mod hsofc; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "HOST Status"] +pub mod status; +#[doc = "FSMSTATUS register accessor: an alias for `Reg`"] +pub type FSMSTATUS = crate::Reg; +#[doc = "Finite State Machine Status"] +pub mod fsmstatus; +#[doc = "FNUM register accessor: an alias for `Reg`"] +pub type FNUM = crate::Reg; +#[doc = "HOST Host Frame Number"] +pub mod fnum; +#[doc = "FLENHIGH register accessor: an alias for `Reg`"] +pub type FLENHIGH = crate::Reg; +#[doc = "HOST Host Frame Length"] +pub mod flenhigh; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "HOST Host Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "HOST Host Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "HOST Host Interrupt Flag"] +pub mod intflag; +#[doc = "PINTSMRY register accessor: an alias for `Reg`"] +pub type PINTSMRY = crate::Reg; +#[doc = "HOST Pipe Interrupt Summary"] +pub mod pintsmry; +#[doc = "DESCADD register accessor: an alias for `Reg`"] +pub type DESCADD = crate::Reg; +#[doc = "Descriptor Address"] +pub mod descadd; +#[doc = "PADCAL register accessor: an alias for `Reg`"] +pub type PADCAL = crate::Reg; +#[doc = "USB PAD Calibration"] +pub mod padcal; +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST_PIPE { + #[doc = "0x00 - HOST_PIPE End Point Configuration"] + pub pcfg: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x03 - HOST_PIPE Bus Access Period of Pipe"] + pub binterval: crate::Reg, + #[doc = "0x04 - HOST_PIPE End Point Pipe Status Clear"] + pub pstatusclr: crate::Reg, + #[doc = "0x05 - HOST_PIPE End Point Pipe Status Set"] + pub pstatusset: crate::Reg, + #[doc = "0x06 - HOST_PIPE End Point Pipe Status"] + pub pstatus: crate::Reg, + #[doc = "0x07 - HOST_PIPE Pipe Interrupt Flag"] + pub pintflag: crate::Reg, + #[doc = "0x08 - HOST_PIPE Pipe Interrupt Flag Clear"] + pub pintenclr: crate::Reg, + #[doc = "0x09 - HOST_PIPE Pipe Interrupt Flag Set"] + pub pintenset: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "HOST_PIPE\\[%s\\]"] +pub mod host_pipe; diff --git a/pac/atsamda1g/src/usb/host/ctrla.rs b/pac/atsamda1g/src/usb/host/ctrla.rs new file mode 100644 index 00000000000..f29253092ce --- /dev/null +++ b/pac/atsamda1g/src/usb/host/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby Mode"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby Mode"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Device Mode"] + DEVICE = 0, + #[doc = "1: Host Mode"] + HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::DEVICE, + true => MODE_A::HOST, + } + } + #[doc = "Checks if the value of the field is `DEVICE`"] + #[inline(always)] + pub fn is_device(&self) -> bool { + **self == MODE_A::DEVICE + } + #[doc = "Checks if the value of the field is `HOST`"] + #[inline(always)] + pub fn is_host(&self) -> bool { + **self == MODE_A::HOST + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Device Mode"] + #[inline(always)] + pub fn device(self) -> &'a mut W { + self.variant(MODE_A::DEVICE) + } + #[doc = "Host Mode"] + #[inline(always)] + pub fn host(self) -> &'a mut W { + self.variant(MODE_A::HOST) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/ctrlb.rs b/pac/atsamda1g/src/usb/host/ctrlb.rs new file mode 100644 index 00000000000..59536faa219 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/ctrlb.rs @@ -0,0 +1,481 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESUME` reader - Send USB Resume"] +pub struct RESUME_R(crate::FieldReader); +impl RESUME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESUME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESUME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESUME` writer - Send USB Resume"] +pub struct RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Configuration for Host\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPDCONF_A { + #[doc = "0: Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable."] + NORMAL = 0, + #[doc = "3: Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only."] + FS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPDCONF_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPDCONF` reader - Speed Configuration for Host"] +pub struct SPDCONF_R(crate::FieldReader); +impl SPDCONF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPDCONF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPDCONF_A::NORMAL), + 3 => Some(SPDCONF_A::FS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NORMAL`"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + **self == SPDCONF_A::NORMAL + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPDCONF_A::FS + } +} +impl core::ops::Deref for SPDCONF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPDCONF` writer - Speed Configuration for Host"] +pub struct SPDCONF_W<'a> { + w: &'a mut W, +} +impl<'a> SPDCONF_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPDCONF_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable."] + #[inline(always)] + pub fn normal(self) -> &'a mut W { + self.variant(SPDCONF_A::NORMAL) + } + #[doc = "Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only."] + #[inline(always)] + pub fn fs(self) -> &'a mut W { + self.variant(SPDCONF_A::FS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `TSTJ` reader - Test mode J"] +pub struct TSTJ_R(crate::FieldReader); +impl TSTJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTJ` writer - Test mode J"] +pub struct TSTJ_W<'a> { + w: &'a mut W, +} +impl<'a> TSTJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTK` reader - Test mode K"] +pub struct TSTK_R(crate::FieldReader); +impl TSTK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTK` writer - Test mode K"] +pub struct TSTK_W<'a> { + w: &'a mut W, +} +impl<'a> TSTK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SOFE` reader - Start of Frame Generation Enable"] +pub struct SOFE_R(crate::FieldReader); +impl SOFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOFE` writer - Start of Frame Generation Enable"] +pub struct SOFE_W<'a> { + w: &'a mut W, +} +impl<'a> SOFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BUSRESET` reader - Send USB Reset"] +pub struct BUSRESET_R(crate::FieldReader); +impl BUSRESET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSRESET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSRESET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSRESET` writer - Send USB Reset"] +pub struct BUSRESET_W<'a> { + w: &'a mut W, +} +impl<'a> BUSRESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `VBUSOK` reader - VBUS is OK"] +pub struct VBUSOK_R(crate::FieldReader); +impl VBUSOK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VBUSOK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VBUSOK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VBUSOK` writer - VBUS is OK"] +pub struct VBUSOK_W<'a> { + w: &'a mut W, +} +impl<'a> VBUSOK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `L1RESUME` reader - Send L1 Resume"] +pub struct L1RESUME_R(crate::FieldReader); +impl L1RESUME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + L1RESUME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for L1RESUME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `L1RESUME` writer - Send L1 Resume"] +pub struct L1RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> L1RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 1 - Send USB Resume"] + #[inline(always)] + pub fn resume(&self) -> RESUME_R { + RESUME_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Configuration for Host"] + #[inline(always)] + pub fn spdconf(&self) -> SPDCONF_R { + SPDCONF_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&self) -> TSTJ_R { + TSTJ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&self) -> TSTK_R { + TSTK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Start of Frame Generation Enable"] + #[inline(always)] + pub fn sofe(&self) -> SOFE_R { + SOFE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Send USB Reset"] + #[inline(always)] + pub fn busreset(&self) -> BUSRESET_R { + BUSRESET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - VBUS is OK"] + #[inline(always)] + pub fn vbusok(&self) -> VBUSOK_R { + VBUSOK_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Send L1 Resume"] + #[inline(always)] + pub fn l1resume(&self) -> L1RESUME_R { + L1RESUME_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Send USB Resume"] + #[inline(always)] + pub fn resume(&mut self) -> RESUME_W { + RESUME_W { w: self } + } + #[doc = "Bits 2:3 - Speed Configuration for Host"] + #[inline(always)] + pub fn spdconf(&mut self) -> SPDCONF_W { + SPDCONF_W { w: self } + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&mut self) -> TSTJ_W { + TSTJ_W { w: self } + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&mut self) -> TSTK_W { + TSTK_W { w: self } + } + #[doc = "Bit 8 - Start of Frame Generation Enable"] + #[inline(always)] + pub fn sofe(&mut self) -> SOFE_W { + SOFE_W { w: self } + } + #[doc = "Bit 9 - Send USB Reset"] + #[inline(always)] + pub fn busreset(&mut self) -> BUSRESET_W { + BUSRESET_W { w: self } + } + #[doc = "Bit 10 - VBUS is OK"] + #[inline(always)] + pub fn vbusok(&mut self) -> VBUSOK_W { + VBUSOK_W { w: self } + } + #[doc = "Bit 11 - Send L1 Resume"] + #[inline(always)] + pub fn l1resume(&mut self) -> L1RESUME_W { + L1RESUME_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/descadd.rs b/pac/atsamda1g/src/usb/host/descadd.rs new file mode 100644 index 00000000000..9fe18a8dcb2 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/descadd.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DESCADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DESCADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCADD` reader - Descriptor Address Value"] +pub struct DESCADD_R(crate::FieldReader); +impl DESCADD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCADD` writer - Descriptor Address Value"] +pub struct DESCADD_W<'a> { + w: &'a mut W, +} +impl<'a> DESCADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&self) -> DESCADD_R { + DESCADD_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&mut self) -> DESCADD_W { + DESCADD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [descadd](index.html) module"] +pub struct DESCADD_SPEC; +impl crate::RegisterSpec for DESCADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [descadd::R](R) reader structure"] +impl crate::Readable for DESCADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [descadd::W](W) writer structure"] +impl crate::Writable for DESCADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DESCADD to value 0"] +impl crate::Resettable for DESCADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/flenhigh.rs b/pac/atsamda1g/src/usb/host/flenhigh.rs new file mode 100644 index 00000000000..ab9d58be29b --- /dev/null +++ b/pac/atsamda1g/src/usb/host/flenhigh.rs @@ -0,0 +1,53 @@ +#[doc = "Register `FLENHIGH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FLENHIGH` reader - Frame Length"] +pub struct FLENHIGH_R(crate::FieldReader); +impl FLENHIGH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLENHIGH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENHIGH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Frame Length"] + #[inline(always)] + pub fn flenhigh(&self) -> FLENHIGH_R { + FLENHIGH_R::new(self.bits as u8) + } +} +#[doc = "HOST Host Frame Length\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flenhigh](index.html) module"] +pub struct FLENHIGH_SPEC; +impl crate::RegisterSpec for FLENHIGH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [flenhigh::R](R) reader structure"] +impl crate::Readable for FLENHIGH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FLENHIGH to value 0"] +impl crate::Resettable for FLENHIGH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/fnum.rs b/pac/atsamda1g/src/usb/host/fnum.rs new file mode 100644 index 00000000000..cc5f2b47dce --- /dev/null +++ b/pac/atsamda1g/src/usb/host/fnum.rs @@ -0,0 +1,140 @@ +#[doc = "Register `FNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MFNUM` reader - Micro Frame Number"] +pub struct MFNUM_R(crate::FieldReader); +impl MFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MFNUM` writer - Micro Frame Number"] +pub struct MFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> MFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `FNUM` reader - Frame Number"] +pub struct FNUM_R(crate::FieldReader); +impl FNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNUM` writer - Frame Number"] +pub struct FNUM_W<'a> { + w: &'a mut W, +} +impl<'a> FNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 3)) | ((value as u16 & 0x07ff) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&self) -> MFNUM_R { + MFNUM_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&self) -> FNUM_R { + FNUM_R::new(((self.bits >> 3) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&mut self) -> MFNUM_W { + MFNUM_W { w: self } + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&mut self) -> FNUM_W { + FNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Frame Number\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fnum](index.html) module"] +pub struct FNUM_SPEC; +impl crate::RegisterSpec for FNUM_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [fnum::R](R) reader structure"] +impl crate::Readable for FNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fnum::W](W) writer structure"] +impl crate::Writable for FNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FNUM to value 0"] +impl crate::Resettable for FNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/fsmstatus.rs b/pac/atsamda1g/src/usb/host/fsmstatus.rs new file mode 100644 index 00000000000..a89e8172c39 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/fsmstatus.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FSMSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Fine State Machine Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSMSTATE_A { + #[doc = "1: OFF (L3). It corresponds to the powered-off, disconnected, and disabled state"] + OFF = 1, + #[doc = "2: ON (L0). It corresponds to the Idle and Active states"] + ON = 2, + #[doc = "4: SUSPEND (L2)"] + SUSPEND = 4, + #[doc = "8: SLEEP (L1)"] + SLEEP = 8, + #[doc = "16: DNRESUME. Down Stream Resume."] + DNRESUME = 16, + #[doc = "32: UPRESUME. Up Stream Resume."] + UPRESUME = 32, + #[doc = "64: RESET. USB lines Reset."] + RESET = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSMSTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSMSTATE` reader - Fine State Machine Status"] +pub struct FSMSTATE_R(crate::FieldReader); +impl FSMSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSMSTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(FSMSTATE_A::OFF), + 2 => Some(FSMSTATE_A::ON), + 4 => Some(FSMSTATE_A::SUSPEND), + 8 => Some(FSMSTATE_A::SLEEP), + 16 => Some(FSMSTATE_A::DNRESUME), + 32 => Some(FSMSTATE_A::UPRESUME), + 64 => Some(FSMSTATE_A::RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FSMSTATE_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + **self == FSMSTATE_A::ON + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == FSMSTATE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `SLEEP`"] + #[inline(always)] + pub fn is_sleep(&self) -> bool { + **self == FSMSTATE_A::SLEEP + } + #[doc = "Checks if the value of the field is `DNRESUME`"] + #[inline(always)] + pub fn is_dnresume(&self) -> bool { + **self == FSMSTATE_A::DNRESUME + } + #[doc = "Checks if the value of the field is `UPRESUME`"] + #[inline(always)] + pub fn is_upresume(&self) -> bool { + **self == FSMSTATE_A::UPRESUME + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == FSMSTATE_A::RESET + } +} +impl core::ops::Deref for FSMSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Fine State Machine Status"] + #[inline(always)] + pub fn fsmstate(&self) -> FSMSTATE_R { + FSMSTATE_R::new((self.bits & 0x7f) as u8) + } +} +#[doc = "Finite State Machine Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmstatus](index.html) module"] +pub struct FSMSTATUS_SPEC; +impl crate::RegisterSpec for FSMSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fsmstatus::R](R) reader structure"] +impl crate::Readable for FSMSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FSMSTATUS to value 0x01"] +impl crate::Resettable for FSMSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe.rs b/pac/atsamda1g/src/usb/host/host_pipe.rs new file mode 100644 index 00000000000..e0a917f3a12 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe.rs @@ -0,0 +1,32 @@ +#[doc = "PCFG register accessor: an alias for `Reg`"] +pub type PCFG = crate::Reg; +#[doc = "HOST_PIPE End Point Configuration"] +pub mod pcfg; +#[doc = "BINTERVAL register accessor: an alias for `Reg`"] +pub type BINTERVAL = crate::Reg; +#[doc = "HOST_PIPE Bus Access Period of Pipe"] +pub mod binterval; +#[doc = "PSTATUSCLR register accessor: an alias for `Reg`"] +pub type PSTATUSCLR = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status Clear"] +pub mod pstatusclr; +#[doc = "PSTATUSSET register accessor: an alias for `Reg`"] +pub type PSTATUSSET = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status Set"] +pub mod pstatusset; +#[doc = "PSTATUS register accessor: an alias for `Reg`"] +pub type PSTATUS = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status"] +pub mod pstatus; +#[doc = "PINTFLAG register accessor: an alias for `Reg`"] +pub type PINTFLAG = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag"] +pub mod pintflag; +#[doc = "PINTENCLR register accessor: an alias for `Reg`"] +pub type PINTENCLR = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag Clear"] +pub mod pintenclr; +#[doc = "PINTENSET register accessor: an alias for `Reg`"] +pub type PINTENSET = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag Set"] +pub mod pintenset; diff --git a/pac/atsamda1g/src/usb/host/host_pipe/binterval.rs b/pac/atsamda1g/src/usb/host/host_pipe/binterval.rs new file mode 100644 index 00000000000..7b29db1e3d6 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/binterval.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BINTERVAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BINTERVAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BITINTERVAL` reader - Bit Interval"] +pub struct BITINTERVAL_R(crate::FieldReader); +impl BITINTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BITINTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BITINTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITINTERVAL` writer - Bit Interval"] +pub struct BITINTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BITINTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Bit Interval"] + #[inline(always)] + pub fn bitinterval(&self) -> BITINTERVAL_R { + BITINTERVAL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Bit Interval"] + #[inline(always)] + pub fn bitinterval(&mut self) -> BITINTERVAL_W { + BITINTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Bus Access Period of Pipe\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [binterval](index.html) module"] +pub struct BINTERVAL_SPEC; +impl crate::RegisterSpec for BINTERVAL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [binterval::R](R) reader structure"] +impl crate::Readable for BINTERVAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [binterval::W](W) writer structure"] +impl crate::Writable for BINTERVAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BINTERVAL to value 0"] +impl crate::Resettable for BINTERVAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe/pcfg.rs b/pac/atsamda1g/src/usb/host/host_pipe/pcfg.rs new file mode 100644 index 00000000000..c6677dce494 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/pcfg.rs @@ -0,0 +1,187 @@ +#[doc = "Register `PCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTOKEN` reader - Pipe Token"] +pub struct PTOKEN_R(crate::FieldReader); +impl PTOKEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PTOKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTOKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTOKEN` writer - Pipe Token"] +pub struct PTOKEN_W<'a> { + w: &'a mut W, +} +impl<'a> PTOKEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Field `BK` reader - Pipe Bank"] +pub struct BK_R(crate::FieldReader); +impl BK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK` writer - Pipe Bank"] +pub struct BK_W<'a> { + w: &'a mut W, +} +impl<'a> BK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PTYPE` reader - Pipe Type"] +pub struct PTYPE_R(crate::FieldReader); +impl PTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PTYPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTYPE` writer - Pipe Type"] +pub struct PTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> PTYPE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u8 & 0x07) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Pipe Token"] + #[inline(always)] + pub fn ptoken(&self) -> PTOKEN_R { + PTOKEN_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Pipe Bank"] + #[inline(always)] + pub fn bk(&self) -> BK_R { + BK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:5 - Pipe Type"] + #[inline(always)] + pub fn ptype(&self) -> PTYPE_R { + PTYPE_R::new(((self.bits >> 3) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Pipe Token"] + #[inline(always)] + pub fn ptoken(&mut self) -> PTOKEN_W { + PTOKEN_W { w: self } + } + #[doc = "Bit 2 - Pipe Bank"] + #[inline(always)] + pub fn bk(&mut self) -> BK_W { + BK_W { w: self } + } + #[doc = "Bits 3:5 - Pipe Type"] + #[inline(always)] + pub fn ptype(&mut self) -> PTYPE_W { + PTYPE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcfg](index.html) module"] +pub struct PCFG_SPEC; +impl crate::RegisterSpec for PCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pcfg::R](R) reader structure"] +impl crate::Readable for PCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pcfg::W](W) writer structure"] +impl crate::Writable for PCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCFG to value 0"] +impl crate::Resettable for PCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe/pintenclr.rs b/pac/atsamda1g/src/usb/host/host_pipe/pintenclr.rs new file mode 100644 index 00000000000..d994194d579 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/pintenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Disable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Disable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Disable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Disable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Disable"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Disable"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Disable"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Disable"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Disable"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Disable"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Disable"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Disable"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Disable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Disable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Disable"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Disable"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Disable"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Disable"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Disable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Disable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Disable"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Disable"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Disable"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Disable"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintenclr](index.html) module"] +pub struct PINTENCLR_SPEC; +impl crate::RegisterSpec for PINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintenclr::R](R) reader structure"] +impl crate::Readable for PINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintenclr::W](W) writer structure"] +impl crate::Writable for PINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTENCLR to value 0"] +impl crate::Resettable for PINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe/pintenset.rs b/pac/atsamda1g/src/usb/host/host_pipe/pintenset.rs new file mode 100644 index 00000000000..fc7368fe117 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/pintenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Enable"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Enable"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Enable"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Enable"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Enable"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Enable"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Enable"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Enable"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Enable"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Enable"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Enable"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Enable"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Enable"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Enable"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Enable"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Enable"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintenset](index.html) module"] +pub struct PINTENSET_SPEC; +impl crate::RegisterSpec for PINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintenset::R](R) reader structure"] +impl crate::Readable for PINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintenset::W](W) writer structure"] +impl crate::Writable for PINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTENSET to value 0"] +impl crate::Resettable for PINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe/pintflag.rs b/pac/atsamda1g/src/usb/host/host_pipe/pintflag.rs new file mode 100644 index 00000000000..9724af9984c --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/pintflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Flag"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Flag"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Flag"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Flag"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Flag"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Flag"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Flag"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Flag"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Flag"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Flag"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Flag"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Flag"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Flag"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Flag"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Flag"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Flag"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Flag"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Flag"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Flag"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Flag"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Flag"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Flag"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintflag](index.html) module"] +pub struct PINTFLAG_SPEC; +impl crate::RegisterSpec for PINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintflag::R](R) reader structure"] +impl crate::Readable for PINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintflag::W](W) writer structure"] +impl crate::Writable for PINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTFLAG to value 0"] +impl crate::Resettable for PINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe/pstatus.rs b/pac/atsamda1g/src/usb/host/host_pipe/pstatus.rs new file mode 100644 index 00000000000..072b3621ff5 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/pstatus.rs @@ -0,0 +1,133 @@ +#[doc = "Register `PSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DTGL` reader - Data Toggle"] +pub struct DTGL_R(crate::FieldReader); +impl DTGL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURBK` reader - Current Bank"] +pub struct CURBK_R(crate::FieldReader); +impl CURBK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CURBK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURBK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PFREEZE` reader - Pipe Freeze"] +pub struct PFREEZE_R(crate::FieldReader); +impl PFREEZE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PFREEZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PFREEZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK0RDY` reader - Bank 0 ready"] +pub struct BK0RDY_R(crate::FieldReader); +impl BK0RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK0RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK0RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK1RDY` reader - Bank 1 ready"] +pub struct BK1RDY_R(crate::FieldReader); +impl BK1RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK1RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK1RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Data Toggle"] + #[inline(always)] + pub fn dtgl(&self) -> DTGL_R { + DTGL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Current Bank"] + #[inline(always)] + pub fn curbk(&self) -> CURBK_R { + CURBK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Pipe Freeze"] + #[inline(always)] + pub fn pfreeze(&self) -> PFREEZE_R { + PFREEZE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Bank 0 ready"] + #[inline(always)] + pub fn bk0rdy(&self) -> BK0RDY_R { + BK0RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bank 1 ready"] + #[inline(always)] + pub fn bk1rdy(&self) -> BK1RDY_R { + BK1RDY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "HOST_PIPE End Point Pipe Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatus](index.html) module"] +pub struct PSTATUS_SPEC; +impl crate::RegisterSpec for PSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pstatus::R](R) reader structure"] +impl crate::Readable for PSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PSTATUS to value 0"] +impl crate::Resettable for PSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe/pstatusclr.rs b/pac/atsamda1g/src/usb/host/host_pipe/pstatusclr.rs new file mode 100644 index 00000000000..6fb40667a9d --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/pstatusclr.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PSTATUSCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGL` writer - Data Toggle clear"] +pub struct DTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DTGL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CURBK` writer - Curren Bank clear"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PFREEZE` writer - Pipe Freeze Clear"] +pub struct PFREEZE_W<'a> { + w: &'a mut W, +} +impl<'a> PFREEZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Clear"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Clear"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle clear"] + #[inline(always)] + pub fn dtgl(&mut self) -> DTGL_W { + DTGL_W { w: self } + } + #[doc = "Bit 2 - Curren Bank clear"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Pipe Freeze Clear"] + #[inline(always)] + pub fn pfreeze(&mut self) -> PFREEZE_W { + PFREEZE_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Clear"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Clear"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Pipe Status Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatusclr](index.html) module"] +pub struct PSTATUSCLR_SPEC; +impl crate::RegisterSpec for PSTATUSCLR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [pstatusclr::W](W) writer structure"] +impl crate::Writable for PSTATUSCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSTATUSCLR to value 0"] +impl crate::Resettable for PSTATUSCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/host_pipe/pstatusset.rs b/pac/atsamda1g/src/usb/host/host_pipe/pstatusset.rs new file mode 100644 index 00000000000..2d3e855e41f --- /dev/null +++ b/pac/atsamda1g/src/usb/host/host_pipe/pstatusset.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PSTATUSSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGL` writer - Data Toggle Set"] +pub struct DTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DTGL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CURBK` writer - Current Bank Set"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PFREEZE` writer - Pipe Freeze Set"] +pub struct PFREEZE_W<'a> { + w: &'a mut W, +} +impl<'a> PFREEZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Set"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Set"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle Set"] + #[inline(always)] + pub fn dtgl(&mut self) -> DTGL_W { + DTGL_W { w: self } + } + #[doc = "Bit 2 - Current Bank Set"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Pipe Freeze Set"] + #[inline(always)] + pub fn pfreeze(&mut self) -> PFREEZE_W { + PFREEZE_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Set"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Set"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Pipe Status Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatusset](index.html) module"] +pub struct PSTATUSSET_SPEC; +impl crate::RegisterSpec for PSTATUSSET_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [pstatusset::W](W) writer structure"] +impl crate::Writable for PSTATUSSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSTATUSSET to value 0"] +impl crate::Resettable for PSTATUSSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/hsofc.rs b/pac/atsamda1g/src/usb/host/hsofc.rs new file mode 100644 index 00000000000..bc714a862ff --- /dev/null +++ b/pac/atsamda1g/src/usb/host/hsofc.rs @@ -0,0 +1,150 @@ +#[doc = "Register `HSOFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HSOFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLENC` reader - Frame Length Control"] +pub struct FLENC_R(crate::FieldReader); +impl FLENC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLENC` writer - Frame Length Control"] +pub struct FLENC_W<'a> { + w: &'a mut W, +} +impl<'a> FLENC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `FLENCE` reader - Frame Length Control Enable"] +pub struct FLENCE_R(crate::FieldReader); +impl FLENCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLENCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLENCE` writer - Frame Length Control Enable"] +pub struct FLENCE_W<'a> { + w: &'a mut W, +} +impl<'a> FLENCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Frame Length Control"] + #[inline(always)] + pub fn flenc(&self) -> FLENC_R { + FLENC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Frame Length Control Enable"] + #[inline(always)] + pub fn flence(&self) -> FLENCE_R { + FLENCE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Frame Length Control"] + #[inline(always)] + pub fn flenc(&mut self) -> FLENC_W { + FLENC_W { w: self } + } + #[doc = "Bit 7 - Frame Length Control Enable"] + #[inline(always)] + pub fn flence(&mut self) -> FLENCE_W { + FLENCE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Start Of Frame Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hsofc](index.html) module"] +pub struct HSOFC_SPEC; +impl crate::RegisterSpec for HSOFC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [hsofc::R](R) reader structure"] +impl crate::Readable for HSOFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hsofc::W](W) writer structure"] +impl crate::Writable for HSOFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HSOFC to value 0"] +impl crate::Resettable for HSOFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/intenclr.rs b/pac/atsamda1g/src/usb/host/intenclr.rs new file mode 100644 index 00000000000..df6a7c7b78e --- /dev/null +++ b/pac/atsamda1g/src/usb/host/intenclr.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Disable"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Disable"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - BUS Reset Interrupt Disable"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - BUS Reset Interrupt Disable"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Disable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Disable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - DownStream to Device Interrupt Disable"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - DownStream to Device Interrupt Disable"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume from Device Interrupt Disable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume from Device Interrupt Disable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Disable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Disable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Device Connection Interrupt Disable"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Device Connection Interrupt Disable"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Disable"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Disable"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BUS Reset Interrupt Disable"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Disable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Disable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Device Connection Interrupt Disable"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - BUS Reset Interrupt Disable"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Disable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Disable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Device Connection Interrupt Disable"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/intenset.rs b/pac/atsamda1g/src/usb/host/intenset.rs new file mode 100644 index 00000000000..dce5e3a61f7 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/intenset.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Enable"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Enable"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - Bus Reset Interrupt Enable"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - Bus Reset Interrupt Enable"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - DownStream to the Device Interrupt Enable"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - DownStream to the Device Interrupt Enable"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume fromthe device Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume fromthe device Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Link Power Management Interrupt Enable"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Link Power Management Interrupt Enable"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Enable"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Enable"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Bus Reset Interrupt Enable"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DownStream to the Device Interrupt Enable"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume fromthe device Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Interrupt Enable"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection Interrupt Enable"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - Bus Reset Interrupt Enable"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - DownStream to the Device Interrupt Enable"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume fromthe device Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Interrupt Enable"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection Interrupt Enable"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/intflag.rs b/pac/atsamda1g/src/usb/host/intflag.rs new file mode 100644 index 00000000000..14fbcfb2d1a --- /dev/null +++ b/pac/atsamda1g/src/usb/host/intflag.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - Bus Reset"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - Bus Reset"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - Downstream"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - Downstream"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume from the Device"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume from the Device"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Device Connection"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Device Connection"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Bus Reset"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Downstream"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume from the Device"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Device Connection"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - Bus Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - Downstream"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume from the Device"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Device Connection"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/padcal.rs b/pac/atsamda1g/src/usb/host/padcal.rs new file mode 100644 index 00000000000..9b11d4fc687 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/padcal.rs @@ -0,0 +1,177 @@ +#[doc = "Register `PADCAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PADCAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRANSP` reader - USB Pad Transp calibration"] +pub struct TRANSP_R(crate::FieldReader); +impl TRANSP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSP` writer - USB Pad Transp calibration"] +pub struct TRANSP_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `TRANSN` reader - USB Pad Transn calibration"] +pub struct TRANSN_R(crate::FieldReader); +impl TRANSN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSN` writer - USB Pad Transn calibration"] +pub struct TRANSN_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 6)) | ((value as u16 & 0x1f) << 6); + self.w + } +} +#[doc = "Field `TRIM` reader - USB Pad Trim calibration"] +pub struct TRIM_R(crate::FieldReader); +impl TRIM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIM` writer - USB Pad Trim calibration"] +pub struct TRIM_W<'a> { + w: &'a mut W, +} +impl<'a> TRIM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u16 & 0x07) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&self) -> TRANSP_R { + TRANSP_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&self) -> TRANSN_R { + TRANSN_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 12) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&mut self) -> TRANSP_W { + TRANSP_W { w: self } + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&mut self) -> TRANSN_W { + TRANSN_W { w: self } + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&mut self) -> TRIM_W { + TRIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB PAD Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [padcal](index.html) module"] +pub struct PADCAL_SPEC; +impl crate::RegisterSpec for PADCAL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [padcal::R](R) reader structure"] +impl crate::Readable for PADCAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [padcal::W](W) writer structure"] +impl crate::Writable for PADCAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PADCAL to value 0"] +impl crate::Resettable for PADCAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/pintsmry.rs b/pac/atsamda1g/src/usb/host/pintsmry.rs new file mode 100644 index 00000000000..bc0fba3f12e --- /dev/null +++ b/pac/atsamda1g/src/usb/host/pintsmry.rs @@ -0,0 +1,193 @@ +#[doc = "Register `PINTSMRY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPINT0` reader - Pipe 0 Interrupt"] +pub struct EPINT0_R(crate::FieldReader); +impl EPINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT1` reader - Pipe 1 Interrupt"] +pub struct EPINT1_R(crate::FieldReader); +impl EPINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT2` reader - Pipe 2 Interrupt"] +pub struct EPINT2_R(crate::FieldReader); +impl EPINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT3` reader - Pipe 3 Interrupt"] +pub struct EPINT3_R(crate::FieldReader); +impl EPINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT4` reader - Pipe 4 Interrupt"] +pub struct EPINT4_R(crate::FieldReader); +impl EPINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT5` reader - Pipe 5 Interrupt"] +pub struct EPINT5_R(crate::FieldReader); +impl EPINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT6` reader - Pipe 6 Interrupt"] +pub struct EPINT6_R(crate::FieldReader); +impl EPINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT7` reader - Pipe 7 Interrupt"] +pub struct EPINT7_R(crate::FieldReader); +impl EPINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pipe 0 Interrupt"] + #[inline(always)] + pub fn epint0(&self) -> EPINT0_R { + EPINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pipe 1 Interrupt"] + #[inline(always)] + pub fn epint1(&self) -> EPINT1_R { + EPINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pipe 2 Interrupt"] + #[inline(always)] + pub fn epint2(&self) -> EPINT2_R { + EPINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe 3 Interrupt"] + #[inline(always)] + pub fn epint3(&self) -> EPINT3_R { + EPINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pipe 4 Interrupt"] + #[inline(always)] + pub fn epint4(&self) -> EPINT4_R { + EPINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pipe 5 Interrupt"] + #[inline(always)] + pub fn epint5(&self) -> EPINT5_R { + EPINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pipe 6 Interrupt"] + #[inline(always)] + pub fn epint6(&self) -> EPINT6_R { + EPINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pipe 7 Interrupt"] + #[inline(always)] + pub fn epint7(&self) -> EPINT7_R { + EPINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "HOST Pipe Interrupt Summary\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintsmry](index.html) module"] +pub struct PINTSMRY_SPEC; +impl crate::RegisterSpec for PINTSMRY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pintsmry::R](R) reader structure"] +impl crate::Readable for PINTSMRY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PINTSMRY to value 0"] +impl crate::Resettable for PINTSMRY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/qosctrl.rs b/pac/atsamda1g/src/usb/host/qosctrl.rs new file mode 100644 index 00000000000..86b85a16067 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/qosctrl.rs @@ -0,0 +1,290 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Configuration Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `CQOS` reader - Configuration Quality of Service"] +pub struct CQOS_R(crate::FieldReader); +impl CQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CQOS_A { + match self.bits { + 0 => CQOS_A::DISABLE, + 1 => CQOS_A::LOW, + 2 => CQOS_A::MEDIUM, + 3 => CQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == CQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == CQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == CQOS_A::HIGH + } +} +impl core::ops::Deref for CQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CQOS` writer - Configuration Quality of Service"] +pub struct CQOS_W<'a> { + w: &'a mut W, +} +impl<'a> CQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(CQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(CQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(CQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Data Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&self) -> CQOS_R { + CQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&mut self) -> CQOS_W { + CQOS_W { w: self } + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB Quality Of Service\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x05"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1g/src/usb/host/status.rs b/pac/atsamda1g/src/usb/host/status.rs new file mode 100644 index 00000000000..45cf612fdac --- /dev/null +++ b/pac/atsamda1g/src/usb/host/status.rs @@ -0,0 +1,140 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPEED` reader - Speed Status"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Status"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Field `LINESTATE` reader - USB Line State Status"] +pub struct LINESTATE_R(crate::FieldReader); +impl LINESTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINESTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINESTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINESTATE` writer - USB Line State Status"] +pub struct LINESTATE_W<'a> { + w: &'a mut W, +} +impl<'a> LINESTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&self) -> LINESTATE_R { + LINESTATE_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&mut self) -> LINESTATE_W { + LINESTATE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/usb/host/syncbusy.rs b/pac/atsamda1g/src/usb/host/syncbusy.rs new file mode 100644 index 00000000000..5f22af98954 --- /dev/null +++ b/pac/atsamda1g/src/usb/host/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/wdt.rs b/pac/atsamda1g/src/wdt.rs new file mode 100644 index 00000000000..0c5da61ba13 --- /dev/null +++ b/pac/atsamda1g/src/wdt.rs @@ -0,0 +1,53 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamda1g/src/wdt/clear.rs b/pac/atsamda1g/src/wdt/clear.rs new file mode 100644 index 00000000000..61ee21f3246 --- /dev/null +++ b/pac/atsamda1g/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/wdt/config.rs b/pac/atsamda1g/src/wdt/config.rs new file mode 100644 index 00000000000..b87e8a0a9bd --- /dev/null +++ b/pac/atsamda1g/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::_8), + 1 => Some(PER_A::_16), + 2 => Some(PER_A::_32), + 3 => Some(PER_A::_64), + 4 => Some(PER_A::_128), + 5 => Some(PER_A::_256), + 6 => Some(PER_A::_512), + 7 => Some(PER_A::_1K), + 8 => Some(PER_A::_2K), + 9 => Some(PER_A::_4K), + 10 => Some(PER_A::_8K), + 11 => Some(PER_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PER_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PER_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PER_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PER_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PER_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PER_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PER_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == PER_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == PER_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == PER_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == PER_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == PER_A::_16K + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PER_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PER_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PER_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PER_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PER_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PER_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PER_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(PER_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(PER_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(PER_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(PER_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(PER_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::_8), + 1 => Some(WINDOW_A::_16), + 2 => Some(WINDOW_A::_32), + 3 => Some(WINDOW_A::_64), + 4 => Some(WINDOW_A::_128), + 5 => Some(WINDOW_A::_256), + 6 => Some(WINDOW_A::_512), + 7 => Some(WINDOW_A::_1K), + 8 => Some(WINDOW_A::_2K), + 9 => Some(WINDOW_A::_4K), + 10 => Some(WINDOW_A::_8K), + 11 => Some(WINDOW_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == WINDOW_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == WINDOW_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == WINDOW_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == WINDOW_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == WINDOW_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == WINDOW_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == WINDOW_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == WINDOW_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == WINDOW_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == WINDOW_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == WINDOW_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == WINDOW_A::_16K + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(WINDOW_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(WINDOW_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(WINDOW_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(WINDOW_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(WINDOW_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(WINDOW_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(WINDOW_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(WINDOW_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(WINDOW_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(WINDOW_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(WINDOW_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(WINDOW_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamda1g/src/wdt/ctrl.rs b/pac/atsamda1g/src/wdt/ctrl.rs new file mode 100644 index 00000000000..d312316d919 --- /dev/null +++ b/pac/atsamda1g/src/wdt/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/wdt/ewctrl.rs b/pac/atsamda1g/src/wdt/ewctrl.rs new file mode 100644 index 00000000000..6c7e31273c3 --- /dev/null +++ b/pac/atsamda1g/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::_8), + 1 => Some(EWOFFSET_A::_16), + 2 => Some(EWOFFSET_A::_32), + 3 => Some(EWOFFSET_A::_64), + 4 => Some(EWOFFSET_A::_128), + 5 => Some(EWOFFSET_A::_256), + 6 => Some(EWOFFSET_A::_512), + 7 => Some(EWOFFSET_A::_1K), + 8 => Some(EWOFFSET_A::_2K), + 9 => Some(EWOFFSET_A::_4K), + 10 => Some(EWOFFSET_A::_8K), + 11 => Some(EWOFFSET_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == EWOFFSET_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == EWOFFSET_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == EWOFFSET_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == EWOFFSET_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == EWOFFSET_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == EWOFFSET_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == EWOFFSET_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == EWOFFSET_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == EWOFFSET_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == EWOFFSET_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == EWOFFSET_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == EWOFFSET_A::_16K + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(EWOFFSET_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(EWOFFSET_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(EWOFFSET_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(EWOFFSET_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(EWOFFSET_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(EWOFFSET_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(EWOFFSET_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamda1g/src/wdt/intenclr.rs b/pac/atsamda1g/src/wdt/intenclr.rs new file mode 100644 index 00000000000..ed4021f96cc --- /dev/null +++ b/pac/atsamda1g/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/wdt/intenset.rs b/pac/atsamda1g/src/wdt/intenset.rs new file mode 100644 index 00000000000..5a0928ff053 --- /dev/null +++ b/pac/atsamda1g/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/wdt/intflag.rs b/pac/atsamda1g/src/wdt/intflag.rs new file mode 100644 index 00000000000..f2c9b858a19 --- /dev/null +++ b/pac/atsamda1g/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1g/src/wdt/status.rs b/pac/atsamda1g/src/wdt/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1g/src/wdt/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/Cargo.toml b/pac/atsamda1j/Cargo.toml new file mode 100644 index 00000000000..e98f181593b --- /dev/null +++ b/pac/atsamda1j/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamda1j" +description = "Peripheral access API for ATSAMDA1J microcontrollers (generated using svd2rust)" +version = "0.12.0" +authors = ["Wez Furlong ", "Paul Sajna "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamda1j/README.md b/pac/atsamda1j/README.md new file mode 100644 index 00000000000..fac3a4f4f0e --- /dev/null +++ b/pac/atsamda1j/README.md @@ -0,0 +1,26 @@ +# ATSAMDA1J + +A peripheral access crate for the ATSAMDA1J chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamda1j.svg)](https://crates.io/crates/atsamda1j) + +## [Documentation](https://docs.rs/atsamda1j) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamda1j/build.rs b/pac/atsamda1j/build.rs new file mode 100644 index 00000000000..597923f5089 --- /dev/null +++ b/pac/atsamda1j/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamda1j/device.x b/pac/atsamda1j/device.x new file mode 100644 index 00000000000..c0f686af5ad --- /dev/null +++ b/pac/atsamda1j/device.x @@ -0,0 +1,29 @@ +PROVIDE(PM = DefaultHandler); +PROVIDE(SYSCTRL = DefaultHandler); +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(USB = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(SERCOM4 = DefaultHandler); +PROVIDE(SERCOM5 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(TC5 = DefaultHandler); +PROVIDE(TC6 = DefaultHandler); +PROVIDE(TC7 = DefaultHandler); +PROVIDE(ADC = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(DAC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); +PROVIDE(I2S = DefaultHandler); + diff --git a/pac/atsamda1j/src/ac.rs b/pac/atsamda1j/src/ac.rs new file mode 100644 index 00000000000..ed9e2eeafde --- /dev/null +++ b/pac/atsamda1j/src/ac.rs @@ -0,0 +1,80 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x09 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x0a - Status C"] + pub statusc: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x0c - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x03], + #[doc = "0x10..0x18 - Comparator Control n"] + pub compctrl: [crate::Reg; 2], + _reserved11: [u8; 0x08], + #[doc = "0x20 - Scaler n"] + pub scaler: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; diff --git a/pac/atsamda1j/src/ac/compctrl.rs b/pac/atsamda1j/src/ac/compctrl.rs new file mode 100644 index 00000000000..531766edc60 --- /dev/null +++ b/pac/atsamda1j/src/ac/compctrl.rs @@ -0,0 +1,927 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "1: High speed"] + HIGH = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 1 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEG_A { + match self.bits { + 0 => MUXNEG_A::PIN0, + 1 => MUXNEG_A::PIN1, + 2 => MUXNEG_A::PIN2, + 3 => MUXNEG_A::PIN3, + 4 => MUXNEG_A::GND, + 5 => MUXNEG_A::VSCALE, + 6 => MUXNEG_A::BANDGAP, + 7 => MUXNEG_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXNEG_A::DAC + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEG_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXPOS_A { + match self.bits { + 0 => MUXPOS_A::PIN0, + 1 => MUXPOS_A::PIN1, + 2 => MUXPOS_A::PIN2, + 3 => MUXPOS_A::PIN3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:13 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 2:3 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bits 5:6 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:13 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/ctrla.rs b/pac/atsamda1j/src/ac/ctrla.rs new file mode 100644 index 00000000000..1a9beb48325 --- /dev/null +++ b/pac/atsamda1j/src/ac/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LPMUX` reader - Low-Power Mux"] +pub struct LPMUX_R(crate::FieldReader); +impl LPMUX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMUX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMUX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMUX` writer - Low-Power Mux"] +pub struct LPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> LPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Low-Power Mux"] + #[inline(always)] + pub fn lpmux(&self) -> LPMUX_R { + LPMUX_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Low-Power Mux"] + #[inline(always)] + pub fn lpmux(&mut self) -> LPMUX_W { + LPMUX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/ctrlb.rs b/pac/atsamda1j/src/ac/ctrlb.rs new file mode 100644 index 00000000000..68aa8d2a20b --- /dev/null +++ b/pac/atsamda1j/src/ac/ctrlb.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/evctrl.rs b/pac/atsamda1j/src/ac/evctrl.rs new file mode 100644 index 00000000000..88fbebc8430 --- /dev/null +++ b/pac/atsamda1j/src/ac/evctrl.rs @@ -0,0 +1,301 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/intenclr.rs b/pac/atsamda1j/src/ac/intenclr.rs new file mode 100644 index 00000000000..45e3320d293 --- /dev/null +++ b/pac/atsamda1j/src/ac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/intenset.rs b/pac/atsamda1j/src/ac/intenset.rs new file mode 100644 index 00000000000..5354a4d111d --- /dev/null +++ b/pac/atsamda1j/src/ac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/intflag.rs b/pac/atsamda1j/src/ac/intflag.rs new file mode 100644 index 00000000000..7da0fea7569 --- /dev/null +++ b/pac/atsamda1j/src/ac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/scaler.rs b/pac/atsamda1j/src/ac/scaler.rs new file mode 100644 index 00000000000..091cacfaeb4 --- /dev/null +++ b/pac/atsamda1j/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/statusa.rs b/pac/atsamda1j/src/ac/statusa.rs new file mode 100644 index 00000000000..7b98c567e8a --- /dev/null +++ b/pac/atsamda1j/src/ac/statusa.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/statusb.rs b/pac/atsamda1j/src/ac/statusb.rs new file mode 100644 index 00000000000..fa16c8bda71 --- /dev/null +++ b/pac/atsamda1j/src/ac/statusb.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/statusc.rs b/pac/atsamda1j/src/ac/statusc.rs new file mode 100644 index 00000000000..7bef2226d54 --- /dev/null +++ b/pac/atsamda1j/src/ac/statusc.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/ac/winctrl.rs b/pac/atsamda1j/src/ac/winctrl.rs new file mode 100644 index 00000000000..3259570489e --- /dev/null +++ b/pac/atsamda1j/src/ac/winctrl.rs @@ -0,0 +1,225 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc.rs b/pac/atsamda1j/src/adc.rs new file mode 100644 index 00000000000..33524a423c2 --- /dev/null +++ b/pac/atsamda1j/src/adc.rs @@ -0,0 +1,130 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x02 - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x03 - Sampling Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x08 - Window Monitor Control"] + pub winctrl: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x0c - Software Trigger"] + pub swtrig: crate::Reg, + _reserved7: [u8; 0x03], + #[doc = "0x10 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x14 - Event Control"] + pub evctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x16 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x17 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x19 - Status"] + pub status: crate::Reg, + #[doc = "0x1a - Result"] + pub result: crate::Reg, + #[doc = "0x1c - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + _reserved15: [u8; 0x02], + #[doc = "0x20 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x24 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x26 - Offset Correction"] + pub offsetcorr: crate::Reg, + #[doc = "0x28 - Calibration"] + pub calib: crate::Reg, + #[doc = "0x2a - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sampling Time Control"] +pub mod sampctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Monitor Control"] +pub mod winctrl; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1j/src/adc/avgctrl.rs b/pac/atsamda1j/src/adc/avgctrl.rs new file mode 100644 index 00000000000..ddb735715c9 --- /dev/null +++ b/pac/atsamda1j/src/adc/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/calib.rs b/pac/atsamda1j/src/adc/calib.rs new file mode 100644 index 00000000000..553ad515946 --- /dev/null +++ b/pac/atsamda1j/src/adc/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LINEARITY_CAL` reader - Linearity Calibration Value"] +pub struct LINEARITY_CAL_R(crate::FieldReader); +impl LINEARITY_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINEARITY_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINEARITY_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINEARITY_CAL` writer - Linearity Calibration Value"] +pub struct LINEARITY_CAL_W<'a> { + w: &'a mut W, +} +impl<'a> LINEARITY_CAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Field `BIAS_CAL` reader - Bias Calibration Value"] +pub struct BIAS_CAL_R(crate::FieldReader); +impl BIAS_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIAS_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIAS_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIAS_CAL` writer - Bias Calibration Value"] +pub struct BIAS_CAL_W<'a> { + w: &'a mut W, +} +impl<'a> BIAS_CAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Linearity Calibration Value"] + #[inline(always)] + pub fn linearity_cal(&self) -> LINEARITY_CAL_R { + LINEARITY_CAL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Bias Calibration Value"] + #[inline(always)] + pub fn bias_cal(&self) -> BIAS_CAL_R { + BIAS_CAL_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Linearity Calibration Value"] + #[inline(always)] + pub fn linearity_cal(&mut self) -> LINEARITY_CAL_W { + LINEARITY_CAL_W { w: self } + } + #[doc = "Bits 8:10 - Bias Calibration Value"] + #[inline(always)] + pub fn bias_cal(&mut self) -> BIAS_CAL_W { + BIAS_CAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/ctrla.rs b/pac/atsamda1j/src/adc/ctrla.rs new file mode 100644 index 00000000000..117922e5aae --- /dev/null +++ b/pac/atsamda1j/src/adc/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/ctrlb.rs b/pac/atsamda1j/src/adc/ctrlb.rs new file mode 100644 index 00000000000..79137605c46 --- /dev/null +++ b/pac/atsamda1j/src/adc/ctrlb.rs @@ -0,0 +1,530 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enabled"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enabled"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit result"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit result"] + _10BIT = 2, + #[doc = "3: 8-bit result"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit result"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit result"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit result"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 4"] + DIV4 = 0, + #[doc = "1: Peripheral clock divided by 8"] + DIV8 = 1, + #[doc = "2: Peripheral clock divided by 16"] + DIV16 = 2, + #[doc = "3: Peripheral clock divided by 32"] + DIV32 = 3, + #[doc = "4: Peripheral clock divided by 64"] + DIV64 = 4, + #[doc = "5: Peripheral clock divided by 128"] + DIV128 = 5, + #[doc = "6: Peripheral clock divided by 256"] + DIV256 = 6, + #[doc = "7: Peripheral clock divided by 512"] + DIV512 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV4, + 1 => PRESCALER_A::DIV8, + 2 => PRESCALER_A::DIV16, + 3 => PRESCALER_A::DIV32, + 4 => PRESCALER_A::DIV64, + 5 => PRESCALER_A::DIV128, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV512, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Peripheral clock divided by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enabled"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enabled"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/dbgctrl.rs b/pac/atsamda1j/src/adc/dbgctrl.rs new file mode 100644 index 00000000000..53636eb2b33 --- /dev/null +++ b/pac/atsamda1j/src/adc/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/evctrl.rs b/pac/atsamda1j/src/adc/evctrl.rs new file mode 100644 index 00000000000..cf040e96c73 --- /dev/null +++ b/pac/atsamda1j/src/adc/evctrl.rs @@ -0,0 +1,254 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event In"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event In"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCEI` reader - Synchronization Event In"] +pub struct SYNCEI_R(crate::FieldReader); +impl SYNCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCEI` writer - Synchronization Event In"] +pub struct SYNCEI_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event In"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Synchronization Event In"] + #[inline(always)] + pub fn syncei(&self) -> SYNCEI_R { + SYNCEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event In"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Synchronization Event In"] + #[inline(always)] + pub fn syncei(&mut self) -> SYNCEI_W { + SYNCEI_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/gaincorr.rs b/pac/atsamda1j/src/adc/gaincorr.rs new file mode 100644 index 00000000000..496cb8c6021 --- /dev/null +++ b/pac/atsamda1j/src/adc/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/inputctrl.rs b/pac/atsamda1j/src/adc/inputctrl.rs new file mode 100644 index 00000000000..8a7dc86535b --- /dev/null +++ b/pac/atsamda1j/src/adc/inputctrl.rs @@ -0,0 +1,853 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + PIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + PIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + PIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + PIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + PIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + PIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + PIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + PIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + PIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + PIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + PIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + PIN11 = 11, + #[doc = "12: ADC AIN12 Pin"] + PIN12 = 12, + #[doc = "13: ADC AIN13 Pin"] + PIN13 = 13, + #[doc = "14: ADC AIN14 Pin"] + PIN14 = 14, + #[doc = "15: ADC AIN15 Pin"] + PIN15 = 15, + #[doc = "16: ADC AIN16 Pin"] + PIN16 = 16, + #[doc = "17: ADC AIN17 Pin"] + PIN17 = 17, + #[doc = "18: ADC AIN18 Pin"] + PIN18 = 18, + #[doc = "19: ADC AIN19 Pin"] + PIN19 = 19, + #[doc = "24: Temperature Reference"] + TEMP = 24, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "28: DAC Output"] + DAC = 28, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::PIN4), + 5 => Some(MUXPOS_A::PIN5), + 6 => Some(MUXPOS_A::PIN6), + 7 => Some(MUXPOS_A::PIN7), + 8 => Some(MUXPOS_A::PIN8), + 9 => Some(MUXPOS_A::PIN9), + 10 => Some(MUXPOS_A::PIN10), + 11 => Some(MUXPOS_A::PIN11), + 12 => Some(MUXPOS_A::PIN12), + 13 => Some(MUXPOS_A::PIN13), + 14 => Some(MUXPOS_A::PIN14), + 15 => Some(MUXPOS_A::PIN15), + 16 => Some(MUXPOS_A::PIN16), + 17 => Some(MUXPOS_A::PIN17), + 18 => Some(MUXPOS_A::PIN18), + 19 => Some(MUXPOS_A::PIN19), + 24 => Some(MUXPOS_A::TEMP), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + 28 => Some(MUXPOS_A::DAC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `PIN4`"] + #[inline(always)] + pub fn is_pin4(&self) -> bool { + **self == MUXPOS_A::PIN4 + } + #[doc = "Checks if the value of the field is `PIN5`"] + #[inline(always)] + pub fn is_pin5(&self) -> bool { + **self == MUXPOS_A::PIN5 + } + #[doc = "Checks if the value of the field is `PIN6`"] + #[inline(always)] + pub fn is_pin6(&self) -> bool { + **self == MUXPOS_A::PIN6 + } + #[doc = "Checks if the value of the field is `PIN7`"] + #[inline(always)] + pub fn is_pin7(&self) -> bool { + **self == MUXPOS_A::PIN7 + } + #[doc = "Checks if the value of the field is `PIN8`"] + #[inline(always)] + pub fn is_pin8(&self) -> bool { + **self == MUXPOS_A::PIN8 + } + #[doc = "Checks if the value of the field is `PIN9`"] + #[inline(always)] + pub fn is_pin9(&self) -> bool { + **self == MUXPOS_A::PIN9 + } + #[doc = "Checks if the value of the field is `PIN10`"] + #[inline(always)] + pub fn is_pin10(&self) -> bool { + **self == MUXPOS_A::PIN10 + } + #[doc = "Checks if the value of the field is `PIN11`"] + #[inline(always)] + pub fn is_pin11(&self) -> bool { + **self == MUXPOS_A::PIN11 + } + #[doc = "Checks if the value of the field is `PIN12`"] + #[inline(always)] + pub fn is_pin12(&self) -> bool { + **self == MUXPOS_A::PIN12 + } + #[doc = "Checks if the value of the field is `PIN13`"] + #[inline(always)] + pub fn is_pin13(&self) -> bool { + **self == MUXPOS_A::PIN13 + } + #[doc = "Checks if the value of the field is `PIN14`"] + #[inline(always)] + pub fn is_pin14(&self) -> bool { + **self == MUXPOS_A::PIN14 + } + #[doc = "Checks if the value of the field is `PIN15`"] + #[inline(always)] + pub fn is_pin15(&self) -> bool { + **self == MUXPOS_A::PIN15 + } + #[doc = "Checks if the value of the field is `PIN16`"] + #[inline(always)] + pub fn is_pin16(&self) -> bool { + **self == MUXPOS_A::PIN16 + } + #[doc = "Checks if the value of the field is `PIN17`"] + #[inline(always)] + pub fn is_pin17(&self) -> bool { + **self == MUXPOS_A::PIN17 + } + #[doc = "Checks if the value of the field is `PIN18`"] + #[inline(always)] + pub fn is_pin18(&self) -> bool { + **self == MUXPOS_A::PIN18 + } + #[doc = "Checks if the value of the field is `PIN19`"] + #[inline(always)] + pub fn is_pin19(&self) -> bool { + **self == MUXPOS_A::PIN19 + } + #[doc = "Checks if the value of the field is `TEMP`"] + #[inline(always)] + pub fn is_temp(&self) -> bool { + **self == MUXPOS_A::TEMP + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXPOS_A::DAC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn pin4(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn pin5(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn pin6(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn pin7(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn pin8(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn pin9(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn pin10(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn pin11(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN11) + } + #[doc = "ADC AIN12 Pin"] + #[inline(always)] + pub fn pin12(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN12) + } + #[doc = "ADC AIN13 Pin"] + #[inline(always)] + pub fn pin13(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN13) + } + #[doc = "ADC AIN14 Pin"] + #[inline(always)] + pub fn pin14(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN14) + } + #[doc = "ADC AIN15 Pin"] + #[inline(always)] + pub fn pin15(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN15) + } + #[doc = "ADC AIN16 Pin"] + #[inline(always)] + pub fn pin16(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN16) + } + #[doc = "ADC AIN17 Pin"] + #[inline(always)] + pub fn pin17(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN17) + } + #[doc = "ADC AIN18 Pin"] + #[inline(always)] + pub fn pin18(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN18) + } + #[doc = "ADC AIN19 Pin"] + #[inline(always)] + pub fn pin19(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN19) + } + #[doc = "Temperature Reference"] + #[inline(always)] + pub fn temp(self) -> &'a mut W { + self.variant(MUXPOS_A::TEMP) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = "DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXPOS_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + PIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + PIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + PIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + PIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + PIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + PIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + PIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + PIN7 = 7, + #[doc = "24: Internal Ground"] + GND = 24, + #[doc = "25: I/O Ground"] + IOGND = 25, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::PIN0), + 1 => Some(MUXNEG_A::PIN1), + 2 => Some(MUXNEG_A::PIN2), + 3 => Some(MUXNEG_A::PIN3), + 4 => Some(MUXNEG_A::PIN4), + 5 => Some(MUXNEG_A::PIN5), + 6 => Some(MUXNEG_A::PIN6), + 7 => Some(MUXNEG_A::PIN7), + 24 => Some(MUXNEG_A::GND), + 25 => Some(MUXNEG_A::IOGND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `PIN4`"] + #[inline(always)] + pub fn is_pin4(&self) -> bool { + **self == MUXNEG_A::PIN4 + } + #[doc = "Checks if the value of the field is `PIN5`"] + #[inline(always)] + pub fn is_pin5(&self) -> bool { + **self == MUXNEG_A::PIN5 + } + #[doc = "Checks if the value of the field is `PIN6`"] + #[inline(always)] + pub fn is_pin6(&self) -> bool { + **self == MUXNEG_A::PIN6 + } + #[doc = "Checks if the value of the field is `PIN7`"] + #[inline(always)] + pub fn is_pin7(&self) -> bool { + **self == MUXNEG_A::PIN7 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `IOGND`"] + #[inline(always)] + pub fn is_iognd(&self) -> bool { + **self == MUXNEG_A::IOGND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn pin4(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn pin5(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn pin6(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn pin7(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN7) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "I/O Ground"] + #[inline(always)] + pub fn iognd(self) -> &'a mut W { + self.variant(MUXNEG_A::IOGND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `INPUTSCAN` reader - Number of Input Channels Included in Scan"] +pub struct INPUTSCAN_R(crate::FieldReader); +impl INPUTSCAN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INPUTSCAN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTSCAN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTSCAN` writer - Number of Input Channels Included in Scan"] +pub struct INPUTSCAN_W<'a> { + w: &'a mut W, +} +impl<'a> INPUTSCAN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INPUTOFFSET` reader - Positive Mux Setting Offset"] +pub struct INPUTOFFSET_R(crate::FieldReader); +impl INPUTOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INPUTOFFSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTOFFSET` writer - Positive Mux Setting Offset"] +pub struct INPUTOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> INPUTOFFSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Gain Factor Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 1x"] + _1X = 0, + #[doc = "1: 2x"] + _2X = 1, + #[doc = "2: 4x"] + _4X = 2, + #[doc = "3: 8x"] + _8X = 3, + #[doc = "4: 16x"] + _16X = 4, + #[doc = "15: 1/2x"] + DIV2 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Gain Factor Selection"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::_1X), + 1 => Some(GAIN_A::_2X), + 2 => Some(GAIN_A::_4X), + 3 => Some(GAIN_A::_8X), + 4 => Some(GAIN_A::_16X), + 15 => Some(GAIN_A::DIV2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1X`"] + #[inline(always)] + pub fn is_1x(&self) -> bool { + **self == GAIN_A::_1X + } + #[doc = "Checks if the value of the field is `_2X`"] + #[inline(always)] + pub fn is_2x(&self) -> bool { + **self == GAIN_A::_2X + } + #[doc = "Checks if the value of the field is `_4X`"] + #[inline(always)] + pub fn is_4x(&self) -> bool { + **self == GAIN_A::_4X + } + #[doc = "Checks if the value of the field is `_8X`"] + #[inline(always)] + pub fn is_8x(&self) -> bool { + **self == GAIN_A::_8X + } + #[doc = "Checks if the value of the field is `_16X`"] + #[inline(always)] + pub fn is_16x(&self) -> bool { + **self == GAIN_A::_16X + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == GAIN_A::DIV2 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Gain Factor Selection"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1x"] + #[inline(always)] + pub fn _1x(self) -> &'a mut W { + self.variant(GAIN_A::_1X) + } + #[doc = "2x"] + #[inline(always)] + pub fn _2x(self) -> &'a mut W { + self.variant(GAIN_A::_2X) + } + #[doc = "4x"] + #[inline(always)] + pub fn _4x(self) -> &'a mut W { + self.variant(GAIN_A::_4X) + } + #[doc = "8x"] + #[inline(always)] + pub fn _8x(self) -> &'a mut W { + self.variant(GAIN_A::_8X) + } + #[doc = "16x"] + #[inline(always)] + pub fn _16x(self) -> &'a mut W { + self.variant(GAIN_A::_16X) + } + #[doc = "1/2x"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(GAIN_A::DIV2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] + #[inline(always)] + pub fn inputscan(&self) -> INPUTSCAN_R { + INPUTSCAN_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Positive Mux Setting Offset"] + #[inline(always)] + pub fn inputoffset(&self) -> INPUTOFFSET_R { + INPUTOFFSET_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Gain Factor Selection"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] + #[inline(always)] + pub fn inputscan(&mut self) -> INPUTSCAN_W { + INPUTSCAN_W { w: self } + } + #[doc = "Bits 20:23 - Positive Mux Setting Offset"] + #[inline(always)] + pub fn inputoffset(&mut self) -> INPUTOFFSET_W { + INPUTOFFSET_W { w: self } + } + #[doc = "Bits 24:27 - Gain Factor Selection"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/intenclr.rs b/pac/atsamda1j/src/adc/intenclr.rs new file mode 100644 index 00000000000..453afa12c61 --- /dev/null +++ b/pac/atsamda1j/src/adc/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/intenset.rs b/pac/atsamda1j/src/adc/intenset.rs new file mode 100644 index 00000000000..0d36429e544 --- /dev/null +++ b/pac/atsamda1j/src/adc/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/intflag.rs b/pac/atsamda1j/src/adc/intflag.rs new file mode 100644 index 00000000000..fec838269e9 --- /dev/null +++ b/pac/atsamda1j/src/adc/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/offsetcorr.rs b/pac/atsamda1j/src/adc/offsetcorr.rs new file mode 100644 index 00000000000..24a97427c64 --- /dev/null +++ b/pac/atsamda1j/src/adc/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/refctrl.rs b/pac/atsamda1j/src/adc/refctrl.rs new file mode 100644 index 00000000000..8053351459b --- /dev/null +++ b/pac/atsamda1j/src/adc/refctrl.rs @@ -0,0 +1,238 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: 1.0V voltage reference"] + INT1V = 0, + #[doc = "1: 1/1.48 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA (only for VDDANA > 2.0V)"] + INTVCC1 = 2, + #[doc = "3: External reference A"] + AREFA = 3, + #[doc = "4: External reference B"] + AREFB = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 4 => Some(REFSEL_A::AREFB), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + **self == REFSEL_A::AREFB + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.0V voltage reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "1/1.48 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA (only for VDDANA > 2.0V)"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External reference A"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "External reference B"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSEL_A::AREFB) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/result.rs b/pac/atsamda1j/src/adc/result.rs new file mode 100644 index 00000000000..f93bf58c6ba --- /dev/null +++ b/pac/atsamda1j/src/adc/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Conversion Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Conversion Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/sampctrl.rs b/pac/atsamda1j/src/adc/sampctrl.rs new file mode 100644 index 00000000000..b8cbc598b10 --- /dev/null +++ b/pac/atsamda1j/src/adc/sampctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sampling Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/status.rs b/pac/atsamda1j/src/adc/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1j/src/adc/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/swtrig.rs b/pac/atsamda1j/src/adc/swtrig.rs new file mode 100644 index 00000000000..111c0662dea --- /dev/null +++ b/pac/atsamda1j/src/adc/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Conversion Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Conversion Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - ADC Start Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - ADC Start Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Conversion Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ADC Start Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Conversion Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - ADC Start Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/winctrl.rs b/pac/atsamda1j/src/adc/winctrl.rs new file mode 100644 index 00000000000..6dd12786c7f --- /dev/null +++ b/pac/atsamda1j/src/adc/winctrl.rs @@ -0,0 +1,191 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: Mode 1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: Mode 2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: Mode 3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: Mode 4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "Mode 1: RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "Mode 2: RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "Mode 3: WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "Mode 4: !(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/winlt.rs b/pac/atsamda1j/src/adc/winlt.rs new file mode 100644 index 00000000000..2a339768476 --- /dev/null +++ b/pac/atsamda1j/src/adc/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/adc/winut.rs b/pac/atsamda1j/src/adc/winut.rs new file mode 100644 index 00000000000..0ea12317493 --- /dev/null +++ b/pac/atsamda1j/src/adc/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac.rs b/pac/atsamda1j/src/dac.rs new file mode 100644 index 00000000000..1816621e5db --- /dev/null +++ b/pac/atsamda1j/src/dac.rs @@ -0,0 +1,60 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Data"] + pub data: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x0c - Data Buffer"] + pub databuf: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DATABUF register accessor: an alias for `Reg`"] +pub type DATABUF = crate::Reg; +#[doc = "Data Buffer"] +pub mod databuf; diff --git a/pac/atsamda1j/src/dac/ctrla.rs b/pac/atsamda1j/src/dac/ctrla.rs new file mode 100644 index 00000000000..117922e5aae --- /dev/null +++ b/pac/atsamda1j/src/dac/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/ctrlb.rs b/pac/atsamda1j/src/dac/ctrlb.rs new file mode 100644 index 00000000000..1da837c6d4a --- /dev/null +++ b/pac/atsamda1j/src/dac/ctrlb.rs @@ -0,0 +1,400 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EOEN` reader - External Output Enable"] +pub struct EOEN_R(crate::FieldReader); +impl EOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EOEN` writer - External Output Enable"] +pub struct EOEN_W<'a> { + w: &'a mut W, +} +impl<'a> EOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `IOEN` reader - Internal Output Enable"] +pub struct IOEN_R(crate::FieldReader); +impl IOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOEN` writer - Internal Output Enable"] +pub struct IOEN_W<'a> { + w: &'a mut W, +} +impl<'a> IOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VPD` reader - Voltage Pump Disable"] +pub struct VPD_R(crate::FieldReader); +impl VPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VPD` writer - Voltage Pump Disable"] +pub struct VPD_W<'a> { + w: &'a mut W, +} +impl<'a> VPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BDWP` reader - Bypass DATABUF Write Protection"] +pub struct BDWP_R(crate::FieldReader); +impl BDWP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BDWP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BDWP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BDWP` writer - Bypass DATABUF Write Protection"] +pub struct BDWP_W<'a> { + w: &'a mut W, +} +impl<'a> BDWP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal 1.0V reference"] + INT1V = 0, + #[doc = "1: AVCC"] + AVCC = 1, + #[doc = "2: External reference"] + VREFP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::AVCC), + 2 => Some(REFSEL_A::VREFP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `AVCC`"] + #[inline(always)] + pub fn is_avcc(&self) -> bool { + **self == REFSEL_A::AVCC + } + #[doc = "Checks if the value of the field is `VREFP`"] + #[inline(always)] + pub fn is_vrefp(&self) -> bool { + **self == REFSEL_A::VREFP + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal 1.0V reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "AVCC"] + #[inline(always)] + pub fn avcc(self) -> &'a mut W { + self.variant(REFSEL_A::AVCC) + } + #[doc = "External reference"] + #[inline(always)] + pub fn vrefp(self) -> &'a mut W { + self.variant(REFSEL_A::VREFP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&self) -> EOEN_R { + EOEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&self) -> IOEN_R { + IOEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&self) -> VPD_R { + VPD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Bypass DATABUF Write Protection"] + #[inline(always)] + pub fn bdwp(&self) -> BDWP_R { + BDWP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&mut self) -> EOEN_W { + EOEN_W { w: self } + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&mut self) -> IOEN_W { + IOEN_W { w: self } + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&mut self) -> VPD_W { + VPD_W { w: self } + } + #[doc = "Bit 4 - Bypass DATABUF Write Protection"] + #[inline(always)] + pub fn bdwp(&mut self) -> BDWP_W { + BDWP_W { w: self } + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/data.rs b/pac/atsamda1j/src/dac/data.rs new file mode 100644 index 00000000000..4caca5e0a51 --- /dev/null +++ b/pac/atsamda1j/src/dac/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data value to be converted"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data value to be converted"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/databuf.rs b/pac/atsamda1j/src/dac/databuf.rs new file mode 100644 index 00000000000..1e945f893ff --- /dev/null +++ b/pac/atsamda1j/src/dac/databuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATABUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATABUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATABUF` reader - Data Buffer"] +pub struct DATABUF_R(crate::FieldReader); +impl DATABUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATABUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATABUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATABUF` writer - Data Buffer"] +pub struct DATABUF_W<'a> { + w: &'a mut W, +} +impl<'a> DATABUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&self) -> DATABUF_R { + DATABUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&mut self) -> DATABUF_W { + DATABUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databuf](index.html) module"] +pub struct DATABUF_SPEC; +impl crate::RegisterSpec for DATABUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [databuf::R](R) reader structure"] +impl crate::Readable for DATABUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [databuf::W](W) writer structure"] +impl crate::Writable for DATABUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATABUF to value 0"] +impl crate::Resettable for DATABUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/evctrl.rs b/pac/atsamda1j/src/dac/evctrl.rs new file mode 100644 index 00000000000..7d48fce2186 --- /dev/null +++ b/pac/atsamda1j/src/dac/evctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTYEO` reader - Data Buffer Empty Event Output"] +pub struct EMPTYEO_R(crate::FieldReader); +impl EMPTYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTYEO` writer - Data Buffer Empty Event Output"] +pub struct EMPTYEO_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&self) -> EMPTYEO_R { + EMPTYEO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&mut self) -> EMPTYEO_W { + EMPTYEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/intenclr.rs b/pac/atsamda1j/src/dac/intenclr.rs new file mode 100644 index 00000000000..5d97a2c4cd4 --- /dev/null +++ b/pac/atsamda1j/src/dac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/intenset.rs b/pac/atsamda1j/src/dac/intenset.rs new file mode 100644 index 00000000000..27b8e50d55a --- /dev/null +++ b/pac/atsamda1j/src/dac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/intflag.rs b/pac/atsamda1j/src/dac/intflag.rs new file mode 100644 index 00000000000..0df47b31e15 --- /dev/null +++ b/pac/atsamda1j/src/dac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Bit 2 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dac/status.rs b/pac/atsamda1j/src/dac/status.rs new file mode 100644 index 00000000000..2667b356df2 --- /dev/null +++ b/pac/atsamda1j/src/dac/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy Status"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy Status"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac.rs b/pac/atsamda1j/src/dmac.rs new file mode 100644 index 00000000000..c23d3669755 --- /dev/null +++ b/pac/atsamda1j/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamda1j/src/dmac/active.rs b/pac/atsamda1j/src/dmac/active.rs new file mode 100644 index 00000000000..c3cc5a0420b --- /dev/null +++ b/pac/atsamda1j/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/baseaddr.rs b/pac/atsamda1j/src/dmac/baseaddr.rs new file mode 100644 index 00000000000..cec8c8cf077 --- /dev/null +++ b/pac/atsamda1j/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/busych.rs b/pac/atsamda1j/src/dmac/busych.rs new file mode 100644 index 00000000000..6f9419d5828 --- /dev/null +++ b/pac/atsamda1j/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/chctrla.rs b/pac/atsamda1j/src/dmac/chctrla.rs new file mode 100644 index 00000000000..49471b92938 --- /dev/null +++ b/pac/atsamda1j/src/dmac/chctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/chctrlb.rs b/pac/atsamda1j/src/dmac/chctrlb.rs new file mode 100644 index 00000000000..c52f6f8de35 --- /dev/null +++ b/pac/atsamda1j/src/dmac/chctrlb.rs @@ -0,0 +1,1331 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Peripheral Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: SERCOM0 RX Trigger"] + SERCOM0_RX = 1, + #[doc = "2: SERCOM0 TX Trigger"] + SERCOM0_TX = 2, + #[doc = "3: SERCOM1 RX Trigger"] + SERCOM1_RX = 3, + #[doc = "4: SERCOM1 TX Trigger"] + SERCOM1_TX = 4, + #[doc = "5: SERCOM2 RX Trigger"] + SERCOM2_RX = 5, + #[doc = "6: SERCOM2 TX Trigger"] + SERCOM2_TX = 6, + #[doc = "7: SERCOM3 RX Trigger"] + SERCOM3_RX = 7, + #[doc = "8: SERCOM3 TX Trigger"] + SERCOM3_TX = 8, + #[doc = "9: SERCOM4 RX Trigger"] + SERCOM4_RX = 9, + #[doc = "10: SERCOM4 TX Trigger"] + SERCOM4_TX = 10, + #[doc = "11: SERCOM5 RX Trigger"] + SERCOM5_RX = 11, + #[doc = "12: SERCOM5 TX Trigger"] + SERCOM5_TX = 12, + #[doc = "13: TCC0 Overflow Trigger"] + TCC0_OVF = 13, + #[doc = "14: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 14, + #[doc = "15: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 15, + #[doc = "16: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 16, + #[doc = "17: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 17, + #[doc = "18: TCC1 Overflow Trigger"] + TCC1_OVF = 18, + #[doc = "19: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 19, + #[doc = "20: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 20, + #[doc = "21: TCC2 Overflow Trigger"] + TCC2_OVF = 21, + #[doc = "22: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 22, + #[doc = "23: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 23, + #[doc = "24: TC3 Overflow Trigger"] + TC3_OVF = 24, + #[doc = "25: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 25, + #[doc = "26: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 26, + #[doc = "27: TC4 Overflow Trigger"] + TC4_OVF = 27, + #[doc = "28: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 28, + #[doc = "29: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 29, + #[doc = "30: TC5 Overflow Trigger"] + TC5_OVF = 30, + #[doc = "31: TC5 Match/Compare 0 Trigger"] + TC5_MC0 = 31, + #[doc = "32: TC5 Match/Compare 1 Trigger"] + TC5_MC1 = 32, + #[doc = "33: TC6 Overflow Trigger"] + TC6_OVF = 33, + #[doc = "34: TC6 Match/Compare 0 Trigger"] + TC6_MC0 = 34, + #[doc = "35: TC6 Match/Compare 1 Trigger"] + TC6_MC1 = 35, + #[doc = "36: TC7 Overflow Trigger"] + TC7_OVF = 36, + #[doc = "37: TC7 Match/Compare 0 Trigger"] + TC7_MC0 = 37, + #[doc = "38: TC7 Match/Compare 1 Trigger"] + TC7_MC1 = 38, + #[doc = "39: ADC Result Ready Trigger"] + ADC_RESRDY = 39, + #[doc = "40: DAC Empty Trigger"] + DAC_EMPTY = 40, + #[doc = "41: I2S RX 0 Trigger"] + I2S_RX_0 = 41, + #[doc = "42: I2S RX 1 Trigger"] + I2S_RX_1 = 42, + #[doc = "43: I2S TX 0 Trigger"] + I2S_TX_0 = 43, + #[doc = "44: I2S TX 1 Trigger"] + I2S_TX_1 = 44, + #[doc = "45: TCC3 Overflow Trigger"] + TCC3_OVF = 45, + #[doc = "46: TCC3 Match/Compare 0 Trigger"] + TCC3_MC0 = 46, + #[doc = "47: TCC3 Match/Compare 1 Trigger"] + TCC3_MC1 = 47, + #[doc = "48: Match/Compare 2 Trigger"] + TCC3_MC2 = 48, + #[doc = "49: Match/Compare 3 Trigger"] + TCC3_MC3 = 49, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Peripheral Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::SERCOM0_RX), + 2 => Some(TRIGSRC_A::SERCOM0_TX), + 3 => Some(TRIGSRC_A::SERCOM1_RX), + 4 => Some(TRIGSRC_A::SERCOM1_TX), + 5 => Some(TRIGSRC_A::SERCOM2_RX), + 6 => Some(TRIGSRC_A::SERCOM2_TX), + 7 => Some(TRIGSRC_A::SERCOM3_RX), + 8 => Some(TRIGSRC_A::SERCOM3_TX), + 9 => Some(TRIGSRC_A::SERCOM4_RX), + 10 => Some(TRIGSRC_A::SERCOM4_TX), + 11 => Some(TRIGSRC_A::SERCOM5_RX), + 12 => Some(TRIGSRC_A::SERCOM5_TX), + 13 => Some(TRIGSRC_A::TCC0_OVF), + 14 => Some(TRIGSRC_A::TCC0_MC0), + 15 => Some(TRIGSRC_A::TCC0_MC1), + 16 => Some(TRIGSRC_A::TCC0_MC2), + 17 => Some(TRIGSRC_A::TCC0_MC3), + 18 => Some(TRIGSRC_A::TCC1_OVF), + 19 => Some(TRIGSRC_A::TCC1_MC0), + 20 => Some(TRIGSRC_A::TCC1_MC1), + 21 => Some(TRIGSRC_A::TCC2_OVF), + 22 => Some(TRIGSRC_A::TCC2_MC0), + 23 => Some(TRIGSRC_A::TCC2_MC1), + 24 => Some(TRIGSRC_A::TC3_OVF), + 25 => Some(TRIGSRC_A::TC3_MC0), + 26 => Some(TRIGSRC_A::TC3_MC1), + 27 => Some(TRIGSRC_A::TC4_OVF), + 28 => Some(TRIGSRC_A::TC4_MC0), + 29 => Some(TRIGSRC_A::TC4_MC1), + 30 => Some(TRIGSRC_A::TC5_OVF), + 31 => Some(TRIGSRC_A::TC5_MC0), + 32 => Some(TRIGSRC_A::TC5_MC1), + 33 => Some(TRIGSRC_A::TC6_OVF), + 34 => Some(TRIGSRC_A::TC6_MC0), + 35 => Some(TRIGSRC_A::TC6_MC1), + 36 => Some(TRIGSRC_A::TC7_OVF), + 37 => Some(TRIGSRC_A::TC7_MC0), + 38 => Some(TRIGSRC_A::TC7_MC1), + 39 => Some(TRIGSRC_A::ADC_RESRDY), + 40 => Some(TRIGSRC_A::DAC_EMPTY), + 41 => Some(TRIGSRC_A::I2S_RX_0), + 42 => Some(TRIGSRC_A::I2S_RX_1), + 43 => Some(TRIGSRC_A::I2S_TX_0), + 44 => Some(TRIGSRC_A::I2S_TX_1), + 45 => Some(TRIGSRC_A::TCC3_OVF), + 46 => Some(TRIGSRC_A::TCC3_MC0), + 47 => Some(TRIGSRC_A::TCC3_MC1), + 48 => Some(TRIGSRC_A::TCC3_MC2), + 49 => Some(TRIGSRC_A::TCC3_MC3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `TC5_OVF`"] + #[inline(always)] + pub fn is_tc5_ovf(&self) -> bool { + **self == TRIGSRC_A::TC5_OVF + } + #[doc = "Checks if the value of the field is `TC5_MC0`"] + #[inline(always)] + pub fn is_tc5_mc0(&self) -> bool { + **self == TRIGSRC_A::TC5_MC0 + } + #[doc = "Checks if the value of the field is `TC5_MC1`"] + #[inline(always)] + pub fn is_tc5_mc1(&self) -> bool { + **self == TRIGSRC_A::TC5_MC1 + } + #[doc = "Checks if the value of the field is `TC6_OVF`"] + #[inline(always)] + pub fn is_tc6_ovf(&self) -> bool { + **self == TRIGSRC_A::TC6_OVF + } + #[doc = "Checks if the value of the field is `TC6_MC0`"] + #[inline(always)] + pub fn is_tc6_mc0(&self) -> bool { + **self == TRIGSRC_A::TC6_MC0 + } + #[doc = "Checks if the value of the field is `TC6_MC1`"] + #[inline(always)] + pub fn is_tc6_mc1(&self) -> bool { + **self == TRIGSRC_A::TC6_MC1 + } + #[doc = "Checks if the value of the field is `TC7_OVF`"] + #[inline(always)] + pub fn is_tc7_ovf(&self) -> bool { + **self == TRIGSRC_A::TC7_OVF + } + #[doc = "Checks if the value of the field is `TC7_MC0`"] + #[inline(always)] + pub fn is_tc7_mc0(&self) -> bool { + **self == TRIGSRC_A::TC7_MC0 + } + #[doc = "Checks if the value of the field is `TC7_MC1`"] + #[inline(always)] + pub fn is_tc7_mc1(&self) -> bool { + **self == TRIGSRC_A::TC7_MC1 + } + #[doc = "Checks if the value of the field is `ADC_RESRDY`"] + #[inline(always)] + pub fn is_adc_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `I2S_RX_0`"] + #[inline(always)] + pub fn is_i2s_rx_0(&self) -> bool { + **self == TRIGSRC_A::I2S_RX_0 + } + #[doc = "Checks if the value of the field is `I2S_RX_1`"] + #[inline(always)] + pub fn is_i2s_rx_1(&self) -> bool { + **self == TRIGSRC_A::I2S_RX_1 + } + #[doc = "Checks if the value of the field is `I2S_TX_0`"] + #[inline(always)] + pub fn is_i2s_tx_0(&self) -> bool { + **self == TRIGSRC_A::I2S_TX_0 + } + #[doc = "Checks if the value of the field is `I2S_TX_1`"] + #[inline(always)] + pub fn is_i2s_tx_1(&self) -> bool { + **self == TRIGSRC_A::I2S_TX_1 + } + #[doc = "Checks if the value of the field is `TCC3_OVF`"] + #[inline(always)] + pub fn is_tcc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC3_OVF + } + #[doc = "Checks if the value of the field is `TCC3_MC0`"] + #[inline(always)] + pub fn is_tcc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC0 + } + #[doc = "Checks if the value of the field is `TCC3_MC1`"] + #[inline(always)] + pub fn is_tcc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC1 + } + #[doc = "Checks if the value of the field is `TCC3_MC2`"] + #[inline(always)] + pub fn is_tcc3_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC2 + } + #[doc = "Checks if the value of the field is `TCC3_MC3`"] + #[inline(always)] + pub fn is_tcc3_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC3_MC3 + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Peripheral Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "TC5 Overflow Trigger"] + #[inline(always)] + pub fn tc5_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_OVF) + } + #[doc = "TC5 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc5_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC0) + } + #[doc = "TC5 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc5_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC1) + } + #[doc = "TC6 Overflow Trigger"] + #[inline(always)] + pub fn tc6_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_OVF) + } + #[doc = "TC6 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc6_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC0) + } + #[doc = "TC6 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc6_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC1) + } + #[doc = "TC7 Overflow Trigger"] + #[inline(always)] + pub fn tc7_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_OVF) + } + #[doc = "TC7 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc7_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC0) + } + #[doc = "TC7 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc7_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC1) + } + #[doc = "ADC Result Ready Trigger"] + #[inline(always)] + pub fn adc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "I2S RX 0 Trigger"] + #[inline(always)] + pub fn i2s_rx_0(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_RX_0) + } + #[doc = "I2S RX 1 Trigger"] + #[inline(always)] + pub fn i2s_rx_1(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_RX_1) + } + #[doc = "I2S TX 0 Trigger"] + #[inline(always)] + pub fn i2s_tx_0(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_TX_0) + } + #[doc = "I2S TX 1 Trigger"] + #[inline(always)] + pub fn i2s_tx_1(self) -> &'a mut W { + self.variant(TRIGSRC_A::I2S_TX_1) + } + #[doc = "TCC3 Overflow Trigger"] + #[inline(always)] + pub fn tcc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_OVF) + } + #[doc = "TCC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC0) + } + #[doc = "TCC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC1) + } + #[doc = "Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc3_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC2) + } + #[doc = "Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc3_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC3_MC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Peripheral Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Peripheral Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/chid.rs b/pac/atsamda1j/src/dmac/chid.rs new file mode 100644 index 00000000000..19151d8e10b --- /dev/null +++ b/pac/atsamda1j/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/chintenclr.rs b/pac/atsamda1j/src/dmac/chintenclr.rs new file mode 100644 index 00000000000..e9e3e0d2e41 --- /dev/null +++ b/pac/atsamda1j/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/chintenset.rs b/pac/atsamda1j/src/dmac/chintenset.rs new file mode 100644 index 00000000000..473843d7f81 --- /dev/null +++ b/pac/atsamda1j/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/chintflag.rs b/pac/atsamda1j/src/dmac/chintflag.rs new file mode 100644 index 00000000000..dd8e72546c1 --- /dev/null +++ b/pac/atsamda1j/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/chstatus.rs b/pac/atsamda1j/src/dmac/chstatus.rs new file mode 100644 index 00000000000..f9432e61dab --- /dev/null +++ b/pac/atsamda1j/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/crcchksum.rs b/pac/atsamda1j/src/dmac/crcchksum.rs new file mode 100644 index 00000000000..89eb5b38a09 --- /dev/null +++ b/pac/atsamda1j/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/crcctrl.rs b/pac/atsamda1j/src/dmac/crcctrl.rs new file mode 100644 index 00000000000..a1d022dd9e6 --- /dev/null +++ b/pac/atsamda1j/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: Byte bus access"] + BYTE = 0, + #[doc = "1: Half-word bus access"] + HWORD = 1, + #[doc = "2: Word bus access"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Byte bus access"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "Half-word bus access"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "Word bus access"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/crcdatain.rs b/pac/atsamda1j/src/dmac/crcdatain.rs new file mode 100644 index 00000000000..ca0879a1213 --- /dev/null +++ b/pac/atsamda1j/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/crcstatus.rs b/pac/atsamda1j/src/dmac/crcstatus.rs new file mode 100644 index 00000000000..a132e9d5cd0 --- /dev/null +++ b/pac/atsamda1j/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/ctrl.rs b/pac/atsamda1j/src/dmac/ctrl.rs new file mode 100644 index 00000000000..fabae9d82a6 --- /dev/null +++ b/pac/atsamda1j/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/dbgctrl.rs b/pac/atsamda1j/src/dmac/dbgctrl.rs new file mode 100644 index 00000000000..53636eb2b33 --- /dev/null +++ b/pac/atsamda1j/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/intpend.rs b/pac/atsamda1j/src/dmac/intpend.rs new file mode 100644 index 00000000000..a107c4c32e6 --- /dev/null +++ b/pac/atsamda1j/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/intstatus.rs b/pac/atsamda1j/src/dmac/intstatus.rs new file mode 100644 index 00000000000..74a836f4a2f --- /dev/null +++ b/pac/atsamda1j/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/pendch.rs b/pac/atsamda1j/src/dmac/pendch.rs new file mode 100644 index 00000000000..8bb68ff8fa5 --- /dev/null +++ b/pac/atsamda1j/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/prictrl0.rs b/pac/atsamda1j/src/dmac/prictrl0.rs new file mode 100644 index 00000000000..ad795d0ba68 --- /dev/null +++ b/pac/atsamda1j/src/dmac/prictrl0.rs @@ -0,0 +1,402 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/qosctrl.rs b/pac/atsamda1j/src/dmac/qosctrl.rs new file mode 100644 index 00000000000..2f8906f0614 --- /dev/null +++ b/pac/atsamda1j/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x15"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x15 + } +} diff --git a/pac/atsamda1j/src/dmac/swtrigctrl.rs b/pac/atsamda1j/src/dmac/swtrigctrl.rs new file mode 100644 index 00000000000..8590fef852d --- /dev/null +++ b/pac/atsamda1j/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dmac/wrbaddr.rs b/pac/atsamda1j/src/dmac/wrbaddr.rs new file mode 100644 index 00000000000..ccf2a376b85 --- /dev/null +++ b/pac/atsamda1j/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu.rs b/pac/atsamda1j/src/dsu.rs new file mode 100644 index 00000000000..499c49a0262 --- /dev/null +++ b/pac/atsamda1j/src/dsu.rs @@ -0,0 +1,134 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved8: [u8; 0x0fe4], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved11: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + _reserved13: [u8; 0x0c], + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamda1j/src/dsu/addr.rs b/pac/atsamda1j/src/dsu/addr.rs new file mode 100644 index 00000000000..1e0a7ad719c --- /dev/null +++ b/pac/atsamda1j/src/dsu/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/cid0.rs b/pac/atsamda1j/src/dsu/cid0.rs new file mode 100644 index 00000000000..b3c2373dfc9 --- /dev/null +++ b/pac/atsamda1j/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamda1j/src/dsu/cid1.rs b/pac/atsamda1j/src/dsu/cid1.rs new file mode 100644 index 00000000000..3628ceac64a --- /dev/null +++ b/pac/atsamda1j/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1j/src/dsu/cid2.rs b/pac/atsamda1j/src/dsu/cid2.rs new file mode 100644 index 00000000000..714078d5c43 --- /dev/null +++ b/pac/atsamda1j/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1j/src/dsu/cid3.rs b/pac/atsamda1j/src/dsu/cid3.rs new file mode 100644 index 00000000000..a345af7b516 --- /dev/null +++ b/pac/atsamda1j/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamda1j/src/dsu/ctrl.rs b/pac/atsamda1j/src/dsu/ctrl.rs new file mode 100644 index 00000000000..ab4b0cd332d --- /dev/null +++ b/pac/atsamda1j/src/dsu/ctrl.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Check"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory Built-In Self-Test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Check"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory Built-In Self-Test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/data.rs b/pac/atsamda1j/src/dsu/data.rs new file mode 100644 index 00000000000..193cc49a07f --- /dev/null +++ b/pac/atsamda1j/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/dcc.rs b/pac/atsamda1j/src/dsu/dcc.rs new file mode 100644 index 00000000000..354323a499e --- /dev/null +++ b/pac/atsamda1j/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/did.rs b/pac/atsamda1j/src/dsu/did.rs new file mode 100644 index 00000000000..24f997da8dd --- /dev/null +++ b/pac/atsamda1j/src/dsu/did.rs @@ -0,0 +1,153 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Identification"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERIES` reader - Product Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAMILY` reader - Product Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Identification"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Product Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Product Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1001_1564"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1001_1564 + } +} diff --git a/pac/atsamda1j/src/dsu/end.rs b/pac/atsamda1j/src/dsu/end.rs new file mode 100644 index 00000000000..cce2edea2bc --- /dev/null +++ b/pac/atsamda1j/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/entry0.rs b/pac/atsamda1j/src/dsu/entry0.rs new file mode 100644 index 00000000000..d8563990e82 --- /dev/null +++ b/pac/atsamda1j/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamda1j/src/dsu/entry1.rs b/pac/atsamda1j/src/dsu/entry1.rs new file mode 100644 index 00000000000..8a5358aaa93 --- /dev/null +++ b/pac/atsamda1j/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x3002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3002 + } +} diff --git a/pac/atsamda1j/src/dsu/length.rs b/pac/atsamda1j/src/dsu/length.rs new file mode 100644 index 00000000000..2dc771f74df --- /dev/null +++ b/pac/atsamda1j/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/memtype.rs b/pac/atsamda1j/src/dsu/memtype.rs new file mode 100644 index 00000000000..3cc841e2ba7 --- /dev/null +++ b/pac/atsamda1j/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/pid0.rs b/pac/atsamda1j/src/dsu/pid0.rs new file mode 100644 index 00000000000..98028ea6283 --- /dev/null +++ b/pac/atsamda1j/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamda1j/src/dsu/pid1.rs b/pac/atsamda1j/src/dsu/pid1.rs new file mode 100644 index 00000000000..4f94b853507 --- /dev/null +++ b/pac/atsamda1j/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamda1j/src/dsu/pid2.rs b/pac/atsamda1j/src/dsu/pid2.rs new file mode 100644 index 00000000000..d8f8ed10192 --- /dev/null +++ b/pac/atsamda1j/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamda1j/src/dsu/pid3.rs b/pac/atsamda1j/src/dsu/pid3.rs new file mode 100644 index 00000000000..c0a8fb2d7f9 --- /dev/null +++ b/pac/atsamda1j/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/pid4.rs b/pac/atsamda1j/src/dsu/pid4.rs new file mode 100644 index 00000000000..d239852ee8f --- /dev/null +++ b/pac/atsamda1j/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB Count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB Count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/statusa.rs b/pac/atsamda1j/src/dsu/statusa.rs new file mode 100644 index 00000000000..c7b90a13e49 --- /dev/null +++ b/pac/atsamda1j/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/dsu/statusb.rs b/pac/atsamda1j/src/dsu/statusb.rs new file mode 100644 index 00000000000..3dc6ea897d3 --- /dev/null +++ b/pac/atsamda1j/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x10"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1j/src/eic.rs b/pac/atsamda1j/src/eic.rs new file mode 100644 index 00000000000..dcfa8655a9f --- /dev/null +++ b/pac/atsamda1j/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status"] + pub status: crate::Reg, + #[doc = "0x02 - Non-Maskable Interrupt Control"] + pub nmictrl: crate::Reg, + #[doc = "0x03 - Non-Maskable Interrupt Flag Status and Clear"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0c - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x10 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x14 - Wake-Up Enable"] + pub wakeup: crate::Reg, + #[doc = "0x18..0x20 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "Non-Maskable Interrupt Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "Non-Maskable Interrupt Flag Status and Clear"] +pub mod nmiflag; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "WAKEUP register accessor: an alias for `Reg`"] +pub type WAKEUP = crate::Reg; +#[doc = "Wake-Up Enable"] +pub mod wakeup; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamda1j/src/eic/config.rs b/pac/atsamda1j/src/eic/config.rs new file mode 100644 index 00000000000..5223e0514d5 --- /dev/null +++ b/pac/atsamda1j/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense 0 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense 0 Configuration"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense 0 Configuration"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter 0 Enable"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter 0 Enable"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense 1 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense 1 Configuration"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense 1 Configuration"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter 1 Enable"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter 1 Enable"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense 2 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense 2 Configuration"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense 2 Configuration"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter 2 Enable"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter 2 Enable"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense 3 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense 3 Configuration"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense 3 Configuration"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter 3 Enable"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter 3 Enable"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense 4 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense 4 Configuration"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense 4 Configuration"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter 4 Enable"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter 4 Enable"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense 5 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense 5 Configuration"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense 5 Configuration"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter 5 Enable"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter 5 Enable"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense 6 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense 6 Configuration"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense 6 Configuration"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter 6 Enable"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter 6 Enable"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense 7 Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense 7 Configuration"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense 7 Configuration"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter 7 Enable"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter 7 Enable"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense 0 Configuration"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter 0 Enable"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense 1 Configuration"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter 1 Enable"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense 2 Configuration"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter 2 Enable"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense 3 Configuration"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter 3 Enable"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense 4 Configuration"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter 4 Enable"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense 5 Configuration"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter 5 Enable"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense 6 Configuration"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter 6 Enable"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense 7 Configuration"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter 7 Enable"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense 0 Configuration"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter 0 Enable"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense 1 Configuration"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter 1 Enable"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense 2 Configuration"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter 2 Enable"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense 3 Configuration"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter 3 Enable"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense 4 Configuration"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter 4 Enable"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense 5 Configuration"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter 5 Enable"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense 6 Configuration"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter 6 Enable"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense 7 Configuration"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter 7 Enable"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/ctrl.rs b/pac/atsamda1j/src/eic/ctrl.rs new file mode 100644 index 00000000000..3d5f7d86a1f --- /dev/null +++ b/pac/atsamda1j/src/eic/ctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/evctrl.rs b/pac/atsamda1j/src/eic/evctrl.rs new file mode 100644 index 00000000000..660952cdc88 --- /dev/null +++ b/pac/atsamda1j/src/eic/evctrl.rs @@ -0,0 +1,818 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO0` reader - External Interrupt 0 Event Output Enable"] +pub struct EXTINTEO0_R(crate::FieldReader); +impl EXTINTEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO0` writer - External Interrupt 0 Event Output Enable"] +pub struct EXTINTEO0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINTEO1` reader - External Interrupt 1 Event Output Enable"] +pub struct EXTINTEO1_R(crate::FieldReader); +impl EXTINTEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO1` writer - External Interrupt 1 Event Output Enable"] +pub struct EXTINTEO1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINTEO2` reader - External Interrupt 2 Event Output Enable"] +pub struct EXTINTEO2_R(crate::FieldReader); +impl EXTINTEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO2` writer - External Interrupt 2 Event Output Enable"] +pub struct EXTINTEO2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINTEO3` reader - External Interrupt 3 Event Output Enable"] +pub struct EXTINTEO3_R(crate::FieldReader); +impl EXTINTEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO3` writer - External Interrupt 3 Event Output Enable"] +pub struct EXTINTEO3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINTEO4` reader - External Interrupt 4 Event Output Enable"] +pub struct EXTINTEO4_R(crate::FieldReader); +impl EXTINTEO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO4` writer - External Interrupt 4 Event Output Enable"] +pub struct EXTINTEO4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINTEO5` reader - External Interrupt 5 Event Output Enable"] +pub struct EXTINTEO5_R(crate::FieldReader); +impl EXTINTEO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO5` writer - External Interrupt 5 Event Output Enable"] +pub struct EXTINTEO5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINTEO6` reader - External Interrupt 6 Event Output Enable"] +pub struct EXTINTEO6_R(crate::FieldReader); +impl EXTINTEO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO6` writer - External Interrupt 6 Event Output Enable"] +pub struct EXTINTEO6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINTEO7` reader - External Interrupt 7 Event Output Enable"] +pub struct EXTINTEO7_R(crate::FieldReader); +impl EXTINTEO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO7` writer - External Interrupt 7 Event Output Enable"] +pub struct EXTINTEO7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINTEO8` reader - External Interrupt 8 Event Output Enable"] +pub struct EXTINTEO8_R(crate::FieldReader); +impl EXTINTEO8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO8` writer - External Interrupt 8 Event Output Enable"] +pub struct EXTINTEO8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINTEO9` reader - External Interrupt 9 Event Output Enable"] +pub struct EXTINTEO9_R(crate::FieldReader); +impl EXTINTEO9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO9` writer - External Interrupt 9 Event Output Enable"] +pub struct EXTINTEO9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINTEO10` reader - External Interrupt 10 Event Output Enable"] +pub struct EXTINTEO10_R(crate::FieldReader); +impl EXTINTEO10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO10` writer - External Interrupt 10 Event Output Enable"] +pub struct EXTINTEO10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINTEO11` reader - External Interrupt 11 Event Output Enable"] +pub struct EXTINTEO11_R(crate::FieldReader); +impl EXTINTEO11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO11` writer - External Interrupt 11 Event Output Enable"] +pub struct EXTINTEO11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINTEO12` reader - External Interrupt 12 Event Output Enable"] +pub struct EXTINTEO12_R(crate::FieldReader); +impl EXTINTEO12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO12` writer - External Interrupt 12 Event Output Enable"] +pub struct EXTINTEO12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINTEO13` reader - External Interrupt 13 Event Output Enable"] +pub struct EXTINTEO13_R(crate::FieldReader); +impl EXTINTEO13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO13` writer - External Interrupt 13 Event Output Enable"] +pub struct EXTINTEO13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINTEO14` reader - External Interrupt 14 Event Output Enable"] +pub struct EXTINTEO14_R(crate::FieldReader); +impl EXTINTEO14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO14` writer - External Interrupt 14 Event Output Enable"] +pub struct EXTINTEO14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINTEO15` reader - External Interrupt 15 Event Output Enable"] +pub struct EXTINTEO15_R(crate::FieldReader); +impl EXTINTEO15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINTEO15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO15` writer - External Interrupt 15 Event Output Enable"] +pub struct EXTINTEO15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] + #[inline(always)] + pub fn extinteo0(&self) -> EXTINTEO0_R { + EXTINTEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] + #[inline(always)] + pub fn extinteo1(&self) -> EXTINTEO1_R { + EXTINTEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] + #[inline(always)] + pub fn extinteo2(&self) -> EXTINTEO2_R { + EXTINTEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] + #[inline(always)] + pub fn extinteo3(&self) -> EXTINTEO3_R { + EXTINTEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] + #[inline(always)] + pub fn extinteo4(&self) -> EXTINTEO4_R { + EXTINTEO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] + #[inline(always)] + pub fn extinteo5(&self) -> EXTINTEO5_R { + EXTINTEO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] + #[inline(always)] + pub fn extinteo6(&self) -> EXTINTEO6_R { + EXTINTEO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] + #[inline(always)] + pub fn extinteo7(&self) -> EXTINTEO7_R { + EXTINTEO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] + #[inline(always)] + pub fn extinteo8(&self) -> EXTINTEO8_R { + EXTINTEO8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] + #[inline(always)] + pub fn extinteo9(&self) -> EXTINTEO9_R { + EXTINTEO9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] + #[inline(always)] + pub fn extinteo10(&self) -> EXTINTEO10_R { + EXTINTEO10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] + #[inline(always)] + pub fn extinteo11(&self) -> EXTINTEO11_R { + EXTINTEO11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] + #[inline(always)] + pub fn extinteo12(&self) -> EXTINTEO12_R { + EXTINTEO12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] + #[inline(always)] + pub fn extinteo13(&self) -> EXTINTEO13_R { + EXTINTEO13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] + #[inline(always)] + pub fn extinteo14(&self) -> EXTINTEO14_R { + EXTINTEO14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] + #[inline(always)] + pub fn extinteo15(&self) -> EXTINTEO15_R { + EXTINTEO15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] + #[inline(always)] + pub fn extinteo0(&mut self) -> EXTINTEO0_W { + EXTINTEO0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] + #[inline(always)] + pub fn extinteo1(&mut self) -> EXTINTEO1_W { + EXTINTEO1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] + #[inline(always)] + pub fn extinteo2(&mut self) -> EXTINTEO2_W { + EXTINTEO2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] + #[inline(always)] + pub fn extinteo3(&mut self) -> EXTINTEO3_W { + EXTINTEO3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] + #[inline(always)] + pub fn extinteo4(&mut self) -> EXTINTEO4_W { + EXTINTEO4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] + #[inline(always)] + pub fn extinteo5(&mut self) -> EXTINTEO5_W { + EXTINTEO5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] + #[inline(always)] + pub fn extinteo6(&mut self) -> EXTINTEO6_W { + EXTINTEO6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] + #[inline(always)] + pub fn extinteo7(&mut self) -> EXTINTEO7_W { + EXTINTEO7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] + #[inline(always)] + pub fn extinteo8(&mut self) -> EXTINTEO8_W { + EXTINTEO8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] + #[inline(always)] + pub fn extinteo9(&mut self) -> EXTINTEO9_W { + EXTINTEO9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] + #[inline(always)] + pub fn extinteo10(&mut self) -> EXTINTEO10_W { + EXTINTEO10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] + #[inline(always)] + pub fn extinteo11(&mut self) -> EXTINTEO11_W { + EXTINTEO11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] + #[inline(always)] + pub fn extinteo12(&mut self) -> EXTINTEO12_W { + EXTINTEO12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] + #[inline(always)] + pub fn extinteo13(&mut self) -> EXTINTEO13_W { + EXTINTEO13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] + #[inline(always)] + pub fn extinteo14(&mut self) -> EXTINTEO14_W { + EXTINTEO14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] + #[inline(always)] + pub fn extinteo15(&mut self) -> EXTINTEO15_W { + EXTINTEO15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/intenclr.rs b/pac/atsamda1j/src/eic/intenclr.rs new file mode 100644 index 00000000000..e8e877b5ed3 --- /dev/null +++ b/pac/atsamda1j/src/eic/intenclr.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0 Enable"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0 Enable"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1 Enable"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1 Enable"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2 Enable"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2 Enable"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3 Enable"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3 Enable"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4 Enable"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4 Enable"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5 Enable"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5 Enable"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6 Enable"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6 Enable"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7 Enable"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7 Enable"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8 Enable"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8 Enable"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9 Enable"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9 Enable"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10 Enable"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10 Enable"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11 Enable"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11 Enable"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12 Enable"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12 Enable"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13 Enable"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13 Enable"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14 Enable"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14 Enable"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15 Enable"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15 Enable"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/intenset.rs b/pac/atsamda1j/src/eic/intenset.rs new file mode 100644 index 00000000000..2ff10d0def2 --- /dev/null +++ b/pac/atsamda1j/src/eic/intenset.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0 Enable"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0 Enable"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1 Enable"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1 Enable"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2 Enable"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2 Enable"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3 Enable"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3 Enable"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4 Enable"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4 Enable"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5 Enable"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5 Enable"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6 Enable"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6 Enable"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7 Enable"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7 Enable"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8 Enable"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8 Enable"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9 Enable"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9 Enable"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10 Enable"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10 Enable"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11 Enable"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11 Enable"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12 Enable"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12 Enable"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13 Enable"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13 Enable"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14 Enable"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14 Enable"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15 Enable"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15 Enable"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Enable"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Enable"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Enable"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Enable"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Enable"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Enable"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Enable"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Enable"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Enable"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Enable"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Enable"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Enable"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Enable"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Enable"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Enable"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Enable"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/intflag.rs b/pac/atsamda1j/src/eic/intflag.rs new file mode 100644 index 00000000000..057d3868ffd --- /dev/null +++ b/pac/atsamda1j/src/eic/intflag.rs @@ -0,0 +1,818 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT0` reader - External Interrupt 0"] +pub struct EXTINT0_R(crate::FieldReader); +impl EXTINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT0` writer - External Interrupt 0"] +pub struct EXTINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTINT1` reader - External Interrupt 1"] +pub struct EXTINT1_R(crate::FieldReader); +impl EXTINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT1` writer - External Interrupt 1"] +pub struct EXTINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EXTINT2` reader - External Interrupt 2"] +pub struct EXTINT2_R(crate::FieldReader); +impl EXTINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT2` writer - External Interrupt 2"] +pub struct EXTINT2_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EXTINT3` reader - External Interrupt 3"] +pub struct EXTINT3_R(crate::FieldReader); +impl EXTINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT3` writer - External Interrupt 3"] +pub struct EXTINT3_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTINT4` reader - External Interrupt 4"] +pub struct EXTINT4_R(crate::FieldReader); +impl EXTINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT4` writer - External Interrupt 4"] +pub struct EXTINT4_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EXTINT5` reader - External Interrupt 5"] +pub struct EXTINT5_R(crate::FieldReader); +impl EXTINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT5` writer - External Interrupt 5"] +pub struct EXTINT5_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EXTINT6` reader - External Interrupt 6"] +pub struct EXTINT6_R(crate::FieldReader); +impl EXTINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT6` writer - External Interrupt 6"] +pub struct EXTINT6_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `EXTINT7` reader - External Interrupt 7"] +pub struct EXTINT7_R(crate::FieldReader); +impl EXTINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT7` writer - External Interrupt 7"] +pub struct EXTINT7_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EXTINT8` reader - External Interrupt 8"] +pub struct EXTINT8_R(crate::FieldReader); +impl EXTINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT8` writer - External Interrupt 8"] +pub struct EXTINT8_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EXTINT9` reader - External Interrupt 9"] +pub struct EXTINT9_R(crate::FieldReader); +impl EXTINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT9` writer - External Interrupt 9"] +pub struct EXTINT9_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EXTINT10` reader - External Interrupt 10"] +pub struct EXTINT10_R(crate::FieldReader); +impl EXTINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT10` writer - External Interrupt 10"] +pub struct EXTINT10_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EXTINT11` reader - External Interrupt 11"] +pub struct EXTINT11_R(crate::FieldReader); +impl EXTINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT11` writer - External Interrupt 11"] +pub struct EXTINT11_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXTINT12` reader - External Interrupt 12"] +pub struct EXTINT12_R(crate::FieldReader); +impl EXTINT12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT12` writer - External Interrupt 12"] +pub struct EXTINT12_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EXTINT13` reader - External Interrupt 13"] +pub struct EXTINT13_R(crate::FieldReader); +impl EXTINT13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT13` writer - External Interrupt 13"] +pub struct EXTINT13_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EXTINT14` reader - External Interrupt 14"] +pub struct EXTINT14_R(crate::FieldReader); +impl EXTINT14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT14` writer - External Interrupt 14"] +pub struct EXTINT14_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EXTINT15` reader - External Interrupt 15"] +pub struct EXTINT15_R(crate::FieldReader); +impl EXTINT15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTINT15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT15` writer - External Interrupt 15"] +pub struct EXTINT15_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0"] + #[inline(always)] + pub fn extint0(&self) -> EXTINT0_R { + EXTINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1"] + #[inline(always)] + pub fn extint1(&self) -> EXTINT1_R { + EXTINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2"] + #[inline(always)] + pub fn extint2(&self) -> EXTINT2_R { + EXTINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3"] + #[inline(always)] + pub fn extint3(&self) -> EXTINT3_R { + EXTINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4"] + #[inline(always)] + pub fn extint4(&self) -> EXTINT4_R { + EXTINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5"] + #[inline(always)] + pub fn extint5(&self) -> EXTINT5_R { + EXTINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6"] + #[inline(always)] + pub fn extint6(&self) -> EXTINT6_R { + EXTINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7"] + #[inline(always)] + pub fn extint7(&self) -> EXTINT7_R { + EXTINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8"] + #[inline(always)] + pub fn extint8(&self) -> EXTINT8_R { + EXTINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9"] + #[inline(always)] + pub fn extint9(&self) -> EXTINT9_R { + EXTINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10"] + #[inline(always)] + pub fn extint10(&self) -> EXTINT10_R { + EXTINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11"] + #[inline(always)] + pub fn extint11(&self) -> EXTINT11_R { + EXTINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12"] + #[inline(always)] + pub fn extint12(&self) -> EXTINT12_R { + EXTINT12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13"] + #[inline(always)] + pub fn extint13(&self) -> EXTINT13_R { + EXTINT13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14"] + #[inline(always)] + pub fn extint14(&self) -> EXTINT14_R { + EXTINT14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15"] + #[inline(always)] + pub fn extint15(&self) -> EXTINT15_R { + EXTINT15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0"] + #[inline(always)] + pub fn extint0(&mut self) -> EXTINT0_W { + EXTINT0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1"] + #[inline(always)] + pub fn extint1(&mut self) -> EXTINT1_W { + EXTINT1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2"] + #[inline(always)] + pub fn extint2(&mut self) -> EXTINT2_W { + EXTINT2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3"] + #[inline(always)] + pub fn extint3(&mut self) -> EXTINT3_W { + EXTINT3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4"] + #[inline(always)] + pub fn extint4(&mut self) -> EXTINT4_W { + EXTINT4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5"] + #[inline(always)] + pub fn extint5(&mut self) -> EXTINT5_W { + EXTINT5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6"] + #[inline(always)] + pub fn extint6(&mut self) -> EXTINT6_W { + EXTINT6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7"] + #[inline(always)] + pub fn extint7(&mut self) -> EXTINT7_W { + EXTINT7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8"] + #[inline(always)] + pub fn extint8(&mut self) -> EXTINT8_W { + EXTINT8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9"] + #[inline(always)] + pub fn extint9(&mut self) -> EXTINT9_W { + EXTINT9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10"] + #[inline(always)] + pub fn extint10(&mut self) -> EXTINT10_W { + EXTINT10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11"] + #[inline(always)] + pub fn extint11(&mut self) -> EXTINT11_W { + EXTINT11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12"] + #[inline(always)] + pub fn extint12(&mut self) -> EXTINT12_W { + EXTINT12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13"] + #[inline(always)] + pub fn extint13(&mut self) -> EXTINT13_W { + EXTINT13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14"] + #[inline(always)] + pub fn extint14(&mut self) -> EXTINT14_W { + EXTINT14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15"] + #[inline(always)] + pub fn extint15(&mut self) -> EXTINT15_W { + EXTINT15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/nmictrl.rs b/pac/atsamda1j/src/eic/nmictrl.rs new file mode 100644 index 00000000000..9abdb233a86 --- /dev/null +++ b/pac/atsamda1j/src/eic/nmictrl.rs @@ -0,0 +1,251 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Non-Maskable Interrupt Sense\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - Non-Maskable Interrupt Sense"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - Non-Maskable Interrupt Sense"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/nmiflag.rs b/pac/atsamda1j/src/eic/nmiflag.rs new file mode 100644 index 00000000000..b2e0be1761d --- /dev/null +++ b/pac/atsamda1j/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - Non-Maskable Interrupt"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - Non-Maskable Interrupt"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/status.rs b/pac/atsamda1j/src/eic/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1j/src/eic/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/eic/wakeup.rs b/pac/atsamda1j/src/eic/wakeup.rs new file mode 100644 index 00000000000..2c5d046923a --- /dev/null +++ b/pac/atsamda1j/src/eic/wakeup.rs @@ -0,0 +1,818 @@ +#[doc = "Register `WAKEUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAKEUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WAKEUPEN0` reader - External Interrupt 0 Wake-up Enable"] +pub struct WAKEUPEN0_R(crate::FieldReader); +impl WAKEUPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN0` writer - External Interrupt 0 Wake-up Enable"] +pub struct WAKEUPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `WAKEUPEN1` reader - External Interrupt 1 Wake-up Enable"] +pub struct WAKEUPEN1_R(crate::FieldReader); +impl WAKEUPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN1` writer - External Interrupt 1 Wake-up Enable"] +pub struct WAKEUPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAKEUPEN2` reader - External Interrupt 2 Wake-up Enable"] +pub struct WAKEUPEN2_R(crate::FieldReader); +impl WAKEUPEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN2` writer - External Interrupt 2 Wake-up Enable"] +pub struct WAKEUPEN2_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WAKEUPEN3` reader - External Interrupt 3 Wake-up Enable"] +pub struct WAKEUPEN3_R(crate::FieldReader); +impl WAKEUPEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN3` writer - External Interrupt 3 Wake-up Enable"] +pub struct WAKEUPEN3_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUPEN4` reader - External Interrupt 4 Wake-up Enable"] +pub struct WAKEUPEN4_R(crate::FieldReader); +impl WAKEUPEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN4` writer - External Interrupt 4 Wake-up Enable"] +pub struct WAKEUPEN4_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WAKEUPEN5` reader - External Interrupt 5 Wake-up Enable"] +pub struct WAKEUPEN5_R(crate::FieldReader); +impl WAKEUPEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN5` writer - External Interrupt 5 Wake-up Enable"] +pub struct WAKEUPEN5_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `WAKEUPEN6` reader - External Interrupt 6 Wake-up Enable"] +pub struct WAKEUPEN6_R(crate::FieldReader); +impl WAKEUPEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN6` writer - External Interrupt 6 Wake-up Enable"] +pub struct WAKEUPEN6_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WAKEUPEN7` reader - External Interrupt 7 Wake-up Enable"] +pub struct WAKEUPEN7_R(crate::FieldReader); +impl WAKEUPEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN7` writer - External Interrupt 7 Wake-up Enable"] +pub struct WAKEUPEN7_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WAKEUPEN8` reader - External Interrupt 8 Wake-up Enable"] +pub struct WAKEUPEN8_R(crate::FieldReader); +impl WAKEUPEN8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN8` writer - External Interrupt 8 Wake-up Enable"] +pub struct WAKEUPEN8_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `WAKEUPEN9` reader - External Interrupt 9 Wake-up Enable"] +pub struct WAKEUPEN9_R(crate::FieldReader); +impl WAKEUPEN9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN9` writer - External Interrupt 9 Wake-up Enable"] +pub struct WAKEUPEN9_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `WAKEUPEN10` reader - External Interrupt 10 Wake-up Enable"] +pub struct WAKEUPEN10_R(crate::FieldReader); +impl WAKEUPEN10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN10` writer - External Interrupt 10 Wake-up Enable"] +pub struct WAKEUPEN10_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `WAKEUPEN11` reader - External Interrupt 11 Wake-up Enable"] +pub struct WAKEUPEN11_R(crate::FieldReader); +impl WAKEUPEN11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN11` writer - External Interrupt 11 Wake-up Enable"] +pub struct WAKEUPEN11_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `WAKEUPEN12` reader - External Interrupt 12 Wake-up Enable"] +pub struct WAKEUPEN12_R(crate::FieldReader); +impl WAKEUPEN12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN12` writer - External Interrupt 12 Wake-up Enable"] +pub struct WAKEUPEN12_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `WAKEUPEN13` reader - External Interrupt 13 Wake-up Enable"] +pub struct WAKEUPEN13_R(crate::FieldReader); +impl WAKEUPEN13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN13` writer - External Interrupt 13 Wake-up Enable"] +pub struct WAKEUPEN13_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `WAKEUPEN14` reader - External Interrupt 14 Wake-up Enable"] +pub struct WAKEUPEN14_R(crate::FieldReader); +impl WAKEUPEN14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN14` writer - External Interrupt 14 Wake-up Enable"] +pub struct WAKEUPEN14_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `WAKEUPEN15` reader - External Interrupt 15 Wake-up Enable"] +pub struct WAKEUPEN15_R(crate::FieldReader); +impl WAKEUPEN15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUPEN15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUPEN15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUPEN15` writer - External Interrupt 15 Wake-up Enable"] +pub struct WAKEUPEN15_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUPEN15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen0(&self) -> WAKEUPEN0_R { + WAKEUPEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen1(&self) -> WAKEUPEN1_R { + WAKEUPEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen2(&self) -> WAKEUPEN2_R { + WAKEUPEN2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen3(&self) -> WAKEUPEN3_R { + WAKEUPEN3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen4(&self) -> WAKEUPEN4_R { + WAKEUPEN4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen5(&self) -> WAKEUPEN5_R { + WAKEUPEN5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen6(&self) -> WAKEUPEN6_R { + WAKEUPEN6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen7(&self) -> WAKEUPEN7_R { + WAKEUPEN7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen8(&self) -> WAKEUPEN8_R { + WAKEUPEN8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen9(&self) -> WAKEUPEN9_R { + WAKEUPEN9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen10(&self) -> WAKEUPEN10_R { + WAKEUPEN10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen11(&self) -> WAKEUPEN11_R { + WAKEUPEN11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen12(&self) -> WAKEUPEN12_R { + WAKEUPEN12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen13(&self) -> WAKEUPEN13_R { + WAKEUPEN13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen14(&self) -> WAKEUPEN14_R { + WAKEUPEN14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen15(&self) -> WAKEUPEN15_R { + WAKEUPEN15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen0(&mut self) -> WAKEUPEN0_W { + WAKEUPEN0_W { w: self } + } + #[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen1(&mut self) -> WAKEUPEN1_W { + WAKEUPEN1_W { w: self } + } + #[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen2(&mut self) -> WAKEUPEN2_W { + WAKEUPEN2_W { w: self } + } + #[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen3(&mut self) -> WAKEUPEN3_W { + WAKEUPEN3_W { w: self } + } + #[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen4(&mut self) -> WAKEUPEN4_W { + WAKEUPEN4_W { w: self } + } + #[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen5(&mut self) -> WAKEUPEN5_W { + WAKEUPEN5_W { w: self } + } + #[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen6(&mut self) -> WAKEUPEN6_W { + WAKEUPEN6_W { w: self } + } + #[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen7(&mut self) -> WAKEUPEN7_W { + WAKEUPEN7_W { w: self } + } + #[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen8(&mut self) -> WAKEUPEN8_W { + WAKEUPEN8_W { w: self } + } + #[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen9(&mut self) -> WAKEUPEN9_W { + WAKEUPEN9_W { w: self } + } + #[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen10(&mut self) -> WAKEUPEN10_W { + WAKEUPEN10_W { w: self } + } + #[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen11(&mut self) -> WAKEUPEN11_W { + WAKEUPEN11_W { w: self } + } + #[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen12(&mut self) -> WAKEUPEN12_W { + WAKEUPEN12_W { w: self } + } + #[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen13(&mut self) -> WAKEUPEN13_W { + WAKEUPEN13_W { w: self } + } + #[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen14(&mut self) -> WAKEUPEN14_W { + WAKEUPEN14_W { w: self } + } + #[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] + #[inline(always)] + pub fn wakeupen15(&mut self) -> WAKEUPEN15_W { + WAKEUPEN15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Wake-Up Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wakeup](index.html) module"] +pub struct WAKEUP_SPEC; +impl crate::RegisterSpec for WAKEUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wakeup::R](R) reader structure"] +impl crate::Readable for WAKEUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wakeup::W](W) writer structure"] +impl crate::Writable for WAKEUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAKEUP to value 0"] +impl crate::Resettable for WAKEUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/evsys.rs b/pac/atsamda1j/src/evsys.rs new file mode 100644 index 00000000000..73f42bb8158 --- /dev/null +++ b/pac/atsamda1j/src/evsys.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Channel"] + pub channel: crate::Reg, + #[doc = "0x08 - User Multiplexer"] + pub user: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer"] +pub mod user; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; diff --git a/pac/atsamda1j/src/evsys/channel.rs b/pac/atsamda1j/src/evsys/channel.rs new file mode 100644 index 00000000000..e17ac9fdf25 --- /dev/null +++ b/pac/atsamda1j/src/evsys/channel.rs @@ -0,0 +1,398 @@ +#[doc = "Register `CHANNEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `SWEVT` reader - Software Event"] +pub struct SWEVT_R(crate::FieldReader); +impl SWEVT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWEVT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWEVT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWEVT` writer - Software Event"] +pub struct SWEVT_W<'a> { + w: &'a mut W, +} +impl<'a> SWEVT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 26)) | ((value as u32 & 0x03) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Software Event"] + #[inline(always)] + pub fn swevt(&self) -> SWEVT_R { + SWEVT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:25 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 26:27 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 26) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Bit 8 - Software Event"] + #[inline(always)] + pub fn swevt(&mut self) -> SWEVT_W { + SWEVT_W { w: self } + } + #[doc = "Bits 16:22 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 24:25 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 26:27 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL to value 0"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/evsys/chstatus.rs b/pac/atsamda1j/src/evsys/chstatus.rs new file mode 100644 index 00000000000..9f5bba4c55c --- /dev/null +++ b/pac/atsamda1j/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0x000f_00ff"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x000f_00ff + } +} diff --git a/pac/atsamda1j/src/evsys/ctrl.rs b/pac/atsamda1j/src/evsys/ctrl.rs new file mode 100644 index 00000000000..0c1cacd5ec1 --- /dev/null +++ b/pac/atsamda1j/src/evsys/ctrl.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `GCLKREQ` writer - Generic Clock Requests"] +pub struct GCLKREQ_W<'a> { + w: &'a mut W, +} +impl<'a> GCLKREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 4 - Generic Clock Requests"] + #[inline(always)] + pub fn gclkreq(&mut self) -> GCLKREQ_W { + GCLKREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/evsys/intenclr.rs b/pac/atsamda1j/src/evsys/intenclr.rs new file mode 100644 index 00000000000..bb007d3cdd4 --- /dev/null +++ b/pac/atsamda1j/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/evsys/intenset.rs b/pac/atsamda1j/src/evsys/intenset.rs new file mode 100644 index 00000000000..a2c0b908380 --- /dev/null +++ b/pac/atsamda1j/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/evsys/intflag.rs b/pac/atsamda1j/src/evsys/intflag.rs new file mode 100644 index 00000000000..7fac4593d6d --- /dev/null +++ b/pac/atsamda1j/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 9 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 10 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 11 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 12 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 13 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 14 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 15 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 16 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 17 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 18 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 19 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/evsys/user.rs b/pac/atsamda1j/src/evsys/user.rs new file mode 100644 index 00000000000..06019221dab --- /dev/null +++ b/pac/atsamda1j/src/evsys/user.rs @@ -0,0 +1,176 @@ +#[doc = "Register `USER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `USER` reader - User Multiplexer Selection"] +pub struct USER_R(crate::FieldReader); +impl USER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + USER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USER` writer - User Multiplexer Selection"] +pub struct USER_W<'a> { + w: &'a mut W, +} +impl<'a> USER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Channel Event Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHANNEL_A { + #[doc = "0: No Channel Output Selected"] + _0 = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHANNEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHANNEL_A::_0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == CHANNEL_A::_0 + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHANNEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Channel Output Selected"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(CHANNEL_A::_0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - User Multiplexer Selection"] + #[inline(always)] + pub fn user(&self) -> USER_R { + USER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - User Multiplexer Selection"] + #[inline(always)] + pub fn user(&mut self) -> USER_W { + USER_W { w: self } + } + #[doc = "Bits 8:12 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/gclk.rs b/pac/atsamda1j/src/gclk.rs new file mode 100644 index 00000000000..c8e002f5502 --- /dev/null +++ b/pac/atsamda1j/src/gclk.rs @@ -0,0 +1,34 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status"] + pub status: crate::Reg, + #[doc = "0x02 - Generic Clock Control"] + pub clkctrl: crate::Reg, + #[doc = "0x04 - Generic Clock Generator Control"] + pub genctrl: crate::Reg, + #[doc = "0x08 - Generic Clock Generator Division"] + pub gendiv: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "CLKCTRL register accessor: an alias for `Reg`"] +pub type CLKCTRL = crate::Reg; +#[doc = "Generic Clock Control"] +pub mod clkctrl; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "GENDIV register accessor: an alias for `Reg`"] +pub type GENDIV = crate::Reg; +#[doc = "Generic Clock Generator Division"] +pub mod gendiv; diff --git a/pac/atsamda1j/src/gclk/clkctrl.rs b/pac/atsamda1j/src/gclk/clkctrl.rs new file mode 100644 index 00000000000..513de299ef9 --- /dev/null +++ b/pac/atsamda1j/src/gclk/clkctrl.rs @@ -0,0 +1,865 @@ +#[doc = "Register `CLKCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Selection ID\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ID_A { + #[doc = "0: DFLL48"] + DFLL48 = 0, + #[doc = "1: FDPLL"] + FDPLL = 1, + #[doc = "2: FDPLL32K"] + FDPLL32K = 2, + #[doc = "3: WDT"] + WDT = 3, + #[doc = "4: RTC"] + RTC = 4, + #[doc = "5: EIC"] + EIC = 5, + #[doc = "6: USB"] + USB = 6, + #[doc = "7: EVSYS_0"] + EVSYS_0 = 7, + #[doc = "8: EVSYS_1"] + EVSYS_1 = 8, + #[doc = "9: EVSYS_2"] + EVSYS_2 = 9, + #[doc = "10: EVSYS_3"] + EVSYS_3 = 10, + #[doc = "11: EVSYS_4"] + EVSYS_4 = 11, + #[doc = "12: EVSYS_5"] + EVSYS_5 = 12, + #[doc = "13: EVSYS_6"] + EVSYS_6 = 13, + #[doc = "14: EVSYS_7"] + EVSYS_7 = 14, + #[doc = "15: EVSYS_8"] + EVSYS_8 = 15, + #[doc = "16: EVSYS_9"] + EVSYS_9 = 16, + #[doc = "17: EVSYS_10"] + EVSYS_10 = 17, + #[doc = "18: EVSYS_11"] + EVSYS_11 = 18, + #[doc = "19: SERCOMX_SLOW"] + SERCOMX_SLOW = 19, + #[doc = "20: SERCOM0_CORE"] + SERCOM0_CORE = 20, + #[doc = "21: SERCOM1_CORE"] + SERCOM1_CORE = 21, + #[doc = "22: SERCOM2_CORE"] + SERCOM2_CORE = 22, + #[doc = "23: SERCOM3_CORE"] + SERCOM3_CORE = 23, + #[doc = "24: SERCOM4_CORE"] + SERCOM4_CORE = 24, + #[doc = "25: SERCOM5_CORE"] + SERCOM5_CORE = 25, + #[doc = "26: TCC0_TCC1"] + TCC0_TCC1 = 26, + #[doc = "27: TCC2_TC3"] + TCC2_TC3 = 27, + #[doc = "28: TC4_TC5"] + TC4_TC5 = 28, + #[doc = "29: TC6_TC7"] + TC6_TC7 = 29, + #[doc = "30: ADC"] + ADC = 30, + #[doc = "31: AC_DIG"] + AC_DIG = 31, + #[doc = "32: AC_ANA"] + AC_ANA = 32, + #[doc = "33: DAC"] + DAC = 33, + #[doc = "35: I2S_0"] + I2S_0 = 35, + #[doc = "36: I2S_1"] + I2S_1 = 36, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ID_A) -> Self { + variant as _ + } +} +#[doc = "Field `ID` reader - Generic Clock Selection ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ID_A::DFLL48), + 1 => Some(ID_A::FDPLL), + 2 => Some(ID_A::FDPLL32K), + 3 => Some(ID_A::WDT), + 4 => Some(ID_A::RTC), + 5 => Some(ID_A::EIC), + 6 => Some(ID_A::USB), + 7 => Some(ID_A::EVSYS_0), + 8 => Some(ID_A::EVSYS_1), + 9 => Some(ID_A::EVSYS_2), + 10 => Some(ID_A::EVSYS_3), + 11 => Some(ID_A::EVSYS_4), + 12 => Some(ID_A::EVSYS_5), + 13 => Some(ID_A::EVSYS_6), + 14 => Some(ID_A::EVSYS_7), + 15 => Some(ID_A::EVSYS_8), + 16 => Some(ID_A::EVSYS_9), + 17 => Some(ID_A::EVSYS_10), + 18 => Some(ID_A::EVSYS_11), + 19 => Some(ID_A::SERCOMX_SLOW), + 20 => Some(ID_A::SERCOM0_CORE), + 21 => Some(ID_A::SERCOM1_CORE), + 22 => Some(ID_A::SERCOM2_CORE), + 23 => Some(ID_A::SERCOM3_CORE), + 24 => Some(ID_A::SERCOM4_CORE), + 25 => Some(ID_A::SERCOM5_CORE), + 26 => Some(ID_A::TCC0_TCC1), + 27 => Some(ID_A::TCC2_TC3), + 28 => Some(ID_A::TC4_TC5), + 29 => Some(ID_A::TC6_TC7), + 30 => Some(ID_A::ADC), + 31 => Some(ID_A::AC_DIG), + 32 => Some(ID_A::AC_ANA), + 33 => Some(ID_A::DAC), + 35 => Some(ID_A::I2S_0), + 36 => Some(ID_A::I2S_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DFLL48`"] + #[inline(always)] + pub fn is_dfll48(&self) -> bool { + **self == ID_A::DFLL48 + } + #[doc = "Checks if the value of the field is `FDPLL`"] + #[inline(always)] + pub fn is_fdpll(&self) -> bool { + **self == ID_A::FDPLL + } + #[doc = "Checks if the value of the field is `FDPLL32K`"] + #[inline(always)] + pub fn is_fdpll32k(&self) -> bool { + **self == ID_A::FDPLL32K + } + #[doc = "Checks if the value of the field is `WDT`"] + #[inline(always)] + pub fn is_wdt(&self) -> bool { + **self == ID_A::WDT + } + #[doc = "Checks if the value of the field is `RTC`"] + #[inline(always)] + pub fn is_rtc(&self) -> bool { + **self == ID_A::RTC + } + #[doc = "Checks if the value of the field is `EIC`"] + #[inline(always)] + pub fn is_eic(&self) -> bool { + **self == ID_A::EIC + } + #[doc = "Checks if the value of the field is `USB`"] + #[inline(always)] + pub fn is_usb(&self) -> bool { + **self == ID_A::USB + } + #[doc = "Checks if the value of the field is `EVSYS_0`"] + #[inline(always)] + pub fn is_evsys_0(&self) -> bool { + **self == ID_A::EVSYS_0 + } + #[doc = "Checks if the value of the field is `EVSYS_1`"] + #[inline(always)] + pub fn is_evsys_1(&self) -> bool { + **self == ID_A::EVSYS_1 + } + #[doc = "Checks if the value of the field is `EVSYS_2`"] + #[inline(always)] + pub fn is_evsys_2(&self) -> bool { + **self == ID_A::EVSYS_2 + } + #[doc = "Checks if the value of the field is `EVSYS_3`"] + #[inline(always)] + pub fn is_evsys_3(&self) -> bool { + **self == ID_A::EVSYS_3 + } + #[doc = "Checks if the value of the field is `EVSYS_4`"] + #[inline(always)] + pub fn is_evsys_4(&self) -> bool { + **self == ID_A::EVSYS_4 + } + #[doc = "Checks if the value of the field is `EVSYS_5`"] + #[inline(always)] + pub fn is_evsys_5(&self) -> bool { + **self == ID_A::EVSYS_5 + } + #[doc = "Checks if the value of the field is `EVSYS_6`"] + #[inline(always)] + pub fn is_evsys_6(&self) -> bool { + **self == ID_A::EVSYS_6 + } + #[doc = "Checks if the value of the field is `EVSYS_7`"] + #[inline(always)] + pub fn is_evsys_7(&self) -> bool { + **self == ID_A::EVSYS_7 + } + #[doc = "Checks if the value of the field is `EVSYS_8`"] + #[inline(always)] + pub fn is_evsys_8(&self) -> bool { + **self == ID_A::EVSYS_8 + } + #[doc = "Checks if the value of the field is `EVSYS_9`"] + #[inline(always)] + pub fn is_evsys_9(&self) -> bool { + **self == ID_A::EVSYS_9 + } + #[doc = "Checks if the value of the field is `EVSYS_10`"] + #[inline(always)] + pub fn is_evsys_10(&self) -> bool { + **self == ID_A::EVSYS_10 + } + #[doc = "Checks if the value of the field is `EVSYS_11`"] + #[inline(always)] + pub fn is_evsys_11(&self) -> bool { + **self == ID_A::EVSYS_11 + } + #[doc = "Checks if the value of the field is `SERCOMX_SLOW`"] + #[inline(always)] + pub fn is_sercomx_slow(&self) -> bool { + **self == ID_A::SERCOMX_SLOW + } + #[doc = "Checks if the value of the field is `SERCOM0_CORE`"] + #[inline(always)] + pub fn is_sercom0_core(&self) -> bool { + **self == ID_A::SERCOM0_CORE + } + #[doc = "Checks if the value of the field is `SERCOM1_CORE`"] + #[inline(always)] + pub fn is_sercom1_core(&self) -> bool { + **self == ID_A::SERCOM1_CORE + } + #[doc = "Checks if the value of the field is `SERCOM2_CORE`"] + #[inline(always)] + pub fn is_sercom2_core(&self) -> bool { + **self == ID_A::SERCOM2_CORE + } + #[doc = "Checks if the value of the field is `SERCOM3_CORE`"] + #[inline(always)] + pub fn is_sercom3_core(&self) -> bool { + **self == ID_A::SERCOM3_CORE + } + #[doc = "Checks if the value of the field is `SERCOM4_CORE`"] + #[inline(always)] + pub fn is_sercom4_core(&self) -> bool { + **self == ID_A::SERCOM4_CORE + } + #[doc = "Checks if the value of the field is `SERCOM5_CORE`"] + #[inline(always)] + pub fn is_sercom5_core(&self) -> bool { + **self == ID_A::SERCOM5_CORE + } + #[doc = "Checks if the value of the field is `TCC0_TCC1`"] + #[inline(always)] + pub fn is_tcc0_tcc1(&self) -> bool { + **self == ID_A::TCC0_TCC1 + } + #[doc = "Checks if the value of the field is `TCC2_TC3`"] + #[inline(always)] + pub fn is_tcc2_tc3(&self) -> bool { + **self == ID_A::TCC2_TC3 + } + #[doc = "Checks if the value of the field is `TC4_TC5`"] + #[inline(always)] + pub fn is_tc4_tc5(&self) -> bool { + **self == ID_A::TC4_TC5 + } + #[doc = "Checks if the value of the field is `TC6_TC7`"] + #[inline(always)] + pub fn is_tc6_tc7(&self) -> bool { + **self == ID_A::TC6_TC7 + } + #[doc = "Checks if the value of the field is `ADC`"] + #[inline(always)] + pub fn is_adc(&self) -> bool { + **self == ID_A::ADC + } + #[doc = "Checks if the value of the field is `AC_DIG`"] + #[inline(always)] + pub fn is_ac_dig(&self) -> bool { + **self == ID_A::AC_DIG + } + #[doc = "Checks if the value of the field is `AC_ANA`"] + #[inline(always)] + pub fn is_ac_ana(&self) -> bool { + **self == ID_A::AC_ANA + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == ID_A::DAC + } + #[doc = "Checks if the value of the field is `I2S_0`"] + #[inline(always)] + pub fn is_i2s_0(&self) -> bool { + **self == ID_A::I2S_0 + } + #[doc = "Checks if the value of the field is `I2S_1`"] + #[inline(always)] + pub fn is_i2s_1(&self) -> bool { + **self == ID_A::I2S_1 + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Selection ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ID_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DFLL48"] + #[inline(always)] + pub fn dfll48(self) -> &'a mut W { + self.variant(ID_A::DFLL48) + } + #[doc = "FDPLL"] + #[inline(always)] + pub fn fdpll(self) -> &'a mut W { + self.variant(ID_A::FDPLL) + } + #[doc = "FDPLL32K"] + #[inline(always)] + pub fn fdpll32k(self) -> &'a mut W { + self.variant(ID_A::FDPLL32K) + } + #[doc = "WDT"] + #[inline(always)] + pub fn wdt(self) -> &'a mut W { + self.variant(ID_A::WDT) + } + #[doc = "RTC"] + #[inline(always)] + pub fn rtc(self) -> &'a mut W { + self.variant(ID_A::RTC) + } + #[doc = "EIC"] + #[inline(always)] + pub fn eic(self) -> &'a mut W { + self.variant(ID_A::EIC) + } + #[doc = "USB"] + #[inline(always)] + pub fn usb(self) -> &'a mut W { + self.variant(ID_A::USB) + } + #[doc = "EVSYS_0"] + #[inline(always)] + pub fn evsys_0(self) -> &'a mut W { + self.variant(ID_A::EVSYS_0) + } + #[doc = "EVSYS_1"] + #[inline(always)] + pub fn evsys_1(self) -> &'a mut W { + self.variant(ID_A::EVSYS_1) + } + #[doc = "EVSYS_2"] + #[inline(always)] + pub fn evsys_2(self) -> &'a mut W { + self.variant(ID_A::EVSYS_2) + } + #[doc = "EVSYS_3"] + #[inline(always)] + pub fn evsys_3(self) -> &'a mut W { + self.variant(ID_A::EVSYS_3) + } + #[doc = "EVSYS_4"] + #[inline(always)] + pub fn evsys_4(self) -> &'a mut W { + self.variant(ID_A::EVSYS_4) + } + #[doc = "EVSYS_5"] + #[inline(always)] + pub fn evsys_5(self) -> &'a mut W { + self.variant(ID_A::EVSYS_5) + } + #[doc = "EVSYS_6"] + #[inline(always)] + pub fn evsys_6(self) -> &'a mut W { + self.variant(ID_A::EVSYS_6) + } + #[doc = "EVSYS_7"] + #[inline(always)] + pub fn evsys_7(self) -> &'a mut W { + self.variant(ID_A::EVSYS_7) + } + #[doc = "EVSYS_8"] + #[inline(always)] + pub fn evsys_8(self) -> &'a mut W { + self.variant(ID_A::EVSYS_8) + } + #[doc = "EVSYS_9"] + #[inline(always)] + pub fn evsys_9(self) -> &'a mut W { + self.variant(ID_A::EVSYS_9) + } + #[doc = "EVSYS_10"] + #[inline(always)] + pub fn evsys_10(self) -> &'a mut W { + self.variant(ID_A::EVSYS_10) + } + #[doc = "EVSYS_11"] + #[inline(always)] + pub fn evsys_11(self) -> &'a mut W { + self.variant(ID_A::EVSYS_11) + } + #[doc = "SERCOMX_SLOW"] + #[inline(always)] + pub fn sercomx_slow(self) -> &'a mut W { + self.variant(ID_A::SERCOMX_SLOW) + } + #[doc = "SERCOM0_CORE"] + #[inline(always)] + pub fn sercom0_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM0_CORE) + } + #[doc = "SERCOM1_CORE"] + #[inline(always)] + pub fn sercom1_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM1_CORE) + } + #[doc = "SERCOM2_CORE"] + #[inline(always)] + pub fn sercom2_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM2_CORE) + } + #[doc = "SERCOM3_CORE"] + #[inline(always)] + pub fn sercom3_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM3_CORE) + } + #[doc = "SERCOM4_CORE"] + #[inline(always)] + pub fn sercom4_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM4_CORE) + } + #[doc = "SERCOM5_CORE"] + #[inline(always)] + pub fn sercom5_core(self) -> &'a mut W { + self.variant(ID_A::SERCOM5_CORE) + } + #[doc = "TCC0_TCC1"] + #[inline(always)] + pub fn tcc0_tcc1(self) -> &'a mut W { + self.variant(ID_A::TCC0_TCC1) + } + #[doc = "TCC2_TC3"] + #[inline(always)] + pub fn tcc2_tc3(self) -> &'a mut W { + self.variant(ID_A::TCC2_TC3) + } + #[doc = "TC4_TC5"] + #[inline(always)] + pub fn tc4_tc5(self) -> &'a mut W { + self.variant(ID_A::TC4_TC5) + } + #[doc = "TC6_TC7"] + #[inline(always)] + pub fn tc6_tc7(self) -> &'a mut W { + self.variant(ID_A::TC6_TC7) + } + #[doc = "ADC"] + #[inline(always)] + pub fn adc(self) -> &'a mut W { + self.variant(ID_A::ADC) + } + #[doc = "AC_DIG"] + #[inline(always)] + pub fn ac_dig(self) -> &'a mut W { + self.variant(ID_A::AC_DIG) + } + #[doc = "AC_ANA"] + #[inline(always)] + pub fn ac_ana(self) -> &'a mut W { + self.variant(ID_A::AC_ANA) + } + #[doc = "DAC"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(ID_A::DAC) + } + #[doc = "I2S_0"] + #[inline(always)] + pub fn i2s_0(self) -> &'a mut W { + self.variant(ID_A::I2S_0) + } + #[doc = "I2S_1"] + #[inline(always)] + pub fn i2s_1(self) -> &'a mut W { + self.variant(ID_A::I2S_1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLKEN` reader - Clock Enable"] +pub struct CLKEN_R(crate::FieldReader); +impl CLKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKEN` writer - Clock Enable"] +pub struct CLKEN_W<'a> { + w: &'a mut W, +} +impl<'a> CLKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Generic Clock Selection ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:11 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 14 - Clock Enable"] + #[inline(always)] + pub fn clken(&self) -> CLKEN_R { + CLKEN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Generic Clock Selection ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:11 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 14 - Clock Enable"] + #[inline(always)] + pub fn clken(&mut self) -> CLKEN_W { + CLKEN_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkctrl](index.html) module"] +pub struct CLKCTRL_SPEC; +impl crate::RegisterSpec for CLKCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [clkctrl::R](R) reader structure"] +impl crate::Readable for CLKCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkctrl::W](W) writer structure"] +impl crate::Writable for CLKCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKCTRL to value 0"] +impl crate::Resettable for CLKCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/gclk/ctrl.rs b/pac/atsamda1j/src/gclk/ctrl.rs new file mode 100644 index 00000000000..2c4cbd696a1 --- /dev/null +++ b/pac/atsamda1j/src/gclk/ctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/gclk/genctrl.rs b/pac/atsamda1j/src/gclk/genctrl.rs new file mode 100644 index 00000000000..0c339999e03 --- /dev/null +++ b/pac/atsamda1j/src/gclk/genctrl.rs @@ -0,0 +1,609 @@ +#[doc = "Register `GENCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Generic Clock Generator Selection"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Generator Selection"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC8M oscillator output"] + OSC8M = 6, + #[doc = "7: DFLL48M output"] + DFLL48M = 7, + #[doc = "8: DPLL96M output"] + DPLL96M = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::XOSC), + 1 => Some(SRC_A::GCLKIN), + 2 => Some(SRC_A::GCLKGEN1), + 3 => Some(SRC_A::OSCULP32K), + 4 => Some(SRC_A::OSC32K), + 5 => Some(SRC_A::XOSC32K), + 6 => Some(SRC_A::OSC8M), + 7 => Some(SRC_A::DFLL48M), + 8 => Some(SRC_A::DPLL96M), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC8M`"] + #[inline(always)] + pub fn is_osc8m(&self) -> bool { + **self == SRC_A::OSC8M + } + #[doc = "Checks if the value of the field is `DFLL48M`"] + #[inline(always)] + pub fn is_dfll48m(&self) -> bool { + **self == SRC_A::DFLL48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC8M oscillator output"] + #[inline(always)] + pub fn osc8m(self) -> &'a mut W { + self.variant(SRC_A::OSC8M) + } + #[doc = "DFLL48M output"] + #[inline(always)] + pub fn dfll48m(self) -> &'a mut W { + self.variant(SRC_A::DFLL48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:12 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 16 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 17 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 18 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 19 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 20 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 21 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/gclk/gendiv.rs b/pac/atsamda1j/src/gclk/gendiv.rs new file mode 100644 index 00000000000..203d2e384c0 --- /dev/null +++ b/pac/atsamda1j/src/gclk/gendiv.rs @@ -0,0 +1,140 @@ +#[doc = "Register `GENDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Generic Clock Generator Selection"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Generic Clock Generator Selection"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 8)) | ((value as u32 & 0xffff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:23 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 8) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator Selection"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bits 8:23 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gendiv](index.html) module"] +pub struct GENDIV_SPEC; +impl crate::RegisterSpec for GENDIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gendiv::R](R) reader structure"] +impl crate::Readable for GENDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gendiv::W](W) writer structure"] +impl crate::Writable for GENDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENDIV to value 0"] +impl crate::Resettable for GENDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/gclk/status.rs b/pac/atsamda1j/src/gclk/status.rs new file mode 100644 index 00000000000..2667b356df2 --- /dev/null +++ b/pac/atsamda1j/src/gclk/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy Status"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy Status"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/generic.rs b/pac/atsamda1j/src/generic.rs new file mode 100644 index 00000000000..76159643acf --- /dev/null +++ b/pac/atsamda1j/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamda1j/src/i2s.rs b/pac/atsamda1j/src/i2s.rs new file mode 100644 index 00000000000..2a81ff75c9f --- /dev/null +++ b/pac/atsamda1j/src/i2s.rs @@ -0,0 +1,58 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04..0x0c - Clock Unit n Control"] + pub clkctrl: [crate::Reg; 2], + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x02], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x18 - Synchronization Status"] + pub syncbusy: crate::Reg, + _reserved6: [u8; 0x06], + #[doc = "0x20..0x28 - Serializer n Control"] + pub serctrl: [crate::Reg; 2], + _reserved7: [u8; 0x08], + #[doc = "0x30..0x38 - Data n"] + pub data: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CLKCTRL register accessor: an alias for `Reg`"] +pub type CLKCTRL = crate::Reg; +#[doc = "Clock Unit n Control"] +pub mod clkctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "SERCTRL register accessor: an alias for `Reg`"] +pub type SERCTRL = crate::Reg; +#[doc = "Serializer n Control"] +pub mod serctrl; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data n"] +pub mod data; diff --git a/pac/atsamda1j/src/i2s/clkctrl.rs b/pac/atsamda1j/src/i2s/clkctrl.rs new file mode 100644 index 00000000000..b2d71698332 --- /dev/null +++ b/pac/atsamda1j/src/i2s/clkctrl.rs @@ -0,0 +1,1013 @@ +#[doc = "Register `CLKCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Slot Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLOTSIZE_A { + #[doc = "0: 8-bit Slot for Clock Unit n"] + _8 = 0, + #[doc = "1: 16-bit Slot for Clock Unit n"] + _16 = 1, + #[doc = "2: 24-bit Slot for Clock Unit n"] + _24 = 2, + #[doc = "3: 32-bit Slot for Clock Unit n"] + _32 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLOTSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLOTSIZE` reader - Slot Size"] +pub struct SLOTSIZE_R(crate::FieldReader); +impl SLOTSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOTSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLOTSIZE_A { + match self.bits { + 0 => SLOTSIZE_A::_8, + 1 => SLOTSIZE_A::_16, + 2 => SLOTSIZE_A::_24, + 3 => SLOTSIZE_A::_32, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SLOTSIZE_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SLOTSIZE_A::_16 + } + #[doc = "Checks if the value of the field is `_24`"] + #[inline(always)] + pub fn is_24(&self) -> bool { + **self == SLOTSIZE_A::_24 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SLOTSIZE_A::_32 + } +} +impl core::ops::Deref for SLOTSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTSIZE` writer - Slot Size"] +pub struct SLOTSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLOTSIZE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_8) + } + #[doc = "16-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_16) + } + #[doc = "24-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _24(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_24) + } + #[doc = "32-bit Slot for Clock Unit n"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SLOTSIZE_A::_32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `NBSLOTS` reader - Number of Slots in Frame"] +pub struct NBSLOTS_R(crate::FieldReader); +impl NBSLOTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NBSLOTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NBSLOTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NBSLOTS` writer - Number of Slots in Frame"] +pub struct NBSLOTS_W<'a> { + w: &'a mut W, +} +impl<'a> NBSLOTS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Frame Sync Width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSWIDTH_A { + #[doc = "0: Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"] + SLOT = 0, + #[doc = "1: Frame Sync Pulse is half a Frame wide"] + HALF = 1, + #[doc = "2: Frame Sync Pulse is 1 Bit wide"] + BIT = 2, + #[doc = "3: Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"] + BURST = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSWIDTH_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSWIDTH` reader - Frame Sync Width"] +pub struct FSWIDTH_R(crate::FieldReader); +impl FSWIDTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSWIDTH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSWIDTH_A { + match self.bits { + 0 => FSWIDTH_A::SLOT, + 1 => FSWIDTH_A::HALF, + 2 => FSWIDTH_A::BIT, + 3 => FSWIDTH_A::BURST, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `SLOT`"] + #[inline(always)] + pub fn is_slot(&self) -> bool { + **self == FSWIDTH_A::SLOT + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == FSWIDTH_A::HALF + } + #[doc = "Checks if the value of the field is `BIT`"] + #[inline(always)] + pub fn is_bit_(&self) -> bool { + **self == FSWIDTH_A::BIT + } + #[doc = "Checks if the value of the field is `BURST`"] + #[inline(always)] + pub fn is_burst(&self) -> bool { + **self == FSWIDTH_A::BURST + } +} +impl core::ops::Deref for FSWIDTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSWIDTH` writer - Frame Sync Width"] +pub struct FSWIDTH_W<'a> { + w: &'a mut W, +} +impl<'a> FSWIDTH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FSWIDTH_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Frame Sync Pulse is 1 Slot wide (default for I2S protocol)"] + #[inline(always)] + pub fn slot(self) -> &'a mut W { + self.variant(FSWIDTH_A::SLOT) + } + #[doc = "Frame Sync Pulse is half a Frame wide"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(FSWIDTH_A::HALF) + } + #[doc = "Frame Sync Pulse is 1 Bit wide"] + #[inline(always)] + pub fn bit_(self) -> &'a mut W { + self.variant(FSWIDTH_A::BIT) + } + #[doc = "Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested"] + #[inline(always)] + pub fn burst(self) -> &'a mut W { + self.variant(FSWIDTH_A::BURST) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Data Delay from Frame Sync\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BITDELAY_A { + #[doc = "0: Left Justified (0 Bit Delay)"] + LJ = 0, + #[doc = "1: I2S (1 Bit Delay)"] + I2S = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BITDELAY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BITDELAY` reader - Data Delay from Frame Sync"] +pub struct BITDELAY_R(crate::FieldReader); +impl BITDELAY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BITDELAY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BITDELAY_A { + match self.bits { + false => BITDELAY_A::LJ, + true => BITDELAY_A::I2S, + } + } + #[doc = "Checks if the value of the field is `LJ`"] + #[inline(always)] + pub fn is_lj(&self) -> bool { + **self == BITDELAY_A::LJ + } + #[doc = "Checks if the value of the field is `I2S`"] + #[inline(always)] + pub fn is_i2s(&self) -> bool { + **self == BITDELAY_A::I2S + } +} +impl core::ops::Deref for BITDELAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITDELAY` writer - Data Delay from Frame Sync"] +pub struct BITDELAY_W<'a> { + w: &'a mut W, +} +impl<'a> BITDELAY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BITDELAY_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Left Justified (0 Bit Delay)"] + #[inline(always)] + pub fn lj(self) -> &'a mut W { + self.variant(BITDELAY_A::LJ) + } + #[doc = "I2S (1 Bit Delay)"] + #[inline(always)] + pub fn i2s(self) -> &'a mut W { + self.variant(BITDELAY_A::I2S) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Frame Sync Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum FSSEL_A { + #[doc = "0: Divided Serial Clock n is used as Frame Sync n source"] + SCKDIV = 0, + #[doc = "1: FSn input pin is used as Frame Sync n source"] + FSPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FSSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FSSEL` reader - Frame Sync Select"] +pub struct FSSEL_R(crate::FieldReader); +impl FSSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSSEL_A { + match self.bits { + false => FSSEL_A::SCKDIV, + true => FSSEL_A::FSPIN, + } + } + #[doc = "Checks if the value of the field is `SCKDIV`"] + #[inline(always)] + pub fn is_sckdiv(&self) -> bool { + **self == FSSEL_A::SCKDIV + } + #[doc = "Checks if the value of the field is `FSPIN`"] + #[inline(always)] + pub fn is_fspin(&self) -> bool { + **self == FSSEL_A::FSPIN + } +} +impl core::ops::Deref for FSSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSSEL` writer - Frame Sync Select"] +pub struct FSSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FSSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FSSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divided Serial Clock n is used as Frame Sync n source"] + #[inline(always)] + pub fn sckdiv(self) -> &'a mut W { + self.variant(FSSEL_A::SCKDIV) + } + #[doc = "FSn input pin is used as Frame Sync n source"] + #[inline(always)] + pub fn fspin(self) -> &'a mut W { + self.variant(FSSEL_A::FSPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FSINV` reader - Frame Sync Invert"] +pub struct FSINV_R(crate::FieldReader); +impl FSINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSINV` writer - Frame Sync Invert"] +pub struct FSINV_W<'a> { + w: &'a mut W, +} +impl<'a> FSINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Serial Clock Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SCKSEL_A { + #[doc = "0: Divided Master Clock n is used as Serial Clock n source"] + MCKDIV = 0, + #[doc = "1: SCKn input pin is used as Serial Clock n source"] + SCKPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SCKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SCKSEL` reader - Serial Clock Select"] +pub struct SCKSEL_R(crate::FieldReader); +impl SCKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SCKSEL_A { + match self.bits { + false => SCKSEL_A::MCKDIV, + true => SCKSEL_A::SCKPIN, + } + } + #[doc = "Checks if the value of the field is `MCKDIV`"] + #[inline(always)] + pub fn is_mckdiv(&self) -> bool { + **self == SCKSEL_A::MCKDIV + } + #[doc = "Checks if the value of the field is `SCKPIN`"] + #[inline(always)] + pub fn is_sckpin(&self) -> bool { + **self == SCKSEL_A::SCKPIN + } +} +impl core::ops::Deref for SCKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCKSEL` writer - Serial Clock Select"] +pub struct SCKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SCKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SCKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divided Master Clock n is used as Serial Clock n source"] + #[inline(always)] + pub fn mckdiv(self) -> &'a mut W { + self.variant(SCKSEL_A::MCKDIV) + } + #[doc = "SCKn input pin is used as Serial Clock n source"] + #[inline(always)] + pub fn sckpin(self) -> &'a mut W { + self.variant(SCKSEL_A::SCKPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Master Clock Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MCKSEL_A { + #[doc = "0: GCLK_I2S_n is used as Master Clock n source"] + GCLK = 0, + #[doc = "1: MCKn input pin is used as Master Clock n source"] + MCKPIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MCKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MCKSEL` reader - Master Clock Select"] +pub struct MCKSEL_R(crate::FieldReader); +impl MCKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MCKSEL_A { + match self.bits { + false => MCKSEL_A::GCLK, + true => MCKSEL_A::MCKPIN, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == MCKSEL_A::GCLK + } + #[doc = "Checks if the value of the field is `MCKPIN`"] + #[inline(always)] + pub fn is_mckpin(&self) -> bool { + **self == MCKSEL_A::MCKPIN + } +} +impl core::ops::Deref for MCKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKSEL` writer - Master Clock Select"] +pub struct MCKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> MCKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MCKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "GCLK_I2S_n is used as Master Clock n source"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(MCKSEL_A::GCLK) + } + #[doc = "MCKn input pin is used as Master Clock n source"] + #[inline(always)] + pub fn mckpin(self) -> &'a mut W { + self.variant(MCKSEL_A::MCKPIN) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCKEN` reader - Master Clock Enable"] +pub struct MCKEN_R(crate::FieldReader); +impl MCKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKEN` writer - Master Clock Enable"] +pub struct MCKEN_W<'a> { + w: &'a mut W, +} +impl<'a> MCKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCKDIV` reader - Master Clock Division Factor"] +pub struct MCKDIV_R(crate::FieldReader); +impl MCKDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MCKDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKDIV` writer - Master Clock Division Factor"] +pub struct MCKDIV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKDIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 19)) | ((value as u32 & 0x1f) << 19); + self.w + } +} +#[doc = "Field `MCKOUTDIV` reader - Master Clock Output Division Factor"] +pub struct MCKOUTDIV_R(crate::FieldReader); +impl MCKOUTDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MCKOUTDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKOUTDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKOUTDIV` writer - Master Clock Output Division Factor"] +pub struct MCKOUTDIV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKOUTDIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `FSOUTINV` reader - Frame Sync Output Invert"] +pub struct FSOUTINV_R(crate::FieldReader); +impl FSOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FSOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSOUTINV` writer - Frame Sync Output Invert"] +pub struct FSOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> FSOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `SCKOUTINV` reader - Serial Clock Output Invert"] +pub struct SCKOUTINV_R(crate::FieldReader); +impl SCKOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCKOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCKOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCKOUTINV` writer - Serial Clock Output Invert"] +pub struct SCKOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> SCKOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `MCKOUTINV` reader - Master Clock Output Invert"] +pub struct MCKOUTINV_R(crate::FieldReader); +impl MCKOUTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCKOUTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCKOUTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCKOUTINV` writer - Master Clock Output Invert"] +pub struct MCKOUTINV_W<'a> { + w: &'a mut W, +} +impl<'a> MCKOUTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Slot Size"] + #[inline(always)] + pub fn slotsize(&self) -> SLOTSIZE_R { + SLOTSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:4 - Number of Slots in Frame"] + #[inline(always)] + pub fn nbslots(&self) -> NBSLOTS_R { + NBSLOTS_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bits 5:6 - Frame Sync Width"] + #[inline(always)] + pub fn fswidth(&self) -> FSWIDTH_R { + FSWIDTH_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Data Delay from Frame Sync"] + #[inline(always)] + pub fn bitdelay(&self) -> BITDELAY_R { + BITDELAY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Frame Sync Select"] + #[inline(always)] + pub fn fssel(&self) -> FSSEL_R { + FSSEL_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 11 - Frame Sync Invert"] + #[inline(always)] + pub fn fsinv(&self) -> FSINV_R { + FSINV_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Serial Clock Select"] + #[inline(always)] + pub fn scksel(&self) -> SCKSEL_R { + SCKSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 16 - Master Clock Select"] + #[inline(always)] + pub fn mcksel(&self) -> MCKSEL_R { + MCKSEL_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 18 - Master Clock Enable"] + #[inline(always)] + pub fn mcken(&self) -> MCKEN_R { + MCKEN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bits 19:23 - Master Clock Division Factor"] + #[inline(always)] + pub fn mckdiv(&self) -> MCKDIV_R { + MCKDIV_R::new(((self.bits >> 19) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - Master Clock Output Division Factor"] + #[inline(always)] + pub fn mckoutdiv(&self) -> MCKOUTDIV_R { + MCKOUTDIV_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 29 - Frame Sync Output Invert"] + #[inline(always)] + pub fn fsoutinv(&self) -> FSOUTINV_R { + FSOUTINV_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Serial Clock Output Invert"] + #[inline(always)] + pub fn sckoutinv(&self) -> SCKOUTINV_R { + SCKOUTINV_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Master Clock Output Invert"] + #[inline(always)] + pub fn mckoutinv(&self) -> MCKOUTINV_R { + MCKOUTINV_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Slot Size"] + #[inline(always)] + pub fn slotsize(&mut self) -> SLOTSIZE_W { + SLOTSIZE_W { w: self } + } + #[doc = "Bits 2:4 - Number of Slots in Frame"] + #[inline(always)] + pub fn nbslots(&mut self) -> NBSLOTS_W { + NBSLOTS_W { w: self } + } + #[doc = "Bits 5:6 - Frame Sync Width"] + #[inline(always)] + pub fn fswidth(&mut self) -> FSWIDTH_W { + FSWIDTH_W { w: self } + } + #[doc = "Bit 7 - Data Delay from Frame Sync"] + #[inline(always)] + pub fn bitdelay(&mut self) -> BITDELAY_W { + BITDELAY_W { w: self } + } + #[doc = "Bit 8 - Frame Sync Select"] + #[inline(always)] + pub fn fssel(&mut self) -> FSSEL_W { + FSSEL_W { w: self } + } + #[doc = "Bit 11 - Frame Sync Invert"] + #[inline(always)] + pub fn fsinv(&mut self) -> FSINV_W { + FSINV_W { w: self } + } + #[doc = "Bit 12 - Serial Clock Select"] + #[inline(always)] + pub fn scksel(&mut self) -> SCKSEL_W { + SCKSEL_W { w: self } + } + #[doc = "Bit 16 - Master Clock Select"] + #[inline(always)] + pub fn mcksel(&mut self) -> MCKSEL_W { + MCKSEL_W { w: self } + } + #[doc = "Bit 18 - Master Clock Enable"] + #[inline(always)] + pub fn mcken(&mut self) -> MCKEN_W { + MCKEN_W { w: self } + } + #[doc = "Bits 19:23 - Master Clock Division Factor"] + #[inline(always)] + pub fn mckdiv(&mut self) -> MCKDIV_W { + MCKDIV_W { w: self } + } + #[doc = "Bits 24:28 - Master Clock Output Division Factor"] + #[inline(always)] + pub fn mckoutdiv(&mut self) -> MCKOUTDIV_W { + MCKOUTDIV_W { w: self } + } + #[doc = "Bit 29 - Frame Sync Output Invert"] + #[inline(always)] + pub fn fsoutinv(&mut self) -> FSOUTINV_W { + FSOUTINV_W { w: self } + } + #[doc = "Bit 30 - Serial Clock Output Invert"] + #[inline(always)] + pub fn sckoutinv(&mut self) -> SCKOUTINV_W { + SCKOUTINV_W { w: self } + } + #[doc = "Bit 31 - Master Clock Output Invert"] + #[inline(always)] + pub fn mckoutinv(&mut self) -> MCKOUTINV_W { + MCKOUTINV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Unit n Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkctrl](index.html) module"] +pub struct CLKCTRL_SPEC; +impl crate::RegisterSpec for CLKCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkctrl::R](R) reader structure"] +impl crate::Readable for CLKCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkctrl::W](W) writer structure"] +impl crate::Writable for CLKCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKCTRL[%s] +to value 0"] +impl crate::Resettable for CLKCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/i2s/ctrla.rs b/pac/atsamda1j/src/i2s/ctrla.rs new file mode 100644 index 00000000000..116902b0a11 --- /dev/null +++ b/pac/atsamda1j/src/i2s/ctrla.rs @@ -0,0 +1,348 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CKEN0` reader - Clock Unit 0 Enable"] +pub struct CKEN0_R(crate::FieldReader); +impl CKEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN0` writer - Clock Unit 0 Enable"] +pub struct CKEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CKEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CKEN1` reader - Clock Unit 1 Enable"] +pub struct CKEN1_R(crate::FieldReader); +impl CKEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN1` writer - Clock Unit 1 Enable"] +pub struct CKEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CKEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SEREN0` reader - Serializer 0 Enable"] +pub struct SEREN0_R(crate::FieldReader); +impl SEREN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN0` writer - Serializer 0 Enable"] +pub struct SEREN0_W<'a> { + w: &'a mut W, +} +impl<'a> SEREN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SEREN1` reader - Serializer 1 Enable"] +pub struct SEREN1_R(crate::FieldReader); +impl SEREN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN1` writer - Serializer 1 Enable"] +pub struct SEREN1_W<'a> { + w: &'a mut W, +} +impl<'a> SEREN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Unit 0 Enable"] + #[inline(always)] + pub fn cken0(&self) -> CKEN0_R { + CKEN0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Unit 1 Enable"] + #[inline(always)] + pub fn cken1(&self) -> CKEN1_R { + CKEN1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Serializer 0 Enable"] + #[inline(always)] + pub fn seren0(&self) -> SEREN0_R { + SEREN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Serializer 1 Enable"] + #[inline(always)] + pub fn seren1(&self) -> SEREN1_R { + SEREN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Clock Unit 0 Enable"] + #[inline(always)] + pub fn cken0(&mut self) -> CKEN0_W { + CKEN0_W { w: self } + } + #[doc = "Bit 3 - Clock Unit 1 Enable"] + #[inline(always)] + pub fn cken1(&mut self) -> CKEN1_W { + CKEN1_W { w: self } + } + #[doc = "Bit 4 - Serializer 0 Enable"] + #[inline(always)] + pub fn seren0(&mut self) -> SEREN0_W { + SEREN0_W { w: self } + } + #[doc = "Bit 5 - Serializer 1 Enable"] + #[inline(always)] + pub fn seren1(&mut self) -> SEREN1_W { + SEREN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/i2s/data.rs b/pac/atsamda1j/src/i2s/data.rs new file mode 100644 index 00000000000..6184a1e36a2 --- /dev/null +++ b/pac/atsamda1j/src/i2s/data.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DATA[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Sample Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Sample Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Sample Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Sample Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA[%s] +to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/i2s/intenclr.rs b/pac/atsamda1j/src/i2s/intenclr.rs new file mode 100644 index 00000000000..8bfa22bba98 --- /dev/null +++ b/pac/atsamda1j/src/i2s/intenclr.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/i2s/intenset.rs b/pac/atsamda1j/src/i2s/intenset.rs new file mode 100644 index 00000000000..45473048a4d --- /dev/null +++ b/pac/atsamda1j/src/i2s/intenset.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0 Interrupt Enable"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1 Interrupt Enable"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0 Interrupt Enable"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1 Interrupt Enable"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0 Interrupt Enable"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1 Interrupt Enable"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0 Interrupt Enable"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1 Interrupt Enable"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0 Interrupt Enable"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1 Interrupt Enable"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0 Interrupt Enable"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1 Interrupt Enable"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0 Interrupt Enable"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1 Interrupt Enable"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/i2s/intflag.rs b/pac/atsamda1j/src/i2s/intflag.rs new file mode 100644 index 00000000000..eaedff6ff40 --- /dev/null +++ b/pac/atsamda1j/src/i2s/intflag.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXRDY0` reader - Receive Ready 0"] +pub struct RXRDY0_R(crate::FieldReader); +impl RXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY0` writer - Receive Ready 0"] +pub struct RXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `RXRDY1` reader - Receive Ready 1"] +pub struct RXRDY1_R(crate::FieldReader); +impl RXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRDY1` writer - Receive Ready 1"] +pub struct RXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> RXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXOR0` reader - Receive Overrun 0"] +pub struct RXOR0_R(crate::FieldReader); +impl RXOR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR0` writer - Receive Overrun 0"] +pub struct RXOR0_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXOR1` reader - Receive Overrun 1"] +pub struct RXOR1_R(crate::FieldReader); +impl RXOR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOR1` writer - Receive Overrun 1"] +pub struct RXOR1_W<'a> { + w: &'a mut W, +} +impl<'a> RXOR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXRDY0` reader - Transmit Ready 0"] +pub struct TXRDY0_R(crate::FieldReader); +impl TXRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY0` writer - Transmit Ready 0"] +pub struct TXRDY0_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TXRDY1` reader - Transmit Ready 1"] +pub struct TXRDY1_R(crate::FieldReader); +impl TXRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXRDY1` writer - Transmit Ready 1"] +pub struct TXRDY1_W<'a> { + w: &'a mut W, +} +impl<'a> TXRDY1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUR0` reader - Transmit Underrun 0"] +pub struct TXUR0_R(crate::FieldReader); +impl TXUR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR0` writer - Transmit Underrun 0"] +pub struct TXUR0_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXUR1` reader - Transmit Underrun 1"] +pub struct TXUR1_R(crate::FieldReader); +impl TXUR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUR1` writer - Transmit Underrun 1"] +pub struct TXUR1_W<'a> { + w: &'a mut W, +} +impl<'a> TXUR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Receive Ready 0"] + #[inline(always)] + pub fn rxrdy0(&self) -> RXRDY0_R { + RXRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Receive Ready 1"] + #[inline(always)] + pub fn rxrdy1(&self) -> RXRDY1_R { + RXRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Overrun 0"] + #[inline(always)] + pub fn rxor0(&self) -> RXOR0_R { + RXOR0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Receive Overrun 1"] + #[inline(always)] + pub fn rxor1(&self) -> RXOR1_R { + RXOR1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmit Ready 0"] + #[inline(always)] + pub fn txrdy0(&self) -> TXRDY0_R { + TXRDY0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmit Ready 1"] + #[inline(always)] + pub fn txrdy1(&self) -> TXRDY1_R { + TXRDY1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmit Underrun 0"] + #[inline(always)] + pub fn txur0(&self) -> TXUR0_R { + TXUR0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmit Underrun 1"] + #[inline(always)] + pub fn txur1(&self) -> TXUR1_R { + TXUR1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive Ready 0"] + #[inline(always)] + pub fn rxrdy0(&mut self) -> RXRDY0_W { + RXRDY0_W { w: self } + } + #[doc = "Bit 1 - Receive Ready 1"] + #[inline(always)] + pub fn rxrdy1(&mut self) -> RXRDY1_W { + RXRDY1_W { w: self } + } + #[doc = "Bit 4 - Receive Overrun 0"] + #[inline(always)] + pub fn rxor0(&mut self) -> RXOR0_W { + RXOR0_W { w: self } + } + #[doc = "Bit 5 - Receive Overrun 1"] + #[inline(always)] + pub fn rxor1(&mut self) -> RXOR1_W { + RXOR1_W { w: self } + } + #[doc = "Bit 8 - Transmit Ready 0"] + #[inline(always)] + pub fn txrdy0(&mut self) -> TXRDY0_W { + TXRDY0_W { w: self } + } + #[doc = "Bit 9 - Transmit Ready 1"] + #[inline(always)] + pub fn txrdy1(&mut self) -> TXRDY1_W { + TXRDY1_W { w: self } + } + #[doc = "Bit 12 - Transmit Underrun 0"] + #[inline(always)] + pub fn txur0(&mut self) -> TXUR0_W { + TXUR0_W { w: self } + } + #[doc = "Bit 13 - Transmit Underrun 1"] + #[inline(always)] + pub fn txur1(&mut self) -> TXUR1_W { + TXUR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/i2s/serctrl.rs b/pac/atsamda1j/src/i2s/serctrl.rs new file mode 100644 index 00000000000..1c1ab945454 --- /dev/null +++ b/pac/atsamda1j/src/i2s/serctrl.rs @@ -0,0 +1,1622 @@ +#[doc = "Register `SERCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SERCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Serializer Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERMODE_A { + #[doc = "0: Receive"] + RX = 0, + #[doc = "1: Transmit"] + TX = 1, + #[doc = "2: Receive one PDM data on each serial clock edge"] + PDM2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERMODE` reader - Serializer Mode"] +pub struct SERMODE_R(crate::FieldReader); +impl SERMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERMODE_A::RX), + 1 => Some(SERMODE_A::TX), + 2 => Some(SERMODE_A::PDM2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + **self == SERMODE_A::RX + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + **self == SERMODE_A::TX + } + #[doc = "Checks if the value of the field is `PDM2`"] + #[inline(always)] + pub fn is_pdm2(&self) -> bool { + **self == SERMODE_A::PDM2 + } +} +impl core::ops::Deref for SERMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERMODE` writer - Serializer Mode"] +pub struct SERMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SERMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SERMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Receive"] + #[inline(always)] + pub fn rx(self) -> &'a mut W { + self.variant(SERMODE_A::RX) + } + #[doc = "Transmit"] + #[inline(always)] + pub fn tx(self) -> &'a mut W { + self.variant(SERMODE_A::TX) + } + #[doc = "Receive one PDM data on each serial clock edge"] + #[inline(always)] + pub fn pdm2(self) -> &'a mut W { + self.variant(SERMODE_A::PDM2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Line Default Line when Slot Disabled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXDEFAULT_A { + #[doc = "0: Output Default Value is 0"] + ZERO = 0, + #[doc = "1: Output Default Value is 1"] + ONE = 1, + #[doc = "3: Output Default Value is high impedance"] + HIZ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXDEFAULT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXDEFAULT` reader - Line Default Line when Slot Disabled"] +pub struct TXDEFAULT_R(crate::FieldReader); +impl TXDEFAULT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXDEFAULT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXDEFAULT_A::ZERO), + 1 => Some(TXDEFAULT_A::ONE), + 3 => Some(TXDEFAULT_A::HIZ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TXDEFAULT_A::ZERO + } + #[doc = "Checks if the value of the field is `ONE`"] + #[inline(always)] + pub fn is_one(&self) -> bool { + **self == TXDEFAULT_A::ONE + } + #[doc = "Checks if the value of the field is `HIZ`"] + #[inline(always)] + pub fn is_hiz(&self) -> bool { + **self == TXDEFAULT_A::HIZ + } +} +impl core::ops::Deref for TXDEFAULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXDEFAULT` writer - Line Default Line when Slot Disabled"] +pub struct TXDEFAULT_W<'a> { + w: &'a mut W, +} +impl<'a> TXDEFAULT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXDEFAULT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Output Default Value is 0"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TXDEFAULT_A::ZERO) + } + #[doc = "Output Default Value is 1"] + #[inline(always)] + pub fn one(self) -> &'a mut W { + self.variant(TXDEFAULT_A::ONE) + } + #[doc = "Output Default Value is high impedance"] + #[inline(always)] + pub fn hiz(self) -> &'a mut W { + self.variant(TXDEFAULT_A::HIZ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Transmit Data when Underrun\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TXSAME_A { + #[doc = "0: Zero data transmitted in case of underrun"] + ZERO = 0, + #[doc = "1: Last data transmitted in case of underrun"] + SAME = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TXSAME_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSAME` reader - Transmit Data when Underrun"] +pub struct TXSAME_R(crate::FieldReader); +impl TXSAME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSAME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TXSAME_A { + match self.bits { + false => TXSAME_A::ZERO, + true => TXSAME_A::SAME, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TXSAME_A::ZERO + } + #[doc = "Checks if the value of the field is `SAME`"] + #[inline(always)] + pub fn is_same(&self) -> bool { + **self == TXSAME_A::SAME + } +} +impl core::ops::Deref for TXSAME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSAME` writer - Transmit Data when Underrun"] +pub struct TXSAME_W<'a> { + w: &'a mut W, +} +impl<'a> TXSAME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXSAME_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Zero data transmitted in case of underrun"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TXSAME_A::ZERO) + } + #[doc = "Last data transmitted in case of underrun"] + #[inline(always)] + pub fn same(self) -> &'a mut W { + self.variant(TXSAME_A::SAME) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Clock Unit Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSEL_A { + #[doc = "0: Use Clock Unit 0"] + CLK0 = 0, + #[doc = "1: Use Clock Unit 1"] + CLK1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSEL` reader - Clock Unit Selection"] +pub struct CLKSEL_R(crate::FieldReader); +impl CLKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSEL_A { + match self.bits { + false => CLKSEL_A::CLK0, + true => CLKSEL_A::CLK1, + } + } + #[doc = "Checks if the value of the field is `CLK0`"] + #[inline(always)] + pub fn is_clk0(&self) -> bool { + **self == CLKSEL_A::CLK0 + } + #[doc = "Checks if the value of the field is `CLK1`"] + #[inline(always)] + pub fn is_clk1(&self) -> bool { + **self == CLKSEL_A::CLK1 + } +} +impl core::ops::Deref for CLKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSEL` writer - Clock Unit Selection"] +pub struct CLKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Use Clock Unit 0"] + #[inline(always)] + pub fn clk0(self) -> &'a mut W { + self.variant(CLKSEL_A::CLK0) + } + #[doc = "Use Clock Unit 1"] + #[inline(always)] + pub fn clk1(self) -> &'a mut W { + self.variant(CLKSEL_A::CLK1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Data Slot Formatting Adjust\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLOTADJ_A { + #[doc = "0: Data is right adjusted in slot"] + RIGHT = 0, + #[doc = "1: Data is left adjusted in slot"] + LEFT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLOTADJ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLOTADJ` reader - Data Slot Formatting Adjust"] +pub struct SLOTADJ_R(crate::FieldReader); +impl SLOTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTADJ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLOTADJ_A { + match self.bits { + false => SLOTADJ_A::RIGHT, + true => SLOTADJ_A::LEFT, + } + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + **self == SLOTADJ_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + **self == SLOTADJ_A::LEFT + } +} +impl core::ops::Deref for SLOTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTADJ` writer - Data Slot Formatting Adjust"] +pub struct SLOTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTADJ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLOTADJ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Data is right adjusted in slot"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(SLOTADJ_A::RIGHT) + } + #[doc = "Data is left adjusted in slot"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(SLOTADJ_A::LEFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Data Word Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DATASIZE_A { + #[doc = "0: 32 bits"] + _32 = 0, + #[doc = "1: 24 bits"] + _24 = 1, + #[doc = "2: 20 bits"] + _20 = 2, + #[doc = "3: 18 bits"] + _18 = 3, + #[doc = "4: 16 bits"] + _16 = 4, + #[doc = "5: 16 bits compact stereo"] + _16C = 5, + #[doc = "6: 8 bits"] + _8 = 6, + #[doc = "7: 8 bits compact stereo"] + _8C = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATASIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DATASIZE` reader - Data Word Size"] +pub struct DATASIZE_R(crate::FieldReader); +impl DATASIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATASIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DATASIZE_A { + match self.bits { + 0 => DATASIZE_A::_32, + 1 => DATASIZE_A::_24, + 2 => DATASIZE_A::_20, + 3 => DATASIZE_A::_18, + 4 => DATASIZE_A::_16, + 5 => DATASIZE_A::_16C, + 6 => DATASIZE_A::_8, + 7 => DATASIZE_A::_8C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == DATASIZE_A::_32 + } + #[doc = "Checks if the value of the field is `_24`"] + #[inline(always)] + pub fn is_24(&self) -> bool { + **self == DATASIZE_A::_24 + } + #[doc = "Checks if the value of the field is `_20`"] + #[inline(always)] + pub fn is_20(&self) -> bool { + **self == DATASIZE_A::_20 + } + #[doc = "Checks if the value of the field is `_18`"] + #[inline(always)] + pub fn is_18(&self) -> bool { + **self == DATASIZE_A::_18 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == DATASIZE_A::_16 + } + #[doc = "Checks if the value of the field is `_16C`"] + #[inline(always)] + pub fn is_16c(&self) -> bool { + **self == DATASIZE_A::_16C + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == DATASIZE_A::_8 + } + #[doc = "Checks if the value of the field is `_8C`"] + #[inline(always)] + pub fn is_8c(&self) -> bool { + **self == DATASIZE_A::_8C + } +} +impl core::ops::Deref for DATASIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATASIZE` writer - Data Word Size"] +pub struct DATASIZE_W<'a> { + w: &'a mut W, +} +impl<'a> DATASIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DATASIZE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(DATASIZE_A::_32) + } + #[doc = "24 bits"] + #[inline(always)] + pub fn _24(self) -> &'a mut W { + self.variant(DATASIZE_A::_24) + } + #[doc = "20 bits"] + #[inline(always)] + pub fn _20(self) -> &'a mut W { + self.variant(DATASIZE_A::_20) + } + #[doc = "18 bits"] + #[inline(always)] + pub fn _18(self) -> &'a mut W { + self.variant(DATASIZE_A::_18) + } + #[doc = "16 bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(DATASIZE_A::_16) + } + #[doc = "16 bits compact stereo"] + #[inline(always)] + pub fn _16c(self) -> &'a mut W { + self.variant(DATASIZE_A::_16C) + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(DATASIZE_A::_8) + } + #[doc = "8 bits compact stereo"] + #[inline(always)] + pub fn _8c(self) -> &'a mut W { + self.variant(DATASIZE_A::_8C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Data Word Formatting Adjust\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum WORDADJ_A { + #[doc = "0: Data is right adjusted in word"] + RIGHT = 0, + #[doc = "1: Data is left adjusted in word"] + LEFT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WORDADJ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WORDADJ` reader - Data Word Formatting Adjust"] +pub struct WORDADJ_R(crate::FieldReader); +impl WORDADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WORDADJ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WORDADJ_A { + match self.bits { + false => WORDADJ_A::RIGHT, + true => WORDADJ_A::LEFT, + } + } + #[doc = "Checks if the value of the field is `RIGHT`"] + #[inline(always)] + pub fn is_right(&self) -> bool { + **self == WORDADJ_A::RIGHT + } + #[doc = "Checks if the value of the field is `LEFT`"] + #[inline(always)] + pub fn is_left(&self) -> bool { + **self == WORDADJ_A::LEFT + } +} +impl core::ops::Deref for WORDADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WORDADJ` writer - Data Word Formatting Adjust"] +pub struct WORDADJ_W<'a> { + w: &'a mut W, +} +impl<'a> WORDADJ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WORDADJ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Data is right adjusted in word"] + #[inline(always)] + pub fn right(self) -> &'a mut W { + self.variant(WORDADJ_A::RIGHT) + } + #[doc = "Data is left adjusted in word"] + #[inline(always)] + pub fn left(self) -> &'a mut W { + self.variant(WORDADJ_A::LEFT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Data Formatting Bit Extension\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EXTEND_A { + #[doc = "0: Extend with zeroes"] + ZERO = 0, + #[doc = "1: Extend with ones"] + ONE = 1, + #[doc = "2: Extend with Most Significant Bit"] + MSBIT = 2, + #[doc = "3: Extend with Least Significant Bit"] + LSBIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EXTEND_A) -> Self { + variant as _ + } +} +#[doc = "Field `EXTEND` reader - Data Formatting Bit Extension"] +pub struct EXTEND_R(crate::FieldReader); +impl EXTEND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EXTEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EXTEND_A { + match self.bits { + 0 => EXTEND_A::ZERO, + 1 => EXTEND_A::ONE, + 2 => EXTEND_A::MSBIT, + 3 => EXTEND_A::LSBIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == EXTEND_A::ZERO + } + #[doc = "Checks if the value of the field is `ONE`"] + #[inline(always)] + pub fn is_one(&self) -> bool { + **self == EXTEND_A::ONE + } + #[doc = "Checks if the value of the field is `MSBIT`"] + #[inline(always)] + pub fn is_msbit(&self) -> bool { + **self == EXTEND_A::MSBIT + } + #[doc = "Checks if the value of the field is `LSBIT`"] + #[inline(always)] + pub fn is_lsbit(&self) -> bool { + **self == EXTEND_A::LSBIT + } +} +impl core::ops::Deref for EXTEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTEND` writer - Data Formatting Bit Extension"] +pub struct EXTEND_W<'a> { + w: &'a mut W, +} +impl<'a> EXTEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EXTEND_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Extend with zeroes"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(EXTEND_A::ZERO) + } + #[doc = "Extend with ones"] + #[inline(always)] + pub fn one(self) -> &'a mut W { + self.variant(EXTEND_A::ONE) + } + #[doc = "Extend with Most Significant Bit"] + #[inline(always)] + pub fn msbit(self) -> &'a mut W { + self.variant(EXTEND_A::MSBIT) + } + #[doc = "Extend with Least Significant Bit"] + #[inline(always)] + pub fn lsbit(self) -> &'a mut W { + self.variant(EXTEND_A::LSBIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Data Formatting Bit Reverse\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum BITREV_A { + #[doc = "0: Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)"] + MSBIT = 0, + #[doc = "1: Transfer Data Least Significant Bit (LSB) first"] + LSBIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BITREV_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BITREV` reader - Data Formatting Bit Reverse"] +pub struct BITREV_R(crate::FieldReader); +impl BITREV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BITREV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BITREV_A { + match self.bits { + false => BITREV_A::MSBIT, + true => BITREV_A::LSBIT, + } + } + #[doc = "Checks if the value of the field is `MSBIT`"] + #[inline(always)] + pub fn is_msbit(&self) -> bool { + **self == BITREV_A::MSBIT + } + #[doc = "Checks if the value of the field is `LSBIT`"] + #[inline(always)] + pub fn is_lsbit(&self) -> bool { + **self == BITREV_A::LSBIT + } +} +impl core::ops::Deref for BITREV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITREV` writer - Data Formatting Bit Reverse"] +pub struct BITREV_W<'a> { + w: &'a mut W, +} +impl<'a> BITREV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BITREV_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)"] + #[inline(always)] + pub fn msbit(self) -> &'a mut W { + self.variant(BITREV_A::MSBIT) + } + #[doc = "Transfer Data Least Significant Bit (LSB) first"] + #[inline(always)] + pub fn lsbit(self) -> &'a mut W { + self.variant(BITREV_A::LSBIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `SLOTDIS0` reader - Slot 0 Disabled for this Serializer"] +pub struct SLOTDIS0_R(crate::FieldReader); +impl SLOTDIS0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS0` writer - Slot 0 Disabled for this Serializer"] +pub struct SLOTDIS0_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `SLOTDIS1` reader - Slot 1 Disabled for this Serializer"] +pub struct SLOTDIS1_R(crate::FieldReader); +impl SLOTDIS1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS1` writer - Slot 1 Disabled for this Serializer"] +pub struct SLOTDIS1_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `SLOTDIS2` reader - Slot 2 Disabled for this Serializer"] +pub struct SLOTDIS2_R(crate::FieldReader); +impl SLOTDIS2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS2` writer - Slot 2 Disabled for this Serializer"] +pub struct SLOTDIS2_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SLOTDIS3` reader - Slot 3 Disabled for this Serializer"] +pub struct SLOTDIS3_R(crate::FieldReader); +impl SLOTDIS3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS3` writer - Slot 3 Disabled for this Serializer"] +pub struct SLOTDIS3_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SLOTDIS4` reader - Slot 4 Disabled for this Serializer"] +pub struct SLOTDIS4_R(crate::FieldReader); +impl SLOTDIS4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS4` writer - Slot 4 Disabled for this Serializer"] +pub struct SLOTDIS4_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `SLOTDIS5` reader - Slot 5 Disabled for this Serializer"] +pub struct SLOTDIS5_R(crate::FieldReader); +impl SLOTDIS5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS5` writer - Slot 5 Disabled for this Serializer"] +pub struct SLOTDIS5_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `SLOTDIS6` reader - Slot 6 Disabled for this Serializer"] +pub struct SLOTDIS6_R(crate::FieldReader); +impl SLOTDIS6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS6` writer - Slot 6 Disabled for this Serializer"] +pub struct SLOTDIS6_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SLOTDIS7` reader - Slot 7 Disabled for this Serializer"] +pub struct SLOTDIS7_R(crate::FieldReader); +impl SLOTDIS7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLOTDIS7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOTDIS7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOTDIS7` writer - Slot 7 Disabled for this Serializer"] +pub struct SLOTDIS7_W<'a> { + w: &'a mut W, +} +impl<'a> SLOTDIS7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Mono Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MONO_A { + #[doc = "0: Normal mode"] + STEREO = 0, + #[doc = "1: Left channel data is duplicated to right channel"] + MONO = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MONO_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MONO` reader - Mono Mode"] +pub struct MONO_R(crate::FieldReader); +impl MONO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MONO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MONO_A { + match self.bits { + false => MONO_A::STEREO, + true => MONO_A::MONO, + } + } + #[doc = "Checks if the value of the field is `STEREO`"] + #[inline(always)] + pub fn is_stereo(&self) -> bool { + **self == MONO_A::STEREO + } + #[doc = "Checks if the value of the field is `MONO`"] + #[inline(always)] + pub fn is_mono(&self) -> bool { + **self == MONO_A::MONO + } +} +impl core::ops::Deref for MONO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONO` writer - Mono Mode"] +pub struct MONO_W<'a> { + w: &'a mut W, +} +impl<'a> MONO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MONO_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Normal mode"] + #[inline(always)] + pub fn stereo(self) -> &'a mut W { + self.variant(MONO_A::STEREO) + } + #[doc = "Left channel data is duplicated to right channel"] + #[inline(always)] + pub fn mono(self) -> &'a mut W { + self.variant(MONO_A::MONO) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Single or Multiple DMA Channels\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DMA_A { + #[doc = "0: Single DMA channel"] + SINGLE = 0, + #[doc = "1: One DMA channel per data channel"] + MULTIPLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA` reader - Single or Multiple DMA Channels"] +pub struct DMA_R(crate::FieldReader); +impl DMA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_A { + match self.bits { + false => DMA_A::SINGLE, + true => DMA_A::MULTIPLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == DMA_A::SINGLE + } + #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[inline(always)] + pub fn is_multiple(&self) -> bool { + **self == DMA_A::MULTIPLE + } +} +impl core::ops::Deref for DMA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMA` writer - Single or Multiple DMA Channels"] +pub struct DMA_W<'a> { + w: &'a mut W, +} +impl<'a> DMA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DMA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Single DMA channel"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(DMA_A::SINGLE) + } + #[doc = "One DMA channel per data channel"] + #[inline(always)] + pub fn multiple(self) -> &'a mut W { + self.variant(DMA_A::MULTIPLE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `RXLOOP` reader - Loop-back Test Mode"] +pub struct RXLOOP_R(crate::FieldReader); +impl RXLOOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXLOOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXLOOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXLOOP` writer - Loop-back Test Mode"] +pub struct RXLOOP_W<'a> { + w: &'a mut W, +} +impl<'a> RXLOOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Serializer Mode"] + #[inline(always)] + pub fn sermode(&self) -> SERMODE_R { + SERMODE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Line Default Line when Slot Disabled"] + #[inline(always)] + pub fn txdefault(&self) -> TXDEFAULT_R { + TXDEFAULT_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - Transmit Data when Underrun"] + #[inline(always)] + pub fn txsame(&self) -> TXSAME_R { + TXSAME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Clock Unit Selection"] + #[inline(always)] + pub fn clksel(&self) -> CLKSEL_R { + CLKSEL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Data Slot Formatting Adjust"] + #[inline(always)] + pub fn slotadj(&self) -> SLOTADJ_R { + SLOTADJ_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Data Word Size"] + #[inline(always)] + pub fn datasize(&self) -> DATASIZE_R { + DATASIZE_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Data Word Formatting Adjust"] + #[inline(always)] + pub fn wordadj(&self) -> WORDADJ_R { + WORDADJ_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:14 - Data Formatting Bit Extension"] + #[inline(always)] + pub fn extend(&self) -> EXTEND_R { + EXTEND_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Data Formatting Bit Reverse"] + #[inline(always)] + pub fn bitrev(&self) -> BITREV_R { + BITREV_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Slot 0 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis0(&self) -> SLOTDIS0_R { + SLOTDIS0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Slot 1 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis1(&self) -> SLOTDIS1_R { + SLOTDIS1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Slot 2 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis2(&self) -> SLOTDIS2_R { + SLOTDIS2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Slot 3 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis3(&self) -> SLOTDIS3_R { + SLOTDIS3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Slot 4 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis4(&self) -> SLOTDIS4_R { + SLOTDIS4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Slot 5 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis5(&self) -> SLOTDIS5_R { + SLOTDIS5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Slot 6 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis6(&self) -> SLOTDIS6_R { + SLOTDIS6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slot 7 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis7(&self) -> SLOTDIS7_R { + SLOTDIS7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Mono Mode"] + #[inline(always)] + pub fn mono(&self) -> MONO_R { + MONO_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Single or Multiple DMA Channels"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Loop-back Test Mode"] + #[inline(always)] + pub fn rxloop(&self) -> RXLOOP_R { + RXLOOP_R::new(((self.bits >> 26) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Serializer Mode"] + #[inline(always)] + pub fn sermode(&mut self) -> SERMODE_W { + SERMODE_W { w: self } + } + #[doc = "Bits 2:3 - Line Default Line when Slot Disabled"] + #[inline(always)] + pub fn txdefault(&mut self) -> TXDEFAULT_W { + TXDEFAULT_W { w: self } + } + #[doc = "Bit 4 - Transmit Data when Underrun"] + #[inline(always)] + pub fn txsame(&mut self) -> TXSAME_W { + TXSAME_W { w: self } + } + #[doc = "Bit 5 - Clock Unit Selection"] + #[inline(always)] + pub fn clksel(&mut self) -> CLKSEL_W { + CLKSEL_W { w: self } + } + #[doc = "Bit 7 - Data Slot Formatting Adjust"] + #[inline(always)] + pub fn slotadj(&mut self) -> SLOTADJ_W { + SLOTADJ_W { w: self } + } + #[doc = "Bits 8:10 - Data Word Size"] + #[inline(always)] + pub fn datasize(&mut self) -> DATASIZE_W { + DATASIZE_W { w: self } + } + #[doc = "Bit 12 - Data Word Formatting Adjust"] + #[inline(always)] + pub fn wordadj(&mut self) -> WORDADJ_W { + WORDADJ_W { w: self } + } + #[doc = "Bits 13:14 - Data Formatting Bit Extension"] + #[inline(always)] + pub fn extend(&mut self) -> EXTEND_W { + EXTEND_W { w: self } + } + #[doc = "Bit 15 - Data Formatting Bit Reverse"] + #[inline(always)] + pub fn bitrev(&mut self) -> BITREV_W { + BITREV_W { w: self } + } + #[doc = "Bit 16 - Slot 0 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis0(&mut self) -> SLOTDIS0_W { + SLOTDIS0_W { w: self } + } + #[doc = "Bit 17 - Slot 1 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis1(&mut self) -> SLOTDIS1_W { + SLOTDIS1_W { w: self } + } + #[doc = "Bit 18 - Slot 2 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis2(&mut self) -> SLOTDIS2_W { + SLOTDIS2_W { w: self } + } + #[doc = "Bit 19 - Slot 3 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis3(&mut self) -> SLOTDIS3_W { + SLOTDIS3_W { w: self } + } + #[doc = "Bit 20 - Slot 4 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis4(&mut self) -> SLOTDIS4_W { + SLOTDIS4_W { w: self } + } + #[doc = "Bit 21 - Slot 5 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis5(&mut self) -> SLOTDIS5_W { + SLOTDIS5_W { w: self } + } + #[doc = "Bit 22 - Slot 6 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis6(&mut self) -> SLOTDIS6_W { + SLOTDIS6_W { w: self } + } + #[doc = "Bit 23 - Slot 7 Disabled for this Serializer"] + #[inline(always)] + pub fn slotdis7(&mut self) -> SLOTDIS7_W { + SLOTDIS7_W { w: self } + } + #[doc = "Bit 24 - Mono Mode"] + #[inline(always)] + pub fn mono(&mut self) -> MONO_W { + MONO_W { w: self } + } + #[doc = "Bit 25 - Single or Multiple DMA Channels"] + #[inline(always)] + pub fn dma(&mut self) -> DMA_W { + DMA_W { w: self } + } + #[doc = "Bit 26 - Loop-back Test Mode"] + #[inline(always)] + pub fn rxloop(&mut self) -> RXLOOP_W { + RXLOOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Serializer n Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [serctrl](index.html) module"] +pub struct SERCTRL_SPEC; +impl crate::RegisterSpec for SERCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [serctrl::R](R) reader structure"] +impl crate::Readable for SERCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [serctrl::W](W) writer structure"] +impl crate::Writable for SERCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SERCTRL[%s] +to value 0"] +impl crate::Resettable for SERCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/i2s/syncbusy.rs b/pac/atsamda1j/src/i2s/syncbusy.rs new file mode 100644 index 00000000000..46ae5a0c282 --- /dev/null +++ b/pac/atsamda1j/src/i2s/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Status"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN0` reader - Clock Unit 0 Enable Synchronization Status"] +pub struct CKEN0_R(crate::FieldReader); +impl CKEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKEN1` reader - Clock Unit 1 Enable Synchronization Status"] +pub struct CKEN1_R(crate::FieldReader); +impl CKEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN0` reader - Serializer 0 Enable Synchronization Status"] +pub struct SEREN0_R(crate::FieldReader); +impl SEREN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEREN1` reader - Serializer 1 Enable Synchronization Status"] +pub struct SEREN1_R(crate::FieldReader); +impl SEREN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEREN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEREN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA0` reader - Data 0 Synchronization Status"] +pub struct DATA0_R(crate::FieldReader); +impl DATA0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA1` reader - Data 1 Synchronization Status"] +pub struct DATA1_R(crate::FieldReader); +impl DATA1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Status"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Unit 0 Enable Synchronization Status"] + #[inline(always)] + pub fn cken0(&self) -> CKEN0_R { + CKEN0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Unit 1 Enable Synchronization Status"] + #[inline(always)] + pub fn cken1(&self) -> CKEN1_R { + CKEN1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Serializer 0 Enable Synchronization Status"] + #[inline(always)] + pub fn seren0(&self) -> SEREN0_R { + SEREN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Serializer 1 Enable Synchronization Status"] + #[inline(always)] + pub fn seren1(&self) -> SEREN1_R { + SEREN1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Data 0 Synchronization Status"] + #[inline(always)] + pub fn data0(&self) -> DATA0_R { + DATA0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Data 1 Synchronization Status"] + #[inline(always)] + pub fn data1(&self) -> DATA1_R { + DATA1_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/lib.rs b/pac/atsamda1j/src/lib.rs new file mode 100644 index 00000000000..b0b8a06d2c0 --- /dev/null +++ b/pac/atsamda1j/src/lib.rs @@ -0,0 +1,1452 @@ +#![doc = "Peripheral access API for ATSAMDA1J microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn PM(); + fn SYSCTRL(); + fn WDT(); + fn RTC(); + fn EIC(); + fn NVMCTRL(); + fn DMAC(); + fn USB(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn SERCOM4(); + fn SERCOM5(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC3(); + fn TC4(); + fn TC5(); + fn TC6(); + fn TC7(); + fn ADC(); + fn AC(); + fn DAC(); + fn PTC(); + fn I2S(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 28] = [ + Vector { _handler: PM }, + Vector { _handler: SYSCTRL }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: USB }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _handler: SERCOM4 }, + Vector { _handler: SERCOM5 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: TC5 }, + Vector { _handler: TC6 }, + Vector { _handler: TC7 }, + Vector { _handler: ADC }, + Vector { _handler: AC }, + Vector { _handler: DAC }, + Vector { _handler: PTC }, + Vector { _handler: I2S }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - PM"] + PM = 0, + #[doc = "1 - SYSCTRL"] + SYSCTRL = 1, + #[doc = "2 - WDT"] + WDT = 2, + #[doc = "3 - RTC"] + RTC = 3, + #[doc = "4 - EIC"] + EIC = 4, + #[doc = "5 - NVMCTRL"] + NVMCTRL = 5, + #[doc = "6 - DMAC"] + DMAC = 6, + #[doc = "7 - USB"] + USB = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "13 - SERCOM4"] + SERCOM4 = 13, + #[doc = "14 - SERCOM5"] + SERCOM5 = 14, + #[doc = "15 - TCC0"] + TCC0 = 15, + #[doc = "16 - TCC1"] + TCC1 = 16, + #[doc = "17 - TCC2"] + TCC2 = 17, + #[doc = "18 - TC3"] + TC3 = 18, + #[doc = "19 - TC4"] + TC4 = 19, + #[doc = "20 - TC5"] + TC5 = 20, + #[doc = "21 - TC6"] + TC6 = 21, + #[doc = "22 - TC7"] + TC7 = 22, + #[doc = "23 - ADC"] + ADC = 23, + #[doc = "24 - AC"] + AC = 24, + #[doc = "25 - DAC"] + DAC = 25, + #[doc = "26 - PTC"] + PTC = 26, + #[doc = "27 - I2S"] + I2S = 27, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc; +#[doc = "Digital Analog Converter"] +pub struct DAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC {} +impl DAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC { + type Target = dac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC").finish() + } +} +#[doc = "Digital Analog Converter"] +pub mod dac; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct SBMATRIX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SBMATRIX {} +impl SBMATRIX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sbmatrix::RegisterBlock = 0x4100_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sbmatrix::RegisterBlock { + Self::PTR + } +} +impl Deref for SBMATRIX { + type Target = sbmatrix::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SBMATRIX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SBMATRIX").finish() + } +} +#[doc = "HSB Matrix"] +pub mod sbmatrix; +#[doc = "Inter-IC Sound Interface"] +pub struct I2S { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S {} +impl I2S { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s::RegisterBlock { + Self::PTR + } +} +impl Deref for I2S { + type Target = i2s::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S").finish() + } +} +#[doc = "Inter-IC Sound Interface"] +pub mod i2s; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC0 {} +impl PAC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC0 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC0").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac0; +#[doc = "Peripheral Access Controller"] +pub struct PAC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC1 {} +impl PAC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC1 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC1").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub use pac0 as pac1; +#[doc = "Peripheral Access Controller"] +pub struct PAC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC2 {} +impl PAC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac0::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac0::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC2 { + type Target = pac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC2").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub use pac0 as pac2; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Serial Communication Interface"] +pub struct SERCOM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM4 {} +impl SERCOM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM4 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM4").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom4; +#[doc = "Serial Communication Interface"] +pub struct SERCOM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM5 {} +impl SERCOM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM5 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM5").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom5; +#[doc = "System Control"] +pub struct SYSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCTRL {} +impl SYSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysctrl::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSCTRL { + type Target = sysctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSCTRL").finish() + } +} +#[doc = "System Control"] +pub mod sysctrl; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc4; +#[doc = "Basic Timer Counter"] +pub struct TC5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC5 {} +impl TC5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC5 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC5").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc5; +#[doc = "Basic Timer Counter"] +pub struct TC6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC6 {} +impl TC6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC6 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC6").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc6; +#[doc = "Basic Timer Counter"] +pub struct TC7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC7 {} +impl TC7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc3::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc3::RegisterBlock { + Self::PTR + } +} +impl Deref for TC7 { + type Target = tc3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC7").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc3 as tc7; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Universal Serial Bus"] +pub struct USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB {} +impl USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb::RegisterBlock = 0x4100_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb::RegisterBlock { + Self::PTR + } +} +impl Deref for USB { + type Target = usb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB").finish() + } +} +#[doc = "Universal Serial Bus"] +pub mod usb; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "DAC"] + pub DAC: DAC, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "SBMATRIX"] + pub SBMATRIX: SBMATRIX, + #[doc = "I2S"] + pub I2S: I2S, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "PAC0"] + pub PAC0: PAC0, + #[doc = "PAC1"] + pub PAC1: PAC1, + #[doc = "PAC2"] + pub PAC2: PAC2, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SERCOM4"] + pub SERCOM4: SERCOM4, + #[doc = "SERCOM5"] + pub SERCOM5: SERCOM5, + #[doc = "SYSCTRL"] + pub SYSCTRL: SYSCTRL, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TC5"] + pub TC5: TC5, + #[doc = "TC6"] + pub TC6: TC6, + #[doc = "TC7"] + pub TC7: TC7, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "USB"] + pub USB: USB, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC: ADC { + _marker: PhantomData, + }, + DAC: DAC { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + SBMATRIX: SBMATRIX { + _marker: PhantomData, + }, + I2S: I2S { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + PAC0: PAC0 { + _marker: PhantomData, + }, + PAC1: PAC1 { + _marker: PhantomData, + }, + PAC2: PAC2 { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SERCOM4: SERCOM4 { + _marker: PhantomData, + }, + SERCOM5: SERCOM5 { + _marker: PhantomData, + }, + SYSCTRL: SYSCTRL { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TC5: TC5 { + _marker: PhantomData, + }, + TC6: TC6 { + _marker: PhantomData, + }, + TC7: TC7 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + USB: USB { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamda1j/src/mtb.rs b/pac/atsamda1j/src/mtb.rs new file mode 100644 index 00000000000..45d81bbf944 --- /dev/null +++ b/pac/atsamda1j/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - CoreSight"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - CoreSight"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - CoreSight"] + pub pid6: crate::Reg, + #[doc = "0xfdc - CoreSight"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - CoreSight"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - CoreSight"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - CoreSight"] + pub pid2: crate::Reg, + #[doc = "0xfec - CoreSight"] + pub pid3: crate::Reg, + #[doc = "0xff0 - CoreSight"] + pub cid0: crate::Reg, + #[doc = "0xff4 - CoreSight"] + pub cid1: crate::Reg, + #[doc = "0xff8 - CoreSight"] + pub cid2: crate::Reg, + #[doc = "0xffc - CoreSight"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "CoreSight"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "CoreSight"] +pub mod cid3; diff --git a/pac/atsamda1j/src/mtb/authstatus.rs b/pac/atsamda1j/src/mtb/authstatus.rs new file mode 100644 index 00000000000..6fe441e0554 --- /dev/null +++ b/pac/atsamda1j/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/base.rs b/pac/atsamda1j/src/mtb/base.rs new file mode 100644 index 00000000000..f59b5a97a39 --- /dev/null +++ b/pac/atsamda1j/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/cid0.rs b/pac/atsamda1j/src/mtb/cid0.rs new file mode 100644 index 00000000000..c4b0c0a2f5e --- /dev/null +++ b/pac/atsamda1j/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/cid1.rs b/pac/atsamda1j/src/mtb/cid1.rs new file mode 100644 index 00000000000..628785fae59 --- /dev/null +++ b/pac/atsamda1j/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/cid2.rs b/pac/atsamda1j/src/mtb/cid2.rs new file mode 100644 index 00000000000..cf5be1dab2f --- /dev/null +++ b/pac/atsamda1j/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/cid3.rs b/pac/atsamda1j/src/mtb/cid3.rs new file mode 100644 index 00000000000..f8d299b02a6 --- /dev/null +++ b/pac/atsamda1j/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/claimclr.rs b/pac/atsamda1j/src/mtb/claimclr.rs new file mode 100644 index 00000000000..7d0fa5d487b --- /dev/null +++ b/pac/atsamda1j/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/claimset.rs b/pac/atsamda1j/src/mtb/claimset.rs new file mode 100644 index 00000000000..d5e8ffaa484 --- /dev/null +++ b/pac/atsamda1j/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/devarch.rs b/pac/atsamda1j/src/mtb/devarch.rs new file mode 100644 index 00000000000..b79480753d5 --- /dev/null +++ b/pac/atsamda1j/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/devid.rs b/pac/atsamda1j/src/mtb/devid.rs new file mode 100644 index 00000000000..21c15d95203 --- /dev/null +++ b/pac/atsamda1j/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/devtype.rs b/pac/atsamda1j/src/mtb/devtype.rs new file mode 100644 index 00000000000..c00d66b98a2 --- /dev/null +++ b/pac/atsamda1j/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/flow.rs b/pac/atsamda1j/src/mtb/flow.rs new file mode 100644 index 00000000000..1b94efdb89b --- /dev/null +++ b/pac/atsamda1j/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/itctrl.rs b/pac/atsamda1j/src/mtb/itctrl.rs new file mode 100644 index 00000000000..a48364e0b06 --- /dev/null +++ b/pac/atsamda1j/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/lockaccess.rs b/pac/atsamda1j/src/mtb/lockaccess.rs new file mode 100644 index 00000000000..0400690bead --- /dev/null +++ b/pac/atsamda1j/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/lockstatus.rs b/pac/atsamda1j/src/mtb/lockstatus.rs new file mode 100644 index 00000000000..0c68410c694 --- /dev/null +++ b/pac/atsamda1j/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/master.rs b/pac/atsamda1j/src/mtb/master.rs new file mode 100644 index 00000000000..0190ca1ce90 --- /dev/null +++ b/pac/atsamda1j/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid0.rs b/pac/atsamda1j/src/mtb/pid0.rs new file mode 100644 index 00000000000..a4daa474849 --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid1.rs b/pac/atsamda1j/src/mtb/pid1.rs new file mode 100644 index 00000000000..37353582c84 --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid2.rs b/pac/atsamda1j/src/mtb/pid2.rs new file mode 100644 index 00000000000..c4e6a4b9c2a --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid3.rs b/pac/atsamda1j/src/mtb/pid3.rs new file mode 100644 index 00000000000..be0caeaeb51 --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid4.rs b/pac/atsamda1j/src/mtb/pid4.rs new file mode 100644 index 00000000000..83e65c1f64f --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid5.rs b/pac/atsamda1j/src/mtb/pid5.rs new file mode 100644 index 00000000000..eeffcc6e22a --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid6.rs b/pac/atsamda1j/src/mtb/pid6.rs new file mode 100644 index 00000000000..c3a4bdcb875 --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/pid7.rs b/pac/atsamda1j/src/mtb/pid7.rs new file mode 100644 index 00000000000..c47e91f7717 --- /dev/null +++ b/pac/atsamda1j/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/mtb/position.rs b/pac/atsamda1j/src/mtb/position.rs new file mode 100644 index 00000000000..4bab0425b14 --- /dev/null +++ b/pac/atsamda1j/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl.rs b/pac/atsamda1j/src/nvmctrl.rs new file mode 100644 index 00000000000..0c4b2717337 --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl.rs @@ -0,0 +1,63 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; diff --git a/pac/atsamda1j/src/nvmctrl/addr.rs b/pac/atsamda1j/src/nvmctrl/addr.rs new file mode 100644 index 00000000000..74ed27736da --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/ctrla.rs b/pac/atsamda1j/src/nvmctrl/ctrla.rs new file mode 100644 index 00000000000..89f175771e4 --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/ctrlb.rs b/pac/atsamda1j/src/nvmctrl/ctrlb.rs new file mode 100644 index 00000000000..169445752da --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/ctrlb.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/intenclr.rs b/pac/atsamda1j/src/nvmctrl/intenclr.rs new file mode 100644 index 00000000000..6e7db4b52c9 --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/intenset.rs b/pac/atsamda1j/src/nvmctrl/intenset.rs new file mode 100644 index 00000000000..ba8698e86c3 --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/intflag.rs b/pac/atsamda1j/src/nvmctrl/intflag.rs new file mode 100644 index 00000000000..1b30cdddf25 --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/lock.rs b/pac/atsamda1j/src/nvmctrl/lock.rs new file mode 100644 index 00000000000..dbcf37a8107 --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/param.rs b/pac/atsamda1j/src/nvmctrl/param.rs new file mode 100644 index 00000000000..d9197cf16de --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/nvmctrl/status.rs b/pac/atsamda1j/src/nvmctrl/status.rs new file mode 100644 index 00000000000..ce849015560 --- /dev/null +++ b/pac/atsamda1j/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pac0.rs b/pac/atsamda1j/src/pac0.rs new file mode 100644 index 00000000000..e6ae6be9ca4 --- /dev/null +++ b/pac/atsamda1j/src/pac0.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write Protection Clear"] + pub wpclr: crate::Reg, + #[doc = "0x04 - Write Protection Set"] + pub wpset: crate::Reg, +} +#[doc = "WPCLR register accessor: an alias for `Reg`"] +pub type WPCLR = crate::Reg; +#[doc = "Write Protection Clear"] +pub mod wpclr; +#[doc = "WPSET register accessor: an alias for `Reg`"] +pub type WPSET = crate::Reg; +#[doc = "Write Protection Set"] +pub mod wpset; diff --git a/pac/atsamda1j/src/pac0/wpclr.rs b/pac/atsamda1j/src/pac0/wpclr.rs new file mode 100644 index 00000000000..e6bb7309f42 --- /dev/null +++ b/pac/atsamda1j/src/pac0/wpclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WPCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WPCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WP` reader - Write Protection Clear"] +pub struct WP_R(crate::FieldReader); +impl WP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WP` writer - Write Protection Clear"] +pub struct WP_W<'a> { + w: &'a mut W, +} +impl<'a> WP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff_ffff << 1)) | ((value as u32 & 0x7fff_ffff) << 1); + self.w + } +} +impl R { + #[doc = "Bits 1:31 - Write Protection Clear"] + #[inline(always)] + pub fn wp(&self) -> WP_R { + WP_R::new(((self.bits >> 1) & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 1:31 - Write Protection Clear"] + #[inline(always)] + pub fn wp(&mut self) -> WP_W { + WP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Protection Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpclr](index.html) module"] +pub struct WPCLR_SPEC; +impl crate::RegisterSpec for WPCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wpclr::R](R) reader structure"] +impl crate::Readable for WPCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wpclr::W](W) writer structure"] +impl crate::Writable for WPCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WPCLR to value 0"] +impl crate::Resettable for WPCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pac0/wpset.rs b/pac/atsamda1j/src/pac0/wpset.rs new file mode 100644 index 00000000000..5a85aae2aad --- /dev/null +++ b/pac/atsamda1j/src/pac0/wpset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WPSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WPSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WP` reader - Write Protection Set"] +pub struct WP_R(crate::FieldReader); +impl WP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WP` writer - Write Protection Set"] +pub struct WP_W<'a> { + w: &'a mut W, +} +impl<'a> WP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff_ffff << 1)) | ((value as u32 & 0x7fff_ffff) << 1); + self.w + } +} +impl R { + #[doc = "Bits 1:31 - Write Protection Set"] + #[inline(always)] + pub fn wp(&self) -> WP_R { + WP_R::new(((self.bits >> 1) & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 1:31 - Write Protection Set"] + #[inline(always)] + pub fn wp(&mut self) -> WP_W { + WP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Protection Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpset](index.html) module"] +pub struct WPSET_SPEC; +impl crate::RegisterSpec for WPSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wpset::R](R) reader structure"] +impl crate::Readable for WPSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wpset::W](W) writer structure"] +impl crate::Writable for WPSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WPSET to value 0"] +impl crate::Resettable for WPSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm.rs b/pac/atsamda1j/src/pm.rs new file mode 100644 index 00000000000..2a5e9b74e89 --- /dev/null +++ b/pac/atsamda1j/src/pm.rs @@ -0,0 +1,98 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Sleep Mode"] + pub sleep: crate::Reg, + #[doc = "0x02 - External Reset Controller"] + pub extctrl: crate::Reg, + _reserved3: [u8; 0x05], + #[doc = "0x08 - CPU Clock Select"] + pub cpusel: crate::Reg, + #[doc = "0x09 - APBA Clock Select"] + pub apbasel: crate::Reg, + #[doc = "0x0a - APBB Clock Select"] + pub apbbsel: crate::Reg, + #[doc = "0x0b - APBC Clock Select"] + pub apbcsel: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0x14 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x18 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x1c - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x20 - APBC Mask"] + pub apbcmask: crate::Reg, + _reserved11: [u8; 0x10], + #[doc = "0x34 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x35 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x36 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved14: [u8; 0x01], + #[doc = "0x38 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SLEEP register accessor: an alias for `Reg`"] +pub type SLEEP = crate::Reg; +#[doc = "Sleep Mode"] +pub mod sleep; +#[doc = "EXTCTRL register accessor: an alias for `Reg`"] +pub type EXTCTRL = crate::Reg; +#[doc = "External Reset Controller"] +pub mod extctrl; +#[doc = "CPUSEL register accessor: an alias for `Reg`"] +pub type CPUSEL = crate::Reg; +#[doc = "CPU Clock Select"] +pub mod cpusel; +#[doc = "APBASEL register accessor: an alias for `Reg`"] +pub type APBASEL = crate::Reg; +#[doc = "APBA Clock Select"] +pub mod apbasel; +#[doc = "APBBSEL register accessor: an alias for `Reg`"] +pub type APBBSEL = crate::Reg; +#[doc = "APBB Clock Select"] +pub mod apbbsel; +#[doc = "APBCSEL register accessor: an alias for `Reg`"] +pub type APBCSEL = crate::Reg; +#[doc = "APBC Clock Select"] +pub mod apbcsel; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamda1j/src/pm/ahbmask.rs b/pac/atsamda1j/src/pm/ahbmask.rs new file mode 100644 index 00000000000..4a45a8dcdd6 --- /dev/null +++ b/pac/atsamda1j/src/pm/ahbmask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `USB_` reader - USB AHB Clock Mask"] +pub struct USB__R(crate::FieldReader); +impl USB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USB_` writer - USB AHB Clock Mask"] +pub struct USB__W<'a> { + w: &'a mut W, +} +impl<'a> USB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - USB AHB Clock Mask"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 6 - USB AHB Clock Mask"] + #[inline(always)] + pub fn usb_(&mut self) -> USB__W { + USB__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x7f"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1j/src/pm/apbamask.rs b/pac/atsamda1j/src/pm/apbamask.rs new file mode 100644 index 00000000000..857ab4989c6 --- /dev/null +++ b/pac/atsamda1j/src/pm/apbamask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC0_` reader - PAC0 APB Clock Enable"] +pub struct PAC0__R(crate::FieldReader); +impl PAC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC0_` writer - PAC0 APB Clock Enable"] +pub struct PAC0__W<'a> { + w: &'a mut W, +} +impl<'a> PAC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYSCTRL_` reader - SYSCTRL APB Clock Enable"] +pub struct SYSCTRL__R(crate::FieldReader); +impl SYSCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSCTRL_` writer - SYSCTRL APB Clock Enable"] +pub struct SYSCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> SYSCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC0 APB Clock Enable"] + #[inline(always)] + pub fn pac0_(&self) -> PAC0__R { + PAC0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SYSCTRL APB Clock Enable"] + #[inline(always)] + pub fn sysctrl_(&self) -> SYSCTRL__R { + SYSCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC0 APB Clock Enable"] + #[inline(always)] + pub fn pac0_(&mut self) -> PAC0__W { + PAC0__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - SYSCTRL APB Clock Enable"] + #[inline(always)] + pub fn sysctrl_(&mut self) -> SYSCTRL__W { + SYSCTRL__W { w: self } + } + #[doc = "Bit 3 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 4 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 5 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 6 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x7f"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1j/src/pm/apbasel.rs b/pac/atsamda1j/src/pm/apbasel.rs new file mode 100644 index 00000000000..494b59e7e3a --- /dev/null +++ b/pac/atsamda1j/src/pm/apbasel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBASEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBASEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBA Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBADIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBADIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBADIV` reader - APBA Prescaler Selection"] +pub struct APBADIV_R(crate::FieldReader); +impl APBADIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBADIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBADIV_A { + match self.bits { + 0 => APBADIV_A::DIV1, + 1 => APBADIV_A::DIV2, + 2 => APBADIV_A::DIV4, + 3 => APBADIV_A::DIV8, + 4 => APBADIV_A::DIV16, + 5 => APBADIV_A::DIV32, + 6 => APBADIV_A::DIV64, + 7 => APBADIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBADIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBADIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBADIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBADIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBADIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBADIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBADIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBADIV_A::DIV128 + } +} +impl core::ops::Deref for APBADIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBADIV` writer - APBA Prescaler Selection"] +pub struct APBADIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBADIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBADIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBADIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBADIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBADIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBADIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBADIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBADIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBADIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBADIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBA Prescaler Selection"] + #[inline(always)] + pub fn apbadiv(&self) -> APBADIV_R { + APBADIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBA Prescaler Selection"] + #[inline(always)] + pub fn apbadiv(&mut self) -> APBADIV_W { + APBADIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbasel](index.html) module"] +pub struct APBASEL_SPEC; +impl crate::RegisterSpec for APBASEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbasel::R](R) reader structure"] +impl crate::Readable for APBASEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbasel::W](W) writer structure"] +impl crate::Writable for APBASEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBASEL to value 0"] +impl crate::Resettable for APBASEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/apbbmask.rs b/pac/atsamda1j/src/pm/apbbmask.rs new file mode 100644 index 00000000000..92e2c404c22 --- /dev/null +++ b/pac/atsamda1j/src/pm/apbbmask.rs @@ -0,0 +1,395 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC1_` reader - PAC1 APB Clock Enable"] +pub struct PAC1__R(crate::FieldReader); +impl PAC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC1_` writer - PAC1 APB Clock Enable"] +pub struct PAC1__W<'a> { + w: &'a mut W, +} +impl<'a> PAC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Clock Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC APB Clock Enable"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `USB_` reader - USB APB Clock Enable"] +pub struct USB__R(crate::FieldReader); +impl USB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USB_` writer - USB APB Clock Enable"] +pub struct USB__W<'a> { + w: &'a mut W, +} +impl<'a> USB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HMATRIX_` reader - HMATRIX APB Clock Enable"] +pub struct HMATRIX__R(crate::FieldReader); +impl HMATRIX__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIX__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIX__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIX_` writer - HMATRIX APB Clock Enable"] +pub struct HMATRIX__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIX__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC1 APB Clock Enable"] + #[inline(always)] + pub fn pac1_(&self) -> PAC1__R { + PAC1__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DMAC APB Clock Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - USB APB Clock Enable"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HMATRIX APB Clock Enable"] + #[inline(always)] + pub fn hmatrix_(&self) -> HMATRIX__R { + HMATRIX__R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC1 APB Clock Enable"] + #[inline(always)] + pub fn pac1_(&mut self) -> PAC1__W { + PAC1__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 4 - DMAC APB Clock Enable"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 5 - USB APB Clock Enable"] + #[inline(always)] + pub fn usb_(&mut self) -> USB__W { + USB__W { w: self } + } + #[doc = "Bit 6 - HMATRIX APB Clock Enable"] + #[inline(always)] + pub fn hmatrix_(&mut self) -> HMATRIX__W { + HMATRIX__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x7f"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/pac/atsamda1j/src/pm/apbbsel.rs b/pac/atsamda1j/src/pm/apbbsel.rs new file mode 100644 index 00000000000..a935873b629 --- /dev/null +++ b/pac/atsamda1j/src/pm/apbbsel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBBSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBB Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBBDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBBDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBBDIV` reader - APBB Prescaler Selection"] +pub struct APBBDIV_R(crate::FieldReader); +impl APBBDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBBDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBBDIV_A { + match self.bits { + 0 => APBBDIV_A::DIV1, + 1 => APBBDIV_A::DIV2, + 2 => APBBDIV_A::DIV4, + 3 => APBBDIV_A::DIV8, + 4 => APBBDIV_A::DIV16, + 5 => APBBDIV_A::DIV32, + 6 => APBBDIV_A::DIV64, + 7 => APBBDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBBDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBBDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBBDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBBDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBBDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBBDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBBDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBBDIV_A::DIV128 + } +} +impl core::ops::Deref for APBBDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBBDIV` writer - APBB Prescaler Selection"] +pub struct APBBDIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBBDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBBDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBBDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBB Prescaler Selection"] + #[inline(always)] + pub fn apbbdiv(&self) -> APBBDIV_R { + APBBDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBB Prescaler Selection"] + #[inline(always)] + pub fn apbbdiv(&mut self) -> APBBDIV_W { + APBBDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbsel](index.html) module"] +pub struct APBBSEL_SPEC; +impl crate::RegisterSpec for APBBSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbbsel::R](R) reader structure"] +impl crate::Readable for APBBSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbsel::W](W) writer structure"] +impl crate::Writable for APBBSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBSEL to value 0"] +impl crate::Resettable for APBBSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/apbcmask.rs b/pac/atsamda1j/src/pm/apbcmask.rs new file mode 100644 index 00000000000..78a1439181f --- /dev/null +++ b/pac/atsamda1j/src/pm/apbcmask.rs @@ -0,0 +1,1053 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC2_` reader - PAC2 APB Clock Enable"] +pub struct PAC2__R(crate::FieldReader); +impl PAC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC2_` writer - PAC2 APB Clock Enable"] +pub struct PAC2__W<'a> { + w: &'a mut W, +} +impl<'a> PAC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5 APB Clock Enable"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5 APB Clock Enable"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6 APB Clock Enable"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6 APB Clock Enable"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7 APB Clock Enable"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7 APB Clock Enable"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADC_` reader - ADC APB Clock Enable"] +pub struct ADC__R(crate::FieldReader); +impl ADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_` writer - ADC APB Clock Enable"] +pub struct ADC__W<'a> { + w: &'a mut W, +} +impl<'a> ADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `I2S_` reader - I2S APB Clock Enable"] +pub struct I2S__R(crate::FieldReader); +impl I2S__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2S__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2S__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2S_` writer - I2S APB Clock Enable"] +pub struct I2S__W<'a> { + w: &'a mut W, +} +impl<'a> I2S__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC2 APB Clock Enable"] + #[inline(always)] + pub fn pac2_(&self) -> PAC2__R { + PAC2__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - ADC APB Clock Enable"] + #[inline(always)] + pub fn adc_(&self) -> ADC__R { + ADC__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - I2S APB Clock Enable"] + #[inline(always)] + pub fn i2s_(&self) -> I2S__R { + I2S__R::new(((self.bits >> 20) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC2 APB Clock Enable"] + #[inline(always)] + pub fn pac2_(&mut self) -> PAC2__W { + PAC2__W { w: self } + } + #[doc = "Bit 1 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 2 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 3 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 4 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 5 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 6 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 7 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 8 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 9 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 10 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 12 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 13 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 14 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 15 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Bit 16 - ADC APB Clock Enable"] + #[inline(always)] + pub fn adc_(&mut self) -> ADC__W { + ADC__W { w: self } + } + #[doc = "Bit 17 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 18 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 19 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 20 - I2S APB Clock Enable"] + #[inline(always)] + pub fn i2s_(&mut self) -> I2S__W { + I2S__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0x0001_0000"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0001_0000 + } +} diff --git a/pac/atsamda1j/src/pm/apbcsel.rs b/pac/atsamda1j/src/pm/apbcsel.rs new file mode 100644 index 00000000000..7669148bc17 --- /dev/null +++ b/pac/atsamda1j/src/pm/apbcsel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `APBCSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "APBC Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum APBCDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: APBCDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `APBCDIV` reader - APBC Prescaler Selection"] +pub struct APBCDIV_R(crate::FieldReader); +impl APBCDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + APBCDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> APBCDIV_A { + match self.bits { + 0 => APBCDIV_A::DIV1, + 1 => APBCDIV_A::DIV2, + 2 => APBCDIV_A::DIV4, + 3 => APBCDIV_A::DIV8, + 4 => APBCDIV_A::DIV16, + 5 => APBCDIV_A::DIV32, + 6 => APBCDIV_A::DIV64, + 7 => APBCDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == APBCDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == APBCDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == APBCDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == APBCDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == APBCDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == APBCDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == APBCDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == APBCDIV_A::DIV128 + } +} +impl core::ops::Deref for APBCDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APBCDIV` writer - APBC Prescaler Selection"] +pub struct APBCDIV_W<'a> { + w: &'a mut W, +} +impl<'a> APBCDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: APBCDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(APBCDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - APBC Prescaler Selection"] + #[inline(always)] + pub fn apbcdiv(&self) -> APBCDIV_R { + APBCDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - APBC Prescaler Selection"] + #[inline(always)] + pub fn apbcdiv(&mut self) -> APBCDIV_W { + APBCDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcsel](index.html) module"] +pub struct APBCSEL_SPEC; +impl crate::RegisterSpec for APBCSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [apbcsel::R](R) reader structure"] +impl crate::Readable for APBCSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcsel::W](W) writer structure"] +impl crate::Writable for APBCSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCSEL to value 0"] +impl crate::Resettable for APBCSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/cpusel.rs b/pac/atsamda1j/src/pm/cpusel.rs new file mode 100644 index 00000000000..5637b22ba7a --- /dev/null +++ b/pac/atsamda1j/src/pm/cpusel.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Prescaler Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "0: Divide by 1"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 32"] + DIV32 = 5, + #[doc = "6: Divide by 64"] + DIV64 = 6, + #[doc = "7: Divide by 128"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Prescaler Selection"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPUDIV_A { + match self.bits { + 0 => CPUDIV_A::DIV1, + 1 => CPUDIV_A::DIV2, + 2 => CPUDIV_A::DIV4, + 3 => CPUDIV_A::DIV8, + 4 => CPUDIV_A::DIV16, + 5 => CPUDIV_A::DIV32, + 6 => CPUDIV_A::DIV64, + 7 => CPUDIV_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Prescaler Selection"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - CPU Prescaler Selection"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - CPU Prescaler Selection"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpusel](index.html) module"] +pub struct CPUSEL_SPEC; +impl crate::RegisterSpec for CPUSEL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpusel::R](R) reader structure"] +impl crate::Readable for CPUSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpusel::W](W) writer structure"] +impl crate::Writable for CPUSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUSEL to value 0"] +impl crate::Resettable for CPUSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/ctrl.rs b/pac/atsamda1j/src/pm/ctrl.rs new file mode 100644 index 00000000000..bde0e70a237 --- /dev/null +++ b/pac/atsamda1j/src/pm/ctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/extctrl.rs b/pac/atsamda1j/src/pm/extctrl.rs new file mode 100644 index 00000000000..c4f97eedac5 --- /dev/null +++ b/pac/atsamda1j/src/pm/extctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EXTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SETDIS` reader - External Reset Disable"] +pub struct SETDIS_R(crate::FieldReader); +impl SETDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SETDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SETDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SETDIS` writer - External Reset Disable"] +pub struct SETDIS_W<'a> { + w: &'a mut W, +} +impl<'a> SETDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Reset Disable"] + #[inline(always)] + pub fn setdis(&self) -> SETDIS_R { + SETDIS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - External Reset Disable"] + #[inline(always)] + pub fn setdis(&mut self) -> SETDIS_W { + SETDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Reset Controller\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extctrl](index.html) module"] +pub struct EXTCTRL_SPEC; +impl crate::RegisterSpec for EXTCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [extctrl::R](R) reader structure"] +impl crate::Readable for EXTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [extctrl::W](W) writer structure"] +impl crate::Writable for EXTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EXTCTRL to value 0"] +impl crate::Resettable for EXTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/intenclr.rs b/pac/atsamda1j/src/pm/intenclr.rs new file mode 100644 index 00000000000..14feb632dbb --- /dev/null +++ b/pac/atsamda1j/src/pm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/intenset.rs b/pac/atsamda1j/src/pm/intenset.rs new file mode 100644 index 00000000000..f01fcc316d9 --- /dev/null +++ b/pac/atsamda1j/src/pm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/intflag.rs b/pac/atsamda1j/src/pm/intflag.rs new file mode 100644 index 00000000000..b5294af3d9d --- /dev/null +++ b/pac/atsamda1j/src/pm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/pm/rcause.rs b/pac/atsamda1j/src/pm/rcause.rs new file mode 100644 index 00000000000..dd192bbc19a --- /dev/null +++ b/pac/atsamda1j/src/pm/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD12` reader - Brown Out 12 Detector Reset"] +pub struct BOD12_R(crate::FieldReader); +impl BOD12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33` reader - Brown Out 33 Detector Reset"] +pub struct BOD33_R(crate::FieldReader); +impl BOD33_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out 12 Detector Reset"] + #[inline(always)] + pub fn bod12(&self) -> BOD12_R { + BOD12_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out 33 Detector Reset"] + #[inline(always)] + pub fn bod33(&self) -> BOD33_R { + BOD33_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0x01"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1j/src/pm/sleep.rs b/pac/atsamda1j/src/pm/sleep.rs new file mode 100644 index 00000000000..c30b443bde1 --- /dev/null +++ b/pac/atsamda1j/src/pm/sleep.rs @@ -0,0 +1,165 @@ +#[doc = "Register `SLEEP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Idle Mode Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDLE_A { + #[doc = "0: The CPU clock domain is stopped"] + CPU = 0, + #[doc = "1: The CPU and AHB clock domains are stopped"] + AHB = 1, + #[doc = "2: The CPU, AHB and APB clock domains are stopped"] + APB = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDLE_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDLE` reader - Idle Mode Configuration"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(IDLE_A::CPU), + 1 => Some(IDLE_A::AHB), + 2 => Some(IDLE_A::APB), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CPU`"] + #[inline(always)] + pub fn is_cpu(&self) -> bool { + **self == IDLE_A::CPU + } + #[doc = "Checks if the value of the field is `AHB`"] + #[inline(always)] + pub fn is_ahb(&self) -> bool { + **self == IDLE_A::AHB + } + #[doc = "Checks if the value of the field is `APB`"] + #[inline(always)] + pub fn is_apb(&self) -> bool { + **self == IDLE_A::APB + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` writer - Idle Mode Configuration"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDLE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The CPU clock domain is stopped"] + #[inline(always)] + pub fn cpu(self) -> &'a mut W { + self.variant(IDLE_A::CPU) + } + #[doc = "The CPU and AHB clock domains are stopped"] + #[inline(always)] + pub fn ahb(self) -> &'a mut W { + self.variant(IDLE_A::AHB) + } + #[doc = "The CPU, AHB and APB clock domains are stopped"] + #[inline(always)] + pub fn apb(self) -> &'a mut W { + self.variant(IDLE_A::APB) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Idle Mode Configuration"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Idle Mode Configuration"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleep](index.html) module"] +pub struct SLEEP_SPEC; +impl crate::RegisterSpec for SLEEP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleep::R](R) reader structure"] +impl crate::Readable for SLEEP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleep::W](W) writer structure"] +impl crate::Writable for SLEEP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEP to value 0"] +impl crate::Resettable for SLEEP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port.rs b/pac/atsamda1j/src/port.rs new file mode 100644 index 00000000000..cd5062cacbd --- /dev/null +++ b/pac/atsamda1j/src/port.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + _reserved11: [u8; 0x04], + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamda1j/src/port/group.rs b/pac/atsamda1j/src/port/group.rs new file mode 100644 index 00000000000..42529765a8d --- /dev/null +++ b/pac/atsamda1j/src/port/group.rs @@ -0,0 +1,52 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamda1j/src/port/group/ctrl.rs b/pac/atsamda1j/src/port/group/ctrl.rs new file mode 100644 index 00000000000..4b57cd6fcd2 --- /dev/null +++ b/pac/atsamda1j/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/dir.rs b/pac/atsamda1j/src/port/group/dir.rs new file mode 100644 index 00000000000..36f642e3c16 --- /dev/null +++ b/pac/atsamda1j/src/port/group/dir.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Port Data Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Port Data Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/dirclr.rs b/pac/atsamda1j/src/port/group/dirclr.rs new file mode 100644 index 00000000000..9d125c964aa --- /dev/null +++ b/pac/atsamda1j/src/port/group/dirclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRCLR` reader - Port Data Direction Clear"] +pub struct DIRCLR_R(crate::FieldReader); +impl DIRCLR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRCLR` writer - Port Data Direction Clear"] +pub struct DIRCLR_W<'a> { + w: &'a mut W, +} +impl<'a> DIRCLR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Clear"] + #[inline(always)] + pub fn dirclr(&self) -> DIRCLR_R { + DIRCLR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Clear"] + #[inline(always)] + pub fn dirclr(&mut self) -> DIRCLR_W { + DIRCLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/dirset.rs b/pac/atsamda1j/src/port/group/dirset.rs new file mode 100644 index 00000000000..f0a4679db6b --- /dev/null +++ b/pac/atsamda1j/src/port/group/dirset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRSET` reader - Port Data Direction Set"] +pub struct DIRSET_R(crate::FieldReader); +impl DIRSET_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRSET` writer - Port Data Direction Set"] +pub struct DIRSET_W<'a> { + w: &'a mut W, +} +impl<'a> DIRSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Set"] + #[inline(always)] + pub fn dirset(&self) -> DIRSET_R { + DIRSET_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Set"] + #[inline(always)] + pub fn dirset(&mut self) -> DIRSET_W { + DIRSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/dirtgl.rs b/pac/atsamda1j/src/port/group/dirtgl.rs new file mode 100644 index 00000000000..37339d76c54 --- /dev/null +++ b/pac/atsamda1j/src/port/group/dirtgl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIRTGL` reader - Port Data Direction Toggle"] +pub struct DIRTGL_R(crate::FieldReader); +impl DIRTGL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIRTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRTGL` writer - Port Data Direction Toggle"] +pub struct DIRTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DIRTGL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Direction Toggle"] + #[inline(always)] + pub fn dirtgl(&self) -> DIRTGL_R { + DIRTGL_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Direction Toggle"] + #[inline(always)] + pub fn dirtgl(&mut self) -> DIRTGL_W { + DIRTGL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/in_.rs b/pac/atsamda1j/src/port/group/in_.rs new file mode 100644 index 00000000000..1e84f070091 --- /dev/null +++ b/pac/atsamda1j/src/port/group/in_.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IN` reader - Port Data Input Value"] +pub struct IN_R(crate::FieldReader); +impl IN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Input Value"] + #[inline(always)] + pub fn in_(&self) -> IN_R { + IN_R::new(self.bits as u32) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/out.rs b/pac/atsamda1j/src/port/group/out.rs new file mode 100644 index 00000000000..48ecaa2358e --- /dev/null +++ b/pac/atsamda1j/src/port/group/out.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUT` reader - Port Data Output Value"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Port Data Output Value"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/outclr.rs b/pac/atsamda1j/src/port/group/outclr.rs new file mode 100644 index 00000000000..3ea8c378ed4 --- /dev/null +++ b/pac/atsamda1j/src/port/group/outclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTCLR` reader - Port Data Output Value Clear"] +pub struct OUTCLR_R(crate::FieldReader); +impl OUTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTCLR` writer - Port Data Output Value Clear"] +pub struct OUTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> OUTCLR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Clear"] + #[inline(always)] + pub fn outclr(&self) -> OUTCLR_R { + OUTCLR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Clear"] + #[inline(always)] + pub fn outclr(&mut self) -> OUTCLR_W { + OUTCLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/outset.rs b/pac/atsamda1j/src/port/group/outset.rs new file mode 100644 index 00000000000..e905e4508b2 --- /dev/null +++ b/pac/atsamda1j/src/port/group/outset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTSET` reader - Port Data Output Value Set"] +pub struct OUTSET_R(crate::FieldReader); +impl OUTSET_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTSET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTSET` writer - Port Data Output Value Set"] +pub struct OUTSET_W<'a> { + w: &'a mut W, +} +impl<'a> OUTSET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Set"] + #[inline(always)] + pub fn outset(&self) -> OUTSET_R { + OUTSET_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Set"] + #[inline(always)] + pub fn outset(&mut self) -> OUTSET_W { + OUTSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/outtgl.rs b/pac/atsamda1j/src/port/group/outtgl.rs new file mode 100644 index 00000000000..437b7f6681d --- /dev/null +++ b/pac/atsamda1j/src/port/group/outtgl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OUTTGL` reader - Port Data Output Value Toggle"] +pub struct OUTTGL_R(crate::FieldReader); +impl OUTTGL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OUTTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OUTTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUTTGL` writer - Port Data Output Value Toggle"] +pub struct OUTTGL_W<'a> { + w: &'a mut W, +} +impl<'a> OUTTGL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Port Data Output Value Toggle"] + #[inline(always)] + pub fn outtgl(&self) -> OUTTGL_R { + OUTTGL_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Port Data Output Value Toggle"] + #[inline(always)] + pub fn outtgl(&mut self) -> OUTTGL_W { + OUTTGL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/pincfg.rs b/pac/atsamda1j/src/port/group/pincfg.rs new file mode 100644 index 00000000000..215e64ba226 --- /dev/null +++ b/pac/atsamda1j/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Peripheral Multiplexer Enable"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Peripheral Multiplexer Enable"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/pmux.rs b/pac/atsamda1j/src/port/group/pmux.rs new file mode 100644 index 00000000000..98cf2bbec5b --- /dev/null +++ b/pac/atsamda1j/src/port/group/pmux.rs @@ -0,0 +1,395 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Peripheral Multiplexing Even\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PMUXE_A { + #[doc = "0: Peripheral function A selected"] + A = 0, + #[doc = "1: Peripheral function B selected"] + B = 1, + #[doc = "2: Peripheral function C selected"] + C = 2, + #[doc = "3: Peripheral function D selected"] + D = 3, + #[doc = "4: Peripheral function E selected"] + E = 4, + #[doc = "5: Peripheral function F selected"] + F = 5, + #[doc = "6: Peripheral function G selected"] + G = 6, + #[doc = "7: Peripheral function H selected"] + H = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PMUXE_A) -> Self { + variant as _ + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing Even"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PMUXE_A::A), + 1 => Some(PMUXE_A::B), + 2 => Some(PMUXE_A::C), + 3 => Some(PMUXE_A::D), + 4 => Some(PMUXE_A::E), + 5 => Some(PMUXE_A::F), + 6 => Some(PMUXE_A::G), + 7 => Some(PMUXE_A::H), + _ => None, + } + } + #[doc = "Checks if the value of the field is `A`"] + #[inline(always)] + pub fn is_a(&self) -> bool { + **self == PMUXE_A::A + } + #[doc = "Checks if the value of the field is `B`"] + #[inline(always)] + pub fn is_b(&self) -> bool { + **self == PMUXE_A::B + } + #[doc = "Checks if the value of the field is `C`"] + #[inline(always)] + pub fn is_c(&self) -> bool { + **self == PMUXE_A::C + } + #[doc = "Checks if the value of the field is `D`"] + #[inline(always)] + pub fn is_d(&self) -> bool { + **self == PMUXE_A::D + } + #[doc = "Checks if the value of the field is `E`"] + #[inline(always)] + pub fn is_e(&self) -> bool { + **self == PMUXE_A::E + } + #[doc = "Checks if the value of the field is `F`"] + #[inline(always)] + pub fn is_f(&self) -> bool { + **self == PMUXE_A::F + } + #[doc = "Checks if the value of the field is `G`"] + #[inline(always)] + pub fn is_g(&self) -> bool { + **self == PMUXE_A::G + } + #[doc = "Checks if the value of the field is `H`"] + #[inline(always)] + pub fn is_h(&self) -> bool { + **self == PMUXE_A::H + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing Even"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMUXE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral function A selected"] + #[inline(always)] + pub fn a(self) -> &'a mut W { + self.variant(PMUXE_A::A) + } + #[doc = "Peripheral function B selected"] + #[inline(always)] + pub fn b(self) -> &'a mut W { + self.variant(PMUXE_A::B) + } + #[doc = "Peripheral function C selected"] + #[inline(always)] + pub fn c(self) -> &'a mut W { + self.variant(PMUXE_A::C) + } + #[doc = "Peripheral function D selected"] + #[inline(always)] + pub fn d(self) -> &'a mut W { + self.variant(PMUXE_A::D) + } + #[doc = "Peripheral function E selected"] + #[inline(always)] + pub fn e(self) -> &'a mut W { + self.variant(PMUXE_A::E) + } + #[doc = "Peripheral function F selected"] + #[inline(always)] + pub fn f(self) -> &'a mut W { + self.variant(PMUXE_A::F) + } + #[doc = "Peripheral function G selected"] + #[inline(always)] + pub fn g(self) -> &'a mut W { + self.variant(PMUXE_A::G) + } + #[doc = "Peripheral function H selected"] + #[inline(always)] + pub fn h(self) -> &'a mut W { + self.variant(PMUXE_A::H) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Peripheral Multiplexing Odd\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PMUXO_A { + #[doc = "0: Peripheral function A selected"] + A = 0, + #[doc = "1: Peripheral function B selected"] + B = 1, + #[doc = "2: Peripheral function C selected"] + C = 2, + #[doc = "3: Peripheral function D selected"] + D = 3, + #[doc = "4: Peripheral function E selected"] + E = 4, + #[doc = "5: Peripheral function F selected"] + F = 5, + #[doc = "6: Peripheral function G selected"] + G = 6, + #[doc = "7: Peripheral function H selected"] + H = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PMUXO_A) -> Self { + variant as _ + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing Odd"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PMUXO_A::A), + 1 => Some(PMUXO_A::B), + 2 => Some(PMUXO_A::C), + 3 => Some(PMUXO_A::D), + 4 => Some(PMUXO_A::E), + 5 => Some(PMUXO_A::F), + 6 => Some(PMUXO_A::G), + 7 => Some(PMUXO_A::H), + _ => None, + } + } + #[doc = "Checks if the value of the field is `A`"] + #[inline(always)] + pub fn is_a(&self) -> bool { + **self == PMUXO_A::A + } + #[doc = "Checks if the value of the field is `B`"] + #[inline(always)] + pub fn is_b(&self) -> bool { + **self == PMUXO_A::B + } + #[doc = "Checks if the value of the field is `C`"] + #[inline(always)] + pub fn is_c(&self) -> bool { + **self == PMUXO_A::C + } + #[doc = "Checks if the value of the field is `D`"] + #[inline(always)] + pub fn is_d(&self) -> bool { + **self == PMUXO_A::D + } + #[doc = "Checks if the value of the field is `E`"] + #[inline(always)] + pub fn is_e(&self) -> bool { + **self == PMUXO_A::E + } + #[doc = "Checks if the value of the field is `F`"] + #[inline(always)] + pub fn is_f(&self) -> bool { + **self == PMUXO_A::F + } + #[doc = "Checks if the value of the field is `G`"] + #[inline(always)] + pub fn is_g(&self) -> bool { + **self == PMUXO_A::G + } + #[doc = "Checks if the value of the field is `H`"] + #[inline(always)] + pub fn is_h(&self) -> bool { + **self == PMUXO_A::H + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing Odd"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMUXO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral function A selected"] + #[inline(always)] + pub fn a(self) -> &'a mut W { + self.variant(PMUXO_A::A) + } + #[doc = "Peripheral function B selected"] + #[inline(always)] + pub fn b(self) -> &'a mut W { + self.variant(PMUXO_A::B) + } + #[doc = "Peripheral function C selected"] + #[inline(always)] + pub fn c(self) -> &'a mut W { + self.variant(PMUXO_A::C) + } + #[doc = "Peripheral function D selected"] + #[inline(always)] + pub fn d(self) -> &'a mut W { + self.variant(PMUXO_A::D) + } + #[doc = "Peripheral function E selected"] + #[inline(always)] + pub fn e(self) -> &'a mut W { + self.variant(PMUXO_A::E) + } + #[doc = "Peripheral function F selected"] + #[inline(always)] + pub fn f(self) -> &'a mut W { + self.variant(PMUXO_A::F) + } + #[doc = "Peripheral function G selected"] + #[inline(always)] + pub fn g(self) -> &'a mut W { + self.variant(PMUXO_A::G) + } + #[doc = "Peripheral function H selected"] + #[inline(always)] + pub fn h(self) -> &'a mut W { + self.variant(PMUXO_A::H) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing Even"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing Odd"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing Even"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing Odd"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/port/group/wrconfig.rs b/pac/atsamda1j/src/port/group/wrconfig.rs new file mode 100644 index 00000000000..67177b9fa53 --- /dev/null +++ b/pac/atsamda1j/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Peripheral Multiplexer Enable"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Peripheral Multiplexer Enable"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc.rs b/pac/atsamda1j/src/rtc.rs new file mode 100644 index 00000000000..47c627343b6 --- /dev/null +++ b/pac/atsamda1j/src/rtc.rs @@ -0,0 +1,123 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x1d], +} +impl RegisterBlock { + #[doc = "0x00..0x1d - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x1c - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x1c - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x18 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x14 - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x18 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x06 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x07 - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Status"] + pub status: crate::Reg, + #[doc = "0x0b - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0c - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved9: [u8; 0x03], + #[doc = "0x10 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x18 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x1c - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamda1j/src/rtc/mode0.rs b/pac/atsamda1j/src/rtc/mode0.rs new file mode 100644 index 00000000000..8dc0e3eea44 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0.rs @@ -0,0 +1,44 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE0 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamda1j/src/rtc/mode0/comp.rs b/pac/atsamda1j/src/rtc/mode0/comp.rs new file mode 100644 index 00000000000..a909d3cea2d --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/count.rs b/pac/atsamda1j/src/rtc/mode0/count.rs new file mode 100644 index 00000000000..cf880b5e77a --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/ctrl.rs b/pac/atsamda1j/src/rtc/mode0/ctrl.rs new file mode 100644 index 00000000000..e32ff1ab1dc --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/ctrl.rs @@ -0,0 +1,509 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/dbgctrl.rs b/pac/atsamda1j/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/evctrl.rs b/pac/atsamda1j/src/rtc/mode0/evctrl.rs new file mode 100644 index 00000000000..e06b491ad66 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/freqcorr.rs b/pac/atsamda1j/src/rtc/mode0/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/intenclr.rs b/pac/atsamda1j/src/rtc/mode0/intenclr.rs new file mode 100644 index 00000000000..3b44cce826b --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/intenset.rs b/pac/atsamda1j/src/rtc/mode0/intenset.rs new file mode 100644 index 00000000000..46c47783336 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/intflag.rs b/pac/atsamda1j/src/rtc/mode0/intflag.rs new file mode 100644 index 00000000000..991f5424f3f --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/readreq.rs b/pac/atsamda1j/src/rtc/mode0/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1j/src/rtc/mode0/status.rs b/pac/atsamda1j/src/rtc/mode0/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode0/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1.rs b/pac/atsamda1j/src/rtc/mode1.rs new file mode 100644 index 00000000000..4582204fc4a --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1.rs @@ -0,0 +1,48 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE1 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamda1j/src/rtc/mode1/comp.rs b/pac/atsamda1j/src/rtc/mode1/comp.rs new file mode 100644 index 00000000000..6935385840f --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/count.rs b/pac/atsamda1j/src/rtc/mode1/count.rs new file mode 100644 index 00000000000..2c41937b189 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/ctrl.rs b/pac/atsamda1j/src/rtc/mode1/ctrl.rs new file mode 100644 index 00000000000..6d513fa447d --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/ctrl.rs @@ -0,0 +1,462 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/dbgctrl.rs b/pac/atsamda1j/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/evctrl.rs b/pac/atsamda1j/src/rtc/mode1/evctrl.rs new file mode 100644 index 00000000000..28fad144acf --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/freqcorr.rs b/pac/atsamda1j/src/rtc/mode1/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/intenclr.rs b/pac/atsamda1j/src/rtc/mode1/intenclr.rs new file mode 100644 index 00000000000..69074385c72 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/intenset.rs b/pac/atsamda1j/src/rtc/mode1/intenset.rs new file mode 100644 index 00000000000..c3751bcd1c5 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/intflag.rs b/pac/atsamda1j/src/rtc/mode1/intflag.rs new file mode 100644 index 00000000000..f138167c02f --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 1 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/per.rs b/pac/atsamda1j/src/rtc/mode1/per.rs new file mode 100644 index 00000000000..c09b31fa30d --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/readreq.rs b/pac/atsamda1j/src/rtc/mode1/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1j/src/rtc/mode1/status.rs b/pac/atsamda1j/src/rtc/mode1/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode1/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2.rs b/pac/atsamda1j/src/rtc/mode2.rs new file mode 100644 index 00000000000..1d505a71021 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2.rs @@ -0,0 +1,48 @@ +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "MODE2 Control"] +pub mod ctrl; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamda1j/src/rtc/mode2/alarm.rs b/pac/atsamda1j/src/rtc/mode2/alarm.rs new file mode 100644 index 00000000000..1242477ea69 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/clock.rs b/pac/atsamda1j/src/rtc/mode2/clock.rs new file mode 100644 index 00000000000..3f364ff8e57 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/ctrl.rs b/pac/atsamda1j/src/rtc/mode2/ctrl.rs new file mode 100644 index 00000000000..a66d90c2afa --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/ctrl.rs @@ -0,0 +1,556 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV1), + 1 => Some(PRESCALER_A::DIV2), + 2 => Some(PRESCALER_A::DIV4), + 3 => Some(PRESCALER_A::DIV8), + 4 => Some(PRESCALER_A::DIV16), + 5 => Some(PRESCALER_A::DIV32), + 6 => Some(PRESCALER_A::DIV64), + 7 => Some(PRESCALER_A::DIV128), + 8 => Some(PRESCALER_A::DIV256), + 9 => Some(PRESCALER_A::DIV512), + 10 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/dbgctrl.rs b/pac/atsamda1j/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 00000000000..0383e70d042 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/evctrl.rs b/pac/atsamda1j/src/rtc/mode2/evctrl.rs new file mode 100644 index 00000000000..1d66be29f63 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/freqcorr.rs b/pac/atsamda1j/src/rtc/mode2/freqcorr.rs new file mode 100644 index 00000000000..043ba6f88eb --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/intenclr.rs b/pac/atsamda1j/src/rtc/mode2/intenclr.rs new file mode 100644 index 00000000000..b7fc6efcaeb --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/intenset.rs b/pac/atsamda1j/src/rtc/mode2/intenset.rs new file mode 100644 index 00000000000..c21bec8514d --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/intflag.rs b/pac/atsamda1j/src/rtc/mode2/intflag.rs new file mode 100644 index 00000000000..651fb283181 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 6 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 7 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/mask.rs b/pac/atsamda1j/src/rtc/mode2/mask.rs new file mode 100644 index 00000000000..53e0bb491a6 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/readreq.rs b/pac/atsamda1j/src/rtc/mode2/readreq.rs new file mode 100644 index 00000000000..3a6e8d70fb4 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u16 & 0x3f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0x10"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamda1j/src/rtc/mode2/status.rs b/pac/atsamda1j/src/rtc/mode2/status.rs new file mode 100644 index 00000000000..8fb21d1d482 --- /dev/null +++ b/pac/atsamda1j/src/rtc/mode2/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` writer - Synchronization Busy"] +pub struct SYNCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&mut self) -> SYNCBUSY_W { + SYNCBUSY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sbmatrix.rs b/pac/atsamda1j/src/sbmatrix.rs new file mode 100644 index 00000000000..460bbc3fab0 --- /dev/null +++ b/pac/atsamda1j/src/sbmatrix.rs @@ -0,0 +1,25 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x80], + #[doc = "0x80..0x100 - PRS\\[%s\\]"] + pub prs: [PRS; 16], + _reserved1: [u8; 0x10], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamda1j/src/sbmatrix/prs.rs b/pac/atsamda1j/src/sbmatrix/prs.rs new file mode 100644 index 00000000000..0313f3c4fc2 --- /dev/null +++ b/pac/atsamda1j/src/sbmatrix/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamda1j/src/sbmatrix/prs/pras.rs b/pac/atsamda1j/src/sbmatrix/prs/pras.rs new file mode 100644 index 00000000000..9c009454899 --- /dev/null +++ b/pac/atsamda1j/src/sbmatrix/prs/pras.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sbmatrix/prs/prbs.rs b/pac/atsamda1j/src/sbmatrix/prs/prbs.rs new file mode 100644 index 00000000000..b92922b5d85 --- /dev/null +++ b/pac/atsamda1j/src/sbmatrix/prs/prbs.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sbmatrix/sfr.rs b/pac/atsamda1j/src/sbmatrix/sfr.rs new file mode 100644 index 00000000000..0a7e024f73c --- /dev/null +++ b/pac/atsamda1j/src/sbmatrix/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0.rs b/pac/atsamda1j/src/sercom0.rs new file mode 100644 index 00000000000..41bcdc65741 --- /dev/null +++ b/pac/atsamda1j/src/sercom0.rs @@ -0,0 +1,325 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + _reserved_2_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved4: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + _reserved_2_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved4: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamda1j/src/sercom0/i2cm.rs b/pac/atsamda1j/src/sercom0/i2cm.rs new file mode 100644 index 00000000000..8aa217da8b1 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1j/src/sercom0/i2cm/addr.rs b/pac/atsamda1j/src/sercom0/i2cm/addr.rs new file mode 100644 index 00000000000..4efd19e824c --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/baud.rs b/pac/atsamda1j/src/sercom0/i2cm/baud.rs new file mode 100644 index 00000000000..7c98d3b5b0d --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/ctrla.rs b/pac/atsamda1j/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 00000000000..34fa668b796 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/ctrlb.rs b/pac/atsamda1j/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 00000000000..ce534463c0d --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/data.rs b/pac/atsamda1j/src/sercom0/i2cm/data.rs new file mode 100644 index 00000000000..cf204596d3a --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamda1j/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 00000000000..0fffdb4c6e3 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/intenclr.rs b/pac/atsamda1j/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 00000000000..17f067a5565 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/intenset.rs b/pac/atsamda1j/src/sercom0/i2cm/intenset.rs new file mode 100644 index 00000000000..a0cbf96b3aa --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/intflag.rs b/pac/atsamda1j/src/sercom0/i2cm/intflag.rs new file mode 100644 index 00000000000..0fb0d2b9060 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/status.rs b/pac/atsamda1j/src/sercom0/i2cm/status.rs new file mode 100644 index 00000000000..95af23673ec --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cm/syncbusy.rs b/pac/atsamda1j/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 00000000000..87dd418d1cd --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs.rs b/pac/atsamda1j/src/sercom0/i2cs.rs new file mode 100644 index 00000000000..baf9513c6cc --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamda1j/src/sercom0/i2cs/addr.rs b/pac/atsamda1j/src/sercom0/i2cs/addr.rs new file mode 100644 index 00000000000..c1b69ee2289 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/ctrla.rs b/pac/atsamda1j/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 00000000000..ec93812b004 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/ctrlb.rs b/pac/atsamda1j/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 00000000000..b20f48581ed --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/data.rs b/pac/atsamda1j/src/sercom0/i2cs/data.rs new file mode 100644 index 00000000000..d8bfe070431 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/intenclr.rs b/pac/atsamda1j/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 00000000000..49f5191c8d6 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/intenset.rs b/pac/atsamda1j/src/sercom0/i2cs/intenset.rs new file mode 100644 index 00000000000..97ea784d747 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/intflag.rs b/pac/atsamda1j/src/sercom0/i2cs/intflag.rs new file mode 100644 index 00000000000..2eee333e4e5 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/status.rs b/pac/atsamda1j/src/sercom0/i2cs/status.rs new file mode 100644 index 00000000000..b3f6d218fa6 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/i2cs/syncbusy.rs b/pac/atsamda1j/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 00000000000..38e2509d966 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim.rs b/pac/atsamda1j/src/sercom0/spim.rs new file mode 100644 index 00000000000..528e38e1b81 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1j/src/sercom0/spim/addr.rs b/pac/atsamda1j/src/sercom0/spim/addr.rs new file mode 100644 index 00000000000..7c25cd522ea --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/baud.rs b/pac/atsamda1j/src/sercom0/spim/baud.rs new file mode 100644 index 00000000000..6bec9ca7435 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/ctrla.rs b/pac/atsamda1j/src/sercom0/spim/ctrla.rs new file mode 100644 index 00000000000..44028f8cbdd --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/ctrlb.rs b/pac/atsamda1j/src/sercom0/spim/ctrlb.rs new file mode 100644 index 00000000000..3d94f824ce8 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/data.rs b/pac/atsamda1j/src/sercom0/spim/data.rs new file mode 100644 index 00000000000..dc9cd020d2a --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/dbgctrl.rs b/pac/atsamda1j/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 00000000000..d9aa7495940 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/intenclr.rs b/pac/atsamda1j/src/sercom0/spim/intenclr.rs new file mode 100644 index 00000000000..ccab3de4348 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/intenset.rs b/pac/atsamda1j/src/sercom0/spim/intenset.rs new file mode 100644 index 00000000000..d9779cf897c --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/intflag.rs b/pac/atsamda1j/src/sercom0/spim/intflag.rs new file mode 100644 index 00000000000..e9bc10c271b --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/status.rs b/pac/atsamda1j/src/sercom0/spim/status.rs new file mode 100644 index 00000000000..9919460bf0e --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spim/syncbusy.rs b/pac/atsamda1j/src/sercom0/spim/syncbusy.rs new file mode 100644 index 00000000000..bee13adf708 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis.rs b/pac/atsamda1j/src/sercom0/spis.rs new file mode 100644 index 00000000000..eed10c90c46 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1j/src/sercom0/spis/addr.rs b/pac/atsamda1j/src/sercom0/spis/addr.rs new file mode 100644 index 00000000000..5fca0a698bf --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/baud.rs b/pac/atsamda1j/src/sercom0/spis/baud.rs new file mode 100644 index 00000000000..eeee4cf633e --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/ctrla.rs b/pac/atsamda1j/src/sercom0/spis/ctrla.rs new file mode 100644 index 00000000000..6151433a852 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/ctrlb.rs b/pac/atsamda1j/src/sercom0/spis/ctrlb.rs new file mode 100644 index 00000000000..ccb70582cf3 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/data.rs b/pac/atsamda1j/src/sercom0/spis/data.rs new file mode 100644 index 00000000000..4edf8089b29 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/dbgctrl.rs b/pac/atsamda1j/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 00000000000..ec36bbd2605 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/intenclr.rs b/pac/atsamda1j/src/sercom0/spis/intenclr.rs new file mode 100644 index 00000000000..e4c9ee0d506 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/intenset.rs b/pac/atsamda1j/src/sercom0/spis/intenset.rs new file mode 100644 index 00000000000..99582a624eb --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/intflag.rs b/pac/atsamda1j/src/sercom0/spis/intflag.rs new file mode 100644 index 00000000000..589e73c2329 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/status.rs b/pac/atsamda1j/src/sercom0/spis/status.rs new file mode 100644 index 00000000000..55c39c1a709 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/spis/syncbusy.rs b/pac/atsamda1j/src/sercom0/spis/syncbusy.rs new file mode 100644 index 00000000000..ac2f2e2c27e --- /dev/null +++ b/pac/atsamda1j/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext.rs b/pac/atsamda1j/src/sercom0/usart_ext.rs new file mode 100644 index 00000000000..09204a683ce --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1j/src/sercom0/usart_ext/baud.rs b/pac/atsamda1j/src/sercom0/usart_ext/baud.rs new file mode 100644 index 00000000000..9558a8e1a52 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamda1j/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 00000000000..d7cdd4570e2 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamda1j/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 00000000000..c1dc5080767 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamda1j/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 00000000000..8d4db16e024 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/ctrla.rs b/pac/atsamda1j/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 00000000000..bb4db0ad4db --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1256 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + PAD0 = 0, + #[doc = "1: PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + PAD1 = 1, + #[doc = "2: PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + PAD2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD1), + 2 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == TXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(TXPO_A::PAD1) + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Sample Adjustment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPA_A { + #[doc = "0: 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + ADJ0 = 0, + #[doc = "1: 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + ADJ1 = 1, + #[doc = "2: 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + ADJ2 = 2, + #[doc = "3: 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + ADJ3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPA_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SAMPA_A { + match self.bits { + 0 => SAMPA_A::ADJ0, + 1 => SAMPA_A::ADJ1, + 2 => SAMPA_A::ADJ2, + 3 => SAMPA_A::ADJ3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ADJ0`"] + #[inline(always)] + pub fn is_adj0(&self) -> bool { + **self == SAMPA_A::ADJ0 + } + #[doc = "Checks if the value of the field is `ADJ1`"] + #[inline(always)] + pub fn is_adj1(&self) -> bool { + **self == SAMPA_A::ADJ1 + } + #[doc = "Checks if the value of the field is `ADJ2`"] + #[inline(always)] + pub fn is_adj2(&self) -> bool { + **self == SAMPA_A::ADJ2 + } + #[doc = "Checks if the value of the field is `ADJ3`"] + #[inline(always)] + pub fn is_adj3(&self) -> bool { + **self == SAMPA_A::ADJ3 + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPA_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + #[inline(always)] + pub fn adj0(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ0) + } + #[doc = "16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + #[inline(always)] + pub fn adj1(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ1) + } + #[doc = "16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + #[inline(always)] + pub fn adj2(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ2) + } + #[doc = "16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + #[inline(always)] + pub fn adj3(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamda1j/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 00000000000..b821c8eb783 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,614 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/data.rs b/pac/atsamda1j/src/sercom0/usart_ext/data.rs new file mode 100644 index 00000000000..a54152c9571 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamda1j/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 00000000000..6c844f3fe40 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/intenclr.rs b/pac/atsamda1j/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 00000000000..a815553ce66 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/intenset.rs b/pac/atsamda1j/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 00000000000..e800681cf42 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/intflag.rs b/pac/atsamda1j/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 00000000000..4b0be279a9a --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/rxpl.rs b/pac/atsamda1j/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 00000000000..174464dc16b --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/status.rs b/pac/atsamda1j/src/sercom0/usart_ext/status.rs new file mode 100644 index 00000000000..a0c50c1bc2c --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamda1j/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 00000000000..7c3b817bbb0 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int.rs b/pac/atsamda1j/src/sercom0/usart_int.rs new file mode 100644 index 00000000000..d19ecaceea5 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamda1j/src/sercom0/usart_int/baud.rs b/pac/atsamda1j/src/sercom0/usart_int/baud.rs new file mode 100644 index 00000000000..a82df20712b --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamda1j/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 00000000000..b9c7fa4c4b2 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamda1j/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 00000000000..0671db99cc9 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamda1j/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 00000000000..b49a7ef5b84 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/ctrla.rs b/pac/atsamda1j/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 00000000000..76aed2866aa --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1256 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + PAD0 = 0, + #[doc = "1: PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + PAD1 = 1, + #[doc = "2: PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + PAD2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD1), + 2 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == TXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[1\\] += XCK"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "PAD\\[2\\] += TxD; PAD\\[3\\] += XCK"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(TXPO_A::PAD1) + } + #[doc = "PAD\\[0\\] += TxD; PAD\\[2\\] += RTS; PAD\\[3\\] += CTS"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Sample Adjustment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPA_A { + #[doc = "0: 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + ADJ0 = 0, + #[doc = "1: 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + ADJ1 = 1, + #[doc = "2: 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + ADJ2 = 2, + #[doc = "3: 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + ADJ3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPA_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SAMPA_A { + match self.bits { + 0 => SAMPA_A::ADJ0, + 1 => SAMPA_A::ADJ1, + 2 => SAMPA_A::ADJ2, + 3 => SAMPA_A::ADJ3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ADJ0`"] + #[inline(always)] + pub fn is_adj0(&self) -> bool { + **self == SAMPA_A::ADJ0 + } + #[doc = "Checks if the value of the field is `ADJ1`"] + #[inline(always)] + pub fn is_adj1(&self) -> bool { + **self == SAMPA_A::ADJ1 + } + #[doc = "Checks if the value of the field is `ADJ2`"] + #[inline(always)] + pub fn is_adj2(&self) -> bool { + **self == SAMPA_A::ADJ2 + } + #[doc = "Checks if the value of the field is `ADJ3`"] + #[inline(always)] + pub fn is_adj3(&self) -> bool { + **self == SAMPA_A::ADJ3 + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPA_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5"] + #[inline(always)] + pub fn adj0(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ0) + } + #[doc = "16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6"] + #[inline(always)] + pub fn adj1(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ1) + } + #[doc = "16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7"] + #[inline(always)] + pub fn adj2(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ2) + } + #[doc = "16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8"] + #[inline(always)] + pub fn adj3(self) -> &'a mut W { + self.variant(SAMPA_A::ADJ3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/ctrlb.rs b/pac/atsamda1j/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 00000000000..5c6cc4e67ee --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,614 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/data.rs b/pac/atsamda1j/src/sercom0/usart_int/data.rs new file mode 100644 index 00000000000..19d74c337d4 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamda1j/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 00000000000..0ac5b9c7b90 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/intenclr.rs b/pac/atsamda1j/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 00000000000..5ad23ad1563 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/intenset.rs b/pac/atsamda1j/src/sercom0/usart_int/intenset.rs new file mode 100644 index 00000000000..457f440e13e --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/intflag.rs b/pac/atsamda1j/src/sercom0/usart_int/intflag.rs new file mode 100644 index 00000000000..a6a26321b8c --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/rxpl.rs b/pac/atsamda1j/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 00000000000..324cbac371c --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/status.rs b/pac/atsamda1j/src/sercom0/usart_int/status.rs new file mode 100644 index 00000000000..1a92018a359 --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sercom0/usart_int/syncbusy.rs b/pac/atsamda1j/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 00000000000..5dea9a5a7ba --- /dev/null +++ b/pac/atsamda1j/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sys_tick.rs b/pac/atsamda1j/src/sys_tick.rs new file mode 100644 index 00000000000..b0fe7a59e5e --- /dev/null +++ b/pac/atsamda1j/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamda1j/src/sys_tick/calib.rs b/pac/atsamda1j/src/sys_tick/calib.rs new file mode 100644 index 00000000000..df7fd80f773 --- /dev/null +++ b/pac/atsamda1j/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sys_tick/csr.rs b/pac/atsamda1j/src/sys_tick/csr.rs new file mode 100644 index 00000000000..872d637f5a8 --- /dev/null +++ b/pac/atsamda1j/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamda1j/src/sys_tick/cvr.rs b/pac/atsamda1j/src/sys_tick/cvr.rs new file mode 100644 index 00000000000..8a40b5f43b3 --- /dev/null +++ b/pac/atsamda1j/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sys_tick/rvr.rs b/pac/atsamda1j/src/sys_tick/rvr.rs new file mode 100644 index 00000000000..ac023ff75f3 --- /dev/null +++ b/pac/atsamda1j/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl.rs b/pac/atsamda1j/src/sysctrl.rs new file mode 100644 index 00000000000..91255f3491a --- /dev/null +++ b/pac/atsamda1j/src/sysctrl.rs @@ -0,0 +1,132 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub pclksr: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xosc: crate::Reg, + _reserved5: [u8; 0x02], + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + _reserved6: [u8; 0x02], + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x20 - 8MHz Internal Oscillator (OSC8M) Control"] + pub osc8m: crate::Reg, + #[doc = "0x24 - DFLL48M Control"] + pub dfllctrl: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x28 - DFLL48M Value"] + pub dfllval: crate::Reg, + #[doc = "0x2c - DFLL48M Multiplier"] + pub dfllmul: crate::Reg, + #[doc = "0x30 - DFLL48M Synchronization"] + pub dfllsync: crate::Reg, + _reserved13: [u8; 0x03], + #[doc = "0x34 - 3.3V Brown-Out Detector (BOD33) Control"] + pub bod33: crate::Reg, + _reserved14: [u8; 0x04], + #[doc = "0x3c - Voltage Regulator System (VREG) Control"] + pub vreg: crate::Reg, + _reserved15: [u8; 0x02], + #[doc = "0x40 - Voltage References System (VREF) Control"] + pub vref: crate::Reg, + #[doc = "0x44 - DPLL Control A"] + pub dpllctrla: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x48 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x4c - DPLL Control B"] + pub dpllctrlb: crate::Reg, + #[doc = "0x50 - DPLL Status"] + pub dpllstatus: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "PCLKSR register accessor: an alias for `Reg`"] +pub type PCLKSR = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod pclksr; +#[doc = "XOSC register accessor: an alias for `Reg`"] +pub type XOSC = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xosc; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; +#[doc = "OSC8M register accessor: an alias for `Reg`"] +pub type OSC8M = crate::Reg; +#[doc = "8MHz Internal Oscillator (OSC8M) Control"] +pub mod osc8m; +#[doc = "DFLLCTRL register accessor: an alias for `Reg`"] +pub type DFLLCTRL = crate::Reg; +#[doc = "DFLL48M Control"] +pub mod dfllctrl; +#[doc = "DFLLVAL register accessor: an alias for `Reg`"] +pub type DFLLVAL = crate::Reg; +#[doc = "DFLL48M Value"] +pub mod dfllval; +#[doc = "DFLLMUL register accessor: an alias for `Reg`"] +pub type DFLLMUL = crate::Reg; +#[doc = "DFLL48M Multiplier"] +pub mod dfllmul; +#[doc = "DFLLSYNC register accessor: an alias for `Reg`"] +pub type DFLLSYNC = crate::Reg; +#[doc = "DFLL48M Synchronization"] +pub mod dfllsync; +#[doc = "BOD33 register accessor: an alias for `Reg`"] +pub type BOD33 = crate::Reg; +#[doc = "3.3V Brown-Out Detector (BOD33) Control"] +pub mod bod33; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "Voltage Regulator System (VREG) Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "Voltage References System (VREF) Control"] +pub mod vref; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control A"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "DPLL Control B"] +pub mod dpllctrlb; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; diff --git a/pac/atsamda1j/src/sysctrl/bod33.rs b/pac/atsamda1j/src/sysctrl/bod33.rs new file mode 100644 index 00000000000..f4678865a1f --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/bod33.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BOD33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOD33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "BOD33 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BOD33 generates a reset"] + RESET = 1, + #[doc = "2: The BOD33 generates an interrupt"] + INTERRUPT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - BOD33 Action"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INTERRUPT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INTERRUPT`"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + **self == ACTION_A::INTERRUPT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - BOD33 Action"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BOD33 generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BOD33 generates an interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut W { + self.variant(ACTION_A::INTERRUPT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MODE` reader - Operation Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operation Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CEN` reader - Clock Enable"] +pub struct CEN_R(crate::FieldReader); +impl CEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CEN` writer - Clock Enable"] +pub struct CEN_W<'a> { + w: &'a mut W, +} +impl<'a> CEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1K = 9, + #[doc = "10: Divide clock by 2048"] + DIV2K = 10, + #[doc = "11: Divide clock by 4096"] + DIV4K = 11, + #[doc = "12: Divide clock by 8192"] + DIV8K = 12, + #[doc = "13: Divide clock by 16384"] + DIV16K = 13, + #[doc = "14: Divide clock by 32768"] + DIV32K = 14, + #[doc = "15: Divide clock by 65536"] + DIV64K = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1K, + 10 => PSEL_A::DIV2K, + 11 => PSEL_A::DIV4K, + 12 => PSEL_A::DIV8K, + 13 => PSEL_A::DIV16K, + 14 => PSEL_A::DIV32K, + 15 => PSEL_A::DIV64K, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1K`"] + #[inline(always)] + pub fn is_div1k(&self) -> bool { + **self == PSEL_A::DIV1K + } + #[doc = "Checks if the value of the field is `DIV2K`"] + #[inline(always)] + pub fn is_div2k(&self) -> bool { + **self == PSEL_A::DIV2K + } + #[doc = "Checks if the value of the field is `DIV4K`"] + #[inline(always)] + pub fn is_div4k(&self) -> bool { + **self == PSEL_A::DIV4K + } + #[doc = "Checks if the value of the field is `DIV8K`"] + #[inline(always)] + pub fn is_div8k(&self) -> bool { + **self == PSEL_A::DIV8K + } + #[doc = "Checks if the value of the field is `DIV16K`"] + #[inline(always)] + pub fn is_div16k(&self) -> bool { + **self == PSEL_A::DIV16K + } + #[doc = "Checks if the value of the field is `DIV32K`"] + #[inline(always)] + pub fn is_div32k(&self) -> bool { + **self == PSEL_A::DIV32K + } + #[doc = "Checks if the value of the field is `DIV64K`"] + #[inline(always)] + pub fn is_div64k(&self) -> bool { + **self == PSEL_A::DIV64K + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1k(self) -> &'a mut W { + self.variant(PSEL_A::DIV1K) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2k(self) -> &'a mut W { + self.variant(PSEL_A::DIV2K) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4k(self) -> &'a mut W { + self.variant(PSEL_A::DIV4K) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8k(self) -> &'a mut W { + self.variant(PSEL_A::DIV8K) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16k(self) -> &'a mut W { + self.variant(PSEL_A::DIV16K) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32k(self) -> &'a mut W { + self.variant(PSEL_A::DIV32K) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div64k(self) -> &'a mut W { + self.variant(PSEL_A::DIV64K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - BOD33 Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - BOD33 Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - BOD33 Action"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Operation Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Clock Enable"] + #[inline(always)] + pub fn cen(&self) -> CEN_R { + CEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - BOD33 Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - BOD33 Action"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Operation Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 9 - Clock Enable"] + #[inline(always)] + pub fn cen(&mut self) -> CEN_W { + CEN_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - BOD33 Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "3.3V Brown-Out Detector (BOD33) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bod33](index.html) module"] +pub struct BOD33_SPEC; +impl crate::RegisterSpec for BOD33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bod33::R](R) reader structure"] +impl crate::Readable for BOD33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bod33::W](W) writer structure"] +impl crate::Writable for BOD33_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BOD33 to value 0"] +impl crate::Resettable for BOD33_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dfllctrl.rs b/pac/atsamda1j/src/sysctrl/dfllctrl.rs new file mode 100644 index 00000000000..0e0c6d5be2b --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dfllctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `DFLLCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - DFLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - DFLL Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MODE` reader - Operating Mode Selection"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode Selection"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STABLE` reader - Stable DFLL Frequency"] +pub struct STABLE_R(crate::FieldReader); +impl STABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STABLE` writer - Stable DFLL Frequency"] +pub struct STABLE_W<'a> { + w: &'a mut W, +} +impl<'a> STABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `LLAW` reader - Lose Lock After Wake"] +pub struct LLAW_R(crate::FieldReader); +impl LLAW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LLAW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LLAW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LLAW` writer - Lose Lock After Wake"] +pub struct LLAW_W<'a> { + w: &'a mut W, +} +impl<'a> LLAW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `USBCRM` reader - USB Clock Recovery Mode"] +pub struct USBCRM_R(crate::FieldReader); +impl USBCRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USBCRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USBCRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USBCRM` writer - USB Clock Recovery Mode"] +pub struct USBCRM_W<'a> { + w: &'a mut W, +} +impl<'a> USBCRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CCDIS` reader - Chill Cycle Disable"] +pub struct CCDIS_R(crate::FieldReader); +impl CCDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCDIS` writer - Chill Cycle Disable"] +pub struct CCDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CCDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QLDIS` reader - Quick Lock Disable"] +pub struct QLDIS_R(crate::FieldReader); +impl QLDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QLDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QLDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QLDIS` writer - Quick Lock Disable"] +pub struct QLDIS_W<'a> { + w: &'a mut W, +} +impl<'a> QLDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BPLCKC` reader - Bypass Coarse Lock"] +pub struct BPLCKC_R(crate::FieldReader); +impl BPLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BPLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BPLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BPLCKC` writer - Bypass Coarse Lock"] +pub struct BPLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> BPLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `WAITLOCK` reader - Wait Lock"] +pub struct WAITLOCK_R(crate::FieldReader); +impl WAITLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITLOCK` writer - Wait Lock"] +pub struct WAITLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WAITLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + pub fn stable(&self) -> STABLE_R { + STABLE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + pub fn llaw(&self) -> LLAW_R { + LLAW_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + pub fn usbcrm(&self) -> USBCRM_R { + USBCRM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + pub fn ccdis(&self) -> CCDIS_R { + CCDIS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + pub fn qldis(&self) -> QLDIS_R { + QLDIS_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + pub fn bplckc(&self) -> BPLCKC_R { + BPLCKC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + pub fn waitlock(&self) -> WAITLOCK_R { + WAITLOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + pub fn stable(&mut self) -> STABLE_W { + STABLE_W { w: self } + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + pub fn llaw(&mut self) -> LLAW_W { + LLAW_W { w: self } + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + pub fn usbcrm(&mut self) -> USBCRM_W { + USBCRM_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + pub fn ccdis(&mut self) -> CCDIS_W { + CCDIS_W { w: self } + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + pub fn qldis(&mut self) -> QLDIS_W { + QLDIS_W { w: self } + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + pub fn bplckc(&mut self) -> BPLCKC_W { + BPLCKC_W { w: self } + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + pub fn waitlock(&mut self) -> WAITLOCK_W { + WAITLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllctrl](index.html) module"] +pub struct DFLLCTRL_SPEC; +impl crate::RegisterSpec for DFLLCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [dfllctrl::R](R) reader structure"] +impl crate::Readable for DFLLCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllctrl::W](W) writer structure"] +impl crate::Writable for DFLLCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLCTRL to value 0x80"] +impl crate::Resettable for DFLLCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dfllmul.rs b/pac/atsamda1j/src/sysctrl/dfllmul.rs new file mode 100644 index 00000000000..a7f8b3e47ed --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dfllmul.rs @@ -0,0 +1,177 @@ +#[doc = "Register `DFLLMUL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLMUL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MUL` reader - DFLL Multiply Factor"] +pub struct MUL_R(crate::FieldReader); +impl MUL_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MUL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MUL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUL` writer - DFLL Multiply Factor"] +pub struct MUL_W<'a> { + w: &'a mut W, +} +impl<'a> MUL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `FSTEP` reader - Fine Maximum Step"] +pub struct FSTEP_R(crate::FieldReader); +impl FSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FSTEP` writer - Fine Maximum Step"] +pub struct FSTEP_W<'a> { + w: &'a mut W, +} +impl<'a> FSTEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 16)) | ((value as u32 & 0x03ff) << 16); + self.w + } +} +#[doc = "Field `CSTEP` reader - Coarse Maximum Step"] +pub struct CSTEP_R(crate::FieldReader); +impl CSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSTEP` writer - Coarse Maximum Step"] +pub struct CSTEP_W<'a> { + w: &'a mut W, +} +impl<'a> CSTEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + pub fn mul(&self) -> MUL_R { + MUL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + pub fn fstep(&self) -> FSTEP_R { + FSTEP_R::new(((self.bits >> 16) & 0x03ff) as u16) + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + pub fn cstep(&self) -> CSTEP_R { + CSTEP_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + pub fn mul(&mut self) -> MUL_W { + MUL_W { w: self } + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + pub fn fstep(&mut self) -> FSTEP_W { + FSTEP_W { w: self } + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + pub fn cstep(&mut self) -> CSTEP_W { + CSTEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Multiplier\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllmul](index.html) module"] +pub struct DFLLMUL_SPEC; +impl crate::RegisterSpec for DFLLMUL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllmul::R](R) reader structure"] +impl crate::Readable for DFLLMUL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllmul::W](W) writer structure"] +impl crate::Writable for DFLLMUL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLMUL to value 0"] +impl crate::Resettable for DFLLMUL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dfllsync.rs b/pac/atsamda1j/src/sysctrl/dfllsync.rs new file mode 100644 index 00000000000..ab2d44b3a57 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dfllsync.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DFLLSYNC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLSYNC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READREQ` reader - Read Request"] +pub struct READREQ_R(crate::FieldReader); +impl READREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READREQ` writer - Read Request"] +pub struct READREQ_W<'a> { + w: &'a mut W, +} +impl<'a> READREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 7 - Read Request"] + #[inline(always)] + pub fn readreq(&self) -> READREQ_R { + READREQ_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 7 - Read Request"] + #[inline(always)] + pub fn readreq(&mut self) -> READREQ_W { + READREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Synchronization\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllsync](index.html) module"] +pub struct DFLLSYNC_SPEC; +impl crate::RegisterSpec for DFLLSYNC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dfllsync::R](R) reader structure"] +impl crate::Readable for DFLLSYNC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllsync::W](W) writer structure"] +impl crate::Writable for DFLLSYNC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLSYNC to value 0"] +impl crate::Resettable for DFLLSYNC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dfllval.rs b/pac/atsamda1j/src/sysctrl/dfllval.rs new file mode 100644 index 00000000000..9098c660072 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dfllval.rs @@ -0,0 +1,177 @@ +#[doc = "Register `DFLLVAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLVAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FINE` reader - Fine Value"] +pub struct FINE_R(crate::FieldReader); +impl FINE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FINE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FINE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FINE` writer - Fine Value"] +pub struct FINE_W<'a> { + w: &'a mut W, +} +impl<'a> FINE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03ff) | (value as u32 & 0x03ff); + self.w + } +} +#[doc = "Field `COARSE` reader - Coarse Value"] +pub struct COARSE_R(crate::FieldReader); +impl COARSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COARSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COARSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COARSE` writer - Coarse Value"] +pub struct COARSE_W<'a> { + w: &'a mut W, +} +impl<'a> COARSE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 10)) | ((value as u32 & 0x3f) << 10); + self.w + } +} +#[doc = "Field `DIFF` reader - Multiplication Ratio Difference"] +pub struct DIFF_R(crate::FieldReader); +impl DIFF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFF` writer - Multiplication Ratio Difference"] +pub struct DIFF_W<'a> { + w: &'a mut W, +} +impl<'a> DIFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + pub fn fine(&self) -> FINE_R { + FINE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + pub fn coarse(&self) -> COARSE_R { + COARSE_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:31 - Multiplication Ratio Difference"] + #[inline(always)] + pub fn diff(&self) -> DIFF_R { + DIFF_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + pub fn fine(&mut self) -> FINE_W { + FINE_W { w: self } + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + pub fn coarse(&mut self) -> COARSE_W { + COARSE_W { w: self } + } + #[doc = "Bits 16:31 - Multiplication Ratio Difference"] + #[inline(always)] + pub fn diff(&mut self) -> DIFF_W { + DIFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllval](index.html) module"] +pub struct DFLLVAL_SPEC; +impl crate::RegisterSpec for DFLLVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllval::R](R) reader structure"] +impl crate::Readable for DFLLVAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllval::W](W) writer structure"] +impl crate::Writable for DFLLVAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFLLVAL to value 0"] +impl crate::Resettable for DFLLVAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dpllctrla.rs b/pac/atsamda1j/src/sysctrl/dpllctrla.rs new file mode 100644 index 00000000000..c0600c21f16 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - DPLL Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Clock Activation"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Clock Activation"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Clock Activation"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - DPLL Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Clock Activation"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dpllctrlb.rs b/pac/atsamda1j/src/sysctrl/dpllctrlb.rs new file mode 100644 index 00000000000..968579fc693 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: CLK_DPLL_REF0 clock reference"] + REF0 = 0, + #[doc = "1: CLK_DPLL_REF1 clock reference"] + REF1 = 1, + #[doc = "2: GCLK_DPLL clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::REF0), + 1 => Some(REFCLK_A::REF1), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `REF0`"] + #[inline(always)] + pub fn is_ref0(&self) -> bool { + **self == REFCLK_A::REF0 + } + #[doc = "Checks if the value of the field is `REF1`"] + #[inline(always)] + pub fn is_ref1(&self) -> bool { + **self == REFCLK_A::REF1 + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_DPLL_REF0 clock reference"] + #[inline(always)] + pub fn ref0(self) -> &'a mut W { + self.variant(REFCLK_A::REF0) + } + #[doc = "CLK_DPLL_REF1 clock reference"] + #[inline(always)] + pub fn ref1(self) -> &'a mut W { + self.variant(REFCLK_A::REF1) + } + #[doc = "GCLK_DPLL clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out"] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8 ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9 ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10 ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11 ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8 ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9 ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10 ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11 ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dpllratio.rs b/pac/atsamda1j/src/sysctrl/dpllratio.rs new file mode 100644 index 00000000000..93b39e30f1a --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/dpllstatus.rs b/pac/atsamda1j/src/sysctrl/dpllstatus.rs new file mode 100644 index 00000000000..70499131cff --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/dpllstatus.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - Output Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` reader - Divider Enable"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Divider Enable"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/intenclr.rs b/pac/atsamda1j/src/sysctrl/intenclr.rs new file mode 100644 index 00000000000..bf0a746e23a --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/intenclr.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/intenset.rs b/pac/atsamda1j/src/sysctrl/intenset.rs new file mode 100644 index 00000000000..39276ad4015 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/intenset.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready Interrupt Enable"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready Interrupt Enable"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection Interrupt Enable"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready Interrupt Enable"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/intflag.rs b/pac/atsamda1j/src/sysctrl/intflag.rs new file mode 100644 index 00000000000..0902e3120a1 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/intflag.rs @@ -0,0 +1,771 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` writer - OSC8M Ready"] +pub struct OSC8MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC8MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` writer - DFLL Ready"] +pub struct DFLLRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds"] +pub struct DFLLOOB_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLOOB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine"] +pub struct DFLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse"] +pub struct DFLLLCKC_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLLCKC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_W<'a> { + w: &'a mut W, +} +impl<'a> DFLLRCS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` writer - BOD33 Ready"] +pub struct BOD33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` writer - BOD33 Detection"] +pub struct BOD33DET_W<'a> { + w: &'a mut W, +} +impl<'a> BOD33DET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"] +pub struct B33SRDY_W<'a> { + w: &'a mut W, +} +impl<'a> B33SRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&mut self) -> OSC8MRDY_W { + OSC8MRDY_W { w: self } + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&mut self) -> DFLLRDY_W { + DFLLRDY_W { w: self } + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&mut self) -> DFLLOOB_W { + DFLLOOB_W { w: self } + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&mut self) -> DFLLLCKF_W { + DFLLLCKF_W { w: self } + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&mut self) -> DFLLLCKC_W { + DFLLLCKC_W { w: self } + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&mut self) -> DFLLRCS_W { + DFLLRCS_W { w: self } + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&mut self) -> BOD33RDY_W { + BOD33RDY_W { w: self } + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&mut self) -> BOD33DET_W { + BOD33DET_W { w: self } + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&mut self) -> B33SRDY_W { + B33SRDY_W { w: self } + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/osc32k.rs b/pac/atsamda1j/src/sysctrl/osc32k.rs new file mode 100644 index 00000000000..aa32cb287aa --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamda1j/src/sysctrl/osc8m.rs b/pac/atsamda1j/src/sysctrl/osc8m.rs new file mode 100644 index 00000000000..24f058d3ed1 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/osc8m.rs @@ -0,0 +1,468 @@ +#[doc = "Register `OSC8M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC8M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Prescaler\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: `0`"] + _0 = 0, + #[doc = "1: `1`"] + _1 = 1, + #[doc = "2: `10`"] + _2 = 2, + #[doc = "3: `11`"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Oscillator Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESC_A { + match self.bits { + 0 => PRESC_A::_0, + 1 => PRESC_A::_1, + 2 => PRESC_A::_2, + 3 => PRESC_A::_3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PRESC_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PRESC_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PRESC_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PRESC_A::_3 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Oscillator Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(PRESC_A::_0) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(PRESC_A::_1) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(PRESC_A::_2) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(PRESC_A::_3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 16)) | ((value as u32 & 0x0fff) << 16); + self.w + } +} +#[doc = "Oscillator Frequency Range\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FRANGE_A { + #[doc = "0: 4 to 6MHz"] + _0 = 0, + #[doc = "1: 6 to 8MHz"] + _1 = 1, + #[doc = "2: 8 to 11MHz"] + _2 = 2, + #[doc = "3: 11 to 15MHz"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FRANGE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FRANGE` reader - Oscillator Frequency Range"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FRANGE_A { + match self.bits { + 0 => FRANGE_A::_0, + 1 => FRANGE_A::_1, + 2 => FRANGE_A::_2, + 3 => FRANGE_A::_3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FRANGE_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FRANGE_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FRANGE_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == FRANGE_A::_3 + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Oscillator Frequency Range"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FRANGE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "4 to 6MHz"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(FRANGE_A::_0) + } + #[doc = "6 to 8MHz"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(FRANGE_A::_1) + } + #[doc = "8 to 11MHz"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(FRANGE_A::_2) + } + #[doc = "11 to 15MHz"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(FRANGE_A::_3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Oscillator Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:27 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x0fff) as u16) + } + #[doc = "Bits 30:31 - Oscillator Frequency Range"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:9 - Oscillator Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Bits 16:27 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bits 30:31 - Oscillator Frequency Range"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "8MHz Internal Oscillator (OSC8M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc8m](index.html) module"] +pub struct OSC8M_SPEC; +impl crate::RegisterSpec for OSC8M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc8m::R](R) reader structure"] +impl crate::Readable for OSC8M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc8m::W](W) writer structure"] +impl crate::Writable for OSC8M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC8M to value 0x8707_0382"] +impl crate::Resettable for OSC8M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8707_0382 + } +} diff --git a/pac/atsamda1j/src/sysctrl/osculp32k.rs b/pac/atsamda1j/src/sysctrl/osculp32k.rs new file mode 100644 index 00000000000..b7baa4236c5 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u8 & 0x1f); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0x1f"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1f + } +} diff --git a/pac/atsamda1j/src/sysctrl/pclksr.rs b/pac/atsamda1j/src/sysctrl/pclksr.rs new file mode 100644 index 00000000000..0298891e5f6 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/pclksr.rs @@ -0,0 +1,333 @@ +#[doc = "Register `PCLKSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC8MRDY` reader - OSC8M Ready"] +pub struct OSC8MRDY_R(crate::FieldReader); +impl OSC8MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC8MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC8MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub struct DFLLRDY_R(crate::FieldReader); +impl DFLLRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub struct DFLLOOB_R(crate::FieldReader); +impl DFLLOOB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLOOB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLOOB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub struct DFLLLCKF_R(crate::FieldReader); +impl DFLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub struct DFLLLCKC_R(crate::FieldReader); +impl DFLLLCKC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLLCKC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLLCKC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub struct DFLLRCS_R(crate::FieldReader); +impl DFLLRCS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFLLRCS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFLLRCS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub struct BOD33RDY_R(crate::FieldReader); +impl BOD33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub struct BOD33DET_R(crate::FieldReader); +impl BOD33DET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOD33DET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOD33DET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub struct B33SRDY_R(crate::FieldReader); +impl B33SRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + B33SRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for B33SRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - OSC8M Ready"] + #[inline(always)] + pub fn osc8mrdy(&self) -> OSC8MRDY_R { + OSC8MRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - DPLL Lock Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pclksr](index.html) module"] +pub struct PCLKSR_SPEC; +impl crate::RegisterSpec for PCLKSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pclksr::R](R) reader structure"] +impl crate::Readable for PCLKSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PCLKSR to value 0"] +impl crate::Resettable for PCLKSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/vref.rs b/pac/atsamda1j/src/sysctrl/vref.rs new file mode 100644 index 00000000000..ecdfa1cc05a --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/vref.rs @@ -0,0 +1,197 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BGOUTEN` reader - Bandgap Output Enable"] +pub struct BGOUTEN_R(crate::FieldReader); +impl BGOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BGOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BGOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BGOUTEN` writer - Bandgap Output Enable"] +pub struct BGOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> BGOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CALIB` reader - Bandgap Voltage Generator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Bandgap Voltage Generator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bandgap Output Enable"] + #[inline(always)] + pub fn bgouten(&self) -> BGOUTEN_R { + BGOUTEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Bandgap Voltage Generator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Bandgap Output Enable"] + #[inline(always)] + pub fn bgouten(&mut self) -> BGOUTEN_W { + BGOUTEN_W { w: self } + } + #[doc = "Bits 16:26 - Bandgap Voltage Generator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Voltage References System (VREF) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/vreg.rs b/pac/atsamda1j/src/sysctrl/vreg.rs new file mode 100644 index 00000000000..42de242a11c --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `FORCELDO` reader - Force LDO Voltage Regulator"] +pub struct FORCELDO_R(crate::FieldReader); +impl FORCELDO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FORCELDO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FORCELDO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORCELDO` writer - Force LDO Voltage Regulator"] +pub struct FORCELDO_W<'a> { + w: &'a mut W, +} +impl<'a> FORCELDO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 13 - Force LDO Voltage Regulator"] + #[inline(always)] + pub fn forceldo(&self) -> FORCELDO_R { + FORCELDO_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 13 - Force LDO Voltage Regulator"] + #[inline(always)] + pub fn forceldo(&mut self) -> FORCELDO_W { + FORCELDO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Voltage Regulator System (VREG) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/sysctrl/xosc.rs b/pac/atsamda1j/src/sysctrl/xosc.rs new file mode 100644 index 00000000000..d1237a54e28 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/xosc.rs @@ -0,0 +1,694 @@ +#[doc = "Register `XOSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2MHz"] + _0 = 0, + #[doc = "1: 4MHz"] + _1 = 1, + #[doc = "2: 8MHz"] + _2 = 2, + #[doc = "3: 16MHz"] + _3 = 3, + #[doc = "4: 30MHz"] + _4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::_0), + 1 => Some(GAIN_A::_1), + 2 => Some(GAIN_A::_2), + 3 => Some(GAIN_A::_3), + 4 => Some(GAIN_A::_4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == GAIN_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == GAIN_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == GAIN_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == GAIN_A::_3 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == GAIN_A::_4 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2MHz"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(GAIN_A::_0) + } + #[doc = "4MHz"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(GAIN_A::_1) + } + #[doc = "8MHz"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(GAIN_A::_2) + } + #[doc = "16MHz"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(GAIN_A::_3) + } + #[doc = "30MHz"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(GAIN_A::_4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc](index.html) module"] +pub struct XOSC_SPEC; +impl crate::RegisterSpec for XOSC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc::R](R) reader structure"] +impl crate::Readable for XOSC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc::W](W) writer structure"] +impl crate::Writable for XOSC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC to value 0x80"] +impl crate::Resettable for XOSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1j/src/sysctrl/xosc32k.rs b/pac/atsamda1j/src/sysctrl/xosc32k.rs new file mode 100644 index 00000000000..6a13602dfc9 --- /dev/null +++ b/pac/atsamda1j/src/sysctrl/xosc32k.rs @@ -0,0 +1,606 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `AAMPEN` reader - Automatic Amplitude Control Enable"] +pub struct AAMPEN_R(crate::FieldReader); +impl AAMPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AAMPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AAMPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AAMPEN` writer - Automatic Amplitude Control Enable"] +pub struct AAMPEN_W<'a> { + w: &'a mut W, +} +impl<'a> AAMPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.592 ms"] + CYCLE2048 = 2, + #[doc = "3: 125.092 ms"] + CYCLE4096 = 3, + #[doc = "4: 500.092 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000.092 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000.092 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000.092 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.592 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125.092 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500.092 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000.092 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000.092 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000.092 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Automatic Amplitude Control Enable"] + #[inline(always)] + pub fn aampen(&self) -> AAMPEN_R { + AAMPEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 5 - Automatic Amplitude Control Enable"] + #[inline(always)] + pub fn aampen(&mut self) -> AAMPEN_W { + AAMPEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamda1j/src/system_control.rs b/pac/atsamda1j/src/system_control.rs new file mode 100644 index 00000000000..4894b22b258 --- /dev/null +++ b/pac/atsamda1j/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamda1j/src/system_control/aircr.rs b/pac/atsamda1j/src/system_control/aircr.rs new file mode 100644 index 00000000000..9453cc6f30b --- /dev/null +++ b/pac/atsamda1j/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/system_control/ccr.rs b/pac/atsamda1j/src/system_control/ccr.rs new file mode 100644 index 00000000000..62516a7b60c --- /dev/null +++ b/pac/atsamda1j/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamda1j/src/system_control/cpuid.rs b/pac/atsamda1j/src/system_control/cpuid.rs new file mode 100644 index 00000000000..4157d7a94e9 --- /dev/null +++ b/pac/atsamda1j/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamda1j/src/system_control/dfsr.rs b/pac/atsamda1j/src/system_control/dfsr.rs new file mode 100644 index 00000000000..948899af090 --- /dev/null +++ b/pac/atsamda1j/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/system_control/icsr.rs b/pac/atsamda1j/src/system_control/icsr.rs new file mode 100644 index 00000000000..7fe5fd41211 --- /dev/null +++ b/pac/atsamda1j/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/system_control/scr.rs b/pac/atsamda1j/src/system_control/scr.rs new file mode 100644 index 00000000000..db9c54fe6f6 --- /dev/null +++ b/pac/atsamda1j/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/system_control/shcsr.rs b/pac/atsamda1j/src/system_control/shcsr.rs new file mode 100644 index 00000000000..bfba26ac06a --- /dev/null +++ b/pac/atsamda1j/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/system_control/shpr2.rs b/pac/atsamda1j/src/system_control/shpr2.rs new file mode 100644 index 00000000000..5665d6a5e8a --- /dev/null +++ b/pac/atsamda1j/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/system_control/shpr3.rs b/pac/atsamda1j/src/system_control/shpr3.rs new file mode 100644 index 00000000000..cb5a92c5350 --- /dev/null +++ b/pac/atsamda1j/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/system_control/vtor.rs b/pac/atsamda1j/src/system_control/vtor.rs new file mode 100644 index 00000000000..0ee4c781781 --- /dev/null +++ b/pac/atsamda1j/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3.rs b/pac/atsamda1j/src/tc3.rs new file mode 100644 index 00000000000..6465deb3413 --- /dev/null +++ b/pac/atsamda1j/src/tc3.rs @@ -0,0 +1,133 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x20], +} +impl RegisterBlock { + #[doc = "0x00..0x20 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x1c - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x1a - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT8 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x14 - COUNT8 Period Value"] + pub per: crate::Reg, + _reserved13: [u8; 0x03], + #[doc = "0x18 - COUNT8 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT16 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x06], + #[doc = "0x18 - COUNT16 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x02 - Read Request"] + pub readreq: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Control C"] + pub ctrlc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x08 - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x0a - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0d - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0e - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0f - Status"] + pub status: crate::Reg, + #[doc = "0x10 - COUNT32 Counter Value"] + pub count: crate::Reg, + _reserved12: [u8; 0x04], + #[doc = "0x18..0x20 - COUNT32 Compare/Capture"] + pub cc: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamda1j/src/tc3/count16.rs b/pac/atsamda1j/src/tc3/count16.rs new file mode 100644 index 00000000000..c184879d148 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16.rs @@ -0,0 +1,52 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Counter Value"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1j/src/tc3/count16/cc.rs b/pac/atsamda1j/src/tc3/count16/cc.rs new file mode 100644 index 00000000000..ca78398c970 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/count.rs b/pac/atsamda1j/src/tc3/count16/count.rs new file mode 100644 index 00000000000..421dff4311a --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Count Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Count Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Count Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Count Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/ctrla.rs b/pac/atsamda1j/src/tc3/count16/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/ctrlbclr.rs b/pac/atsamda1j/src/tc3/count16/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/ctrlbset.rs b/pac/atsamda1j/src/tc3/count16/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/ctrlc.rs b/pac/atsamda1j/src/tc3/count16/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/dbgctrl.rs b/pac/atsamda1j/src/tc3/count16/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/evctrl.rs b/pac/atsamda1j/src/tc3/count16/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/intenclr.rs b/pac/atsamda1j/src/tc3/count16/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/intenset.rs b/pac/atsamda1j/src/tc3/count16/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/intflag.rs b/pac/atsamda1j/src/tc3/count16/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/readreq.rs b/pac/atsamda1j/src/tc3/count16/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count16/status.rs b/pac/atsamda1j/src/tc3/count16/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count16/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1j/src/tc3/count32.rs b/pac/atsamda1j/src/tc3/count32.rs new file mode 100644 index 00000000000..aeb206f527b --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32.rs @@ -0,0 +1,52 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Counter Value"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1j/src/tc3/count32/cc.rs b/pac/atsamda1j/src/tc3/count32/cc.rs new file mode 100644 index 00000000000..d9cafa8cf2a --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/count.rs b/pac/atsamda1j/src/tc3/count32/count.rs new file mode 100644 index 00000000000..80e47741321 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Count Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Count Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Count Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Count Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/ctrla.rs b/pac/atsamda1j/src/tc3/count32/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/ctrlbclr.rs b/pac/atsamda1j/src/tc3/count32/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/ctrlbset.rs b/pac/atsamda1j/src/tc3/count32/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/ctrlc.rs b/pac/atsamda1j/src/tc3/count32/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/dbgctrl.rs b/pac/atsamda1j/src/tc3/count32/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/evctrl.rs b/pac/atsamda1j/src/tc3/count32/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/intenclr.rs b/pac/atsamda1j/src/tc3/count32/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/intenset.rs b/pac/atsamda1j/src/tc3/count32/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/intflag.rs b/pac/atsamda1j/src/tc3/count32/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/readreq.rs b/pac/atsamda1j/src/tc3/count32/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count32/status.rs b/pac/atsamda1j/src/tc3/count32/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count32/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1j/src/tc3/count8.rs b/pac/atsamda1j/src/tc3/count8.rs new file mode 100644 index 00000000000..c25911542ec --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8.rs @@ -0,0 +1,56 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "READREQ register accessor: an alias for `Reg`"] +pub type READREQ = crate::Reg; +#[doc = "Read Request"] +pub mod readreq; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period Value"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare/Capture"] +pub mod cc; diff --git a/pac/atsamda1j/src/tc3/count8/cc.rs b/pac/atsamda1j/src/tc3/count8/cc.rs new file mode 100644 index 00000000000..02ab7eb2bf7 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare/Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/count.rs b/pac/atsamda1j/src/tc3/count8/count.rs new file mode 100644 index 00000000000..203d066a2e2 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/ctrla.rs b/pac/atsamda1j/src/tc3/count8/ctrla.rs new file mode 100644 index 00000000000..d54098ca9b3 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/ctrla.rs @@ -0,0 +1,681 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "TC Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - TC Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - TC Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Waveform Generation Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: `0`"] + NFRQ = 0, + #[doc = "1: `1`"] + MFRQ = 1, + #[doc = "2: `10`"] + NPWM = 2, + #[doc = "3: `11`"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "`0`"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "`1`"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "`10`"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "`11`"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u16 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - TC Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 5:6 - Waveform Generation Operation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/ctrlbclr.rs b/pac/atsamda1j/src/tc3/count8/ctrlbclr.rs new file mode 100644 index 00000000000..cd1cb53b621 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/ctrlbclr.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0x02"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/ctrlbset.rs b/pac/atsamda1j/src/tc3/count8/ctrlbset.rs new file mode 100644 index 00000000000..bbb5f014932 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/ctrlbset.rs @@ -0,0 +1,259 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 6:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/ctrlc.rs b/pac/atsamda1j/src/tc3/count8/ctrlc.rs new file mode 100644 index 00000000000..beae5c9d4b2 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/ctrlc.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform 0 Invert Enable"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform 1 Invert Enable"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 4 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 5 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/dbgctrl.rs b/pac/atsamda1j/src/tc3/count8/dbgctrl.rs new file mode 100644 index 00000000000..c2255596f92 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/evctrl.rs b/pac/atsamda1j/src/tc3/count8/evctrl.rs new file mode 100644 index 00000000000..c2f2ec9cd28 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/evctrl.rs @@ -0,0 +1,439 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "5: Period captured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period captured in CC1, pulse width in CC0"] + PWP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::OFF), + 1 => Some(EVACT_A::RETRIGGER), + 2 => Some(EVACT_A::COUNT), + 3 => Some(EVACT_A::START), + 5 => Some(EVACT_A::PPW), + 6 => Some(EVACT_A::PWP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Period captured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period captured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Inverted Event Input"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Inverted Event Input"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Input"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Input"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Inverted Event Input"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Input"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/intenclr.rs b/pac/atsamda1j/src/tc3/count8/intenclr.rs new file mode 100644 index 00000000000..e37bf2e610b --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/intenset.rs b/pac/atsamda1j/src/tc3/count8/intenset.rs new file mode 100644 index 00000000000..13f971963ec --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready Interrupt Enable"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/intflag.rs b/pac/atsamda1j/src/tc3/count8/intflag.rs new file mode 100644 index 00000000000..f638593e86a --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYNCRDY` reader - Synchronization Ready"] +pub struct SYNCRDY_R(crate::FieldReader); +impl SYNCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCRDY` writer - Synchronization Ready"] +pub struct SYNCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> SYNCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&self) -> SYNCRDY_R { + SYNCRDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 3 - Synchronization Ready"] + #[inline(always)] + pub fn syncrdy(&mut self) -> SYNCRDY_W { + SYNCRDY_W { w: self } + } + #[doc = "Bit 4 - Match or Capture Channel 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - Match or Capture Channel 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/per.rs b/pac/atsamda1j/src/tc3/count8/per.rs new file mode 100644 index 00000000000..27a157b4646 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamda1j/src/tc3/count8/readreq.rs b/pac/atsamda1j/src/tc3/count8/readreq.rs new file mode 100644 index 00000000000..921b0d9f823 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/readreq.rs @@ -0,0 +1,197 @@ +#[doc = "Register `READREQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `READREQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `RCONT` reader - Read Continuously"] +pub struct RCONT_R(crate::FieldReader); +impl RCONT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCONT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCONT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCONT` writer - Read Continuously"] +pub struct RCONT_W<'a> { + w: &'a mut W, +} +impl<'a> RCONT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RREQ` reader - Read Request"] +pub struct RREQ_R(crate::FieldReader); +impl RREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RREQ` writer - Read Request"] +pub struct RREQ_W<'a> { + w: &'a mut W, +} +impl<'a> RREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&self) -> RCONT_R { + RCONT_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&self) -> RREQ_R { + RREQ_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 14 - Read Continuously"] + #[inline(always)] + pub fn rcont(&mut self) -> RCONT_W { + RCONT_W { w: self } + } + #[doc = "Bit 15 - Read Request"] + #[inline(always)] + pub fn rreq(&mut self) -> RREQ_W { + RREQ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Read Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readreq](index.html) module"] +pub struct READREQ_SPEC; +impl crate::RegisterSpec for READREQ_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [readreq::R](R) reader structure"] +impl crate::Readable for READREQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [readreq::W](W) writer structure"] +impl crate::Writable for READREQ_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets READREQ to value 0"] +impl crate::Resettable for READREQ_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tc3/count8/status.rs b/pac/atsamda1j/src/tc3/count8/status.rs new file mode 100644 index 00000000000..338a4a4d2a9 --- /dev/null +++ b/pac/atsamda1j/src/tc3/count8/status.rs @@ -0,0 +1,93 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x08"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/pac/atsamda1j/src/tcc0.rs b/pac/atsamda1j/src/tcc0.rs new file mode 100644 index 00000000000..32249343331 --- /dev/null +++ b/pac/atsamda1j/src/tcc0.rs @@ -0,0 +1,365 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattb: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x68 - Waveform Control Buffer"] + pub waveb: crate::Reg, + _reserved_21_perb: [u8; 0x04], + _reserved_22_ccb: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perb(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccb(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTB register accessor: an alias for `Reg`"] +pub type PATTB = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattb; +#[doc = "WAVEB register accessor: an alias for `Reg`"] +pub type WAVEB = crate::Reg; +#[doc = "Waveform Control Buffer"] +pub mod waveb; +#[doc = "PERB register accessor: an alias for `Reg`"] +pub type PERB = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb; +#[doc = "PERB_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith4_mode; +#[doc = "PERB_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith5_mode; +#[doc = "PERB_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERB_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perb_dith6_mode; +#[doc = "CCB register accessor: an alias for `Reg`"] +pub type CCB = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb; +#[doc = "CCB_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith4_mode; +#[doc = "CCB_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith5_mode; +#[doc = "CCB_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCB_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccb_dith6_mode; diff --git a/pac/atsamda1j/src/tcc0/cc.rs b/pac/atsamda1j/src/tcc0/cc.rs new file mode 100644 index 00000000000..c4d6df7a9a2 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/cc_dith4_mode.rs b/pac/atsamda1j/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 00000000000..f386ab1bdd8 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/cc_dith5_mode.rs b/pac/atsamda1j/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 00000000000..88749a75cb3 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/cc_dith6_mode.rs b/pac/atsamda1j/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 00000000000..a315f193152 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/ccb.rs b/pac/atsamda1j/src/tcc0/ccb.rs new file mode 100644 index 00000000000..3ccab84b34c --- /dev/null +++ b/pac/atsamda1j/src/tcc0/ccb.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCB[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb](index.html) module"] +pub struct CCB_SPEC; +impl crate::RegisterSpec for CCB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb::R](R) reader structure"] +impl crate::Readable for CCB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb::W](W) writer structure"] +impl crate::Writable for CCB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB[%s] +to value 0"] +impl crate::Resettable for CCB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/ccb_dith4_mode.rs b/pac/atsamda1j/src/tcc0/ccb_dith4_mode.rs new file mode 100644 index 00000000000..bece549a8d7 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/ccb_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith4_mode](index.html) module"] +pub struct CCB_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/ccb_dith5_mode.rs b/pac/atsamda1j/src/tcc0/ccb_dith5_mode.rs new file mode 100644 index 00000000000..71235fa105b --- /dev/null +++ b/pac/atsamda1j/src/tcc0/ccb_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith5_mode](index.html) module"] +pub struct CCB_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/ccb_dith6_mode.rs b/pac/atsamda1j/src/tcc0/ccb_dith6_mode.rs new file mode 100644 index 00000000000..f7aa63650de --- /dev/null +++ b/pac/atsamda1j/src/tcc0/ccb_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCB_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCB_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCB` reader - Channel Compare/Capture Buffer Value"] +pub struct CCB_R(crate::FieldReader); +impl CCB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB` writer - Channel Compare/Capture Buffer Value"] +pub struct CCB_W<'a> { + w: &'a mut W, +} +impl<'a> CCB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&self) -> CCB_R { + CCB_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccb(&mut self) -> CCB_W { + CCB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccb_dith6_mode](index.html) module"] +pub struct CCB_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCB_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccb_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCB_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccb_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCB_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCB_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCB_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/count.rs b/pac/atsamda1j/src/tcc0/count.rs new file mode 100644 index 00000000000..7628f2c0d5e --- /dev/null +++ b/pac/atsamda1j/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/count_dith4_mode.rs b/pac/atsamda1j/src/tcc0/count_dith4_mode.rs new file mode 100644 index 00000000000..fc058ae5efd --- /dev/null +++ b/pac/atsamda1j/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/count_dith5_mode.rs b/pac/atsamda1j/src/tcc0/count_dith5_mode.rs new file mode 100644 index 00000000000..e66e2031072 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/count_dith6_mode.rs b/pac/atsamda1j/src/tcc0/count_dith6_mode.rs new file mode 100644 index 00000000000..5410fc6c945 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/ctrla.rs b/pac/atsamda1j/src/tcc0/ctrla.rs new file mode 100644 index 00000000000..ce94f627db2 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/ctrla.rs @@ -0,0 +1,817 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/ctrlbclr.rs b/pac/atsamda1j/src/tcc0/ctrlbclr.rs new file mode 100644 index 00000000000..39a196da677 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/ctrlbclr.rs @@ -0,0 +1,444 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update of double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/ctrlbset.rs b/pac/atsamda1j/src/tcc0/ctrlbset.rs new file mode 100644 index 00000000000..a02c4d5e1ee --- /dev/null +++ b/pac/atsamda1j/src/tcc0/ctrlbset.rs @@ -0,0 +1,444 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update of double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/dbgctrl.rs b/pac/atsamda1j/src/tcc0/dbgctrl.rs new file mode 100644 index 00000000000..313ebe3f5c1 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/drvctrl.rs b/pac/atsamda1j/src/tcc0/drvctrl.rs new file mode 100644 index 00000000000..316041e1e3b --- /dev/null +++ b/pac/atsamda1j/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/evctrl.rs b/pac/atsamda1j/src/tcc0/evctrl.rs new file mode 100644 index 00000000000..5eaba702e34 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/evctrl.rs @@ -0,0 +1,1198 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT0_A::OFF), + 1 => Some(EVACT0_A::RETRIGGER), + 2 => Some(EVACT0_A::COUNTEV), + 3 => Some(EVACT0_A::START), + 4 => Some(EVACT0_A::INC), + 5 => Some(EVACT0_A::COUNT), + 7 => Some(EVACT0_A::FAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/fctrla.rs b/pac/atsamda1j/src/tcc0/fctrla.rs new file mode 100644 index 00000000000..e55d54575a4 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/fctrla.rs @@ -0,0 +1,880 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: No blanking applied"] + NONE = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::NONE, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == BLANK_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No blanking applied"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BLANK_A::NONE) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTURE_A::DISABLE), + 1 => Some(CAPTURE_A::CAPT), + 2 => Some(CAPTURE_A::CAPTMIN), + 3 => Some(CAPTURE_A::CAPTMAX), + 4 => Some(CAPTURE_A::LOCMIN), + 5 => Some(CAPTURE_A::LOCMAX), + 6 => Some(CAPTURE_A::DERIV0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/fctrlb.rs b/pac/atsamda1j/src/tcc0/fctrlb.rs new file mode 100644 index 00000000000..2dd88cc1904 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/fctrlb.rs @@ -0,0 +1,880 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: No blanking applied"] + NONE = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::NONE, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == BLANK_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No blanking applied"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BLANK_A::NONE) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTURE_A::DISABLE), + 1 => Some(CAPTURE_A::CAPT), + 2 => Some(CAPTURE_A::CAPTMIN), + 3 => Some(CAPTURE_A::CAPTMAX), + 4 => Some(CAPTURE_A::LOCMIN), + 5 => Some(CAPTURE_A::LOCMAX), + 6 => Some(CAPTURE_A::DERIV0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/intenclr.rs b/pac/atsamda1j/src/tcc0/intenclr.rs new file mode 100644 index 00000000000..bd054b6cbbd --- /dev/null +++ b/pac/atsamda1j/src/tcc0/intenclr.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/intenset.rs b/pac/atsamda1j/src/tcc0/intenset.rs new file mode 100644 index 00000000000..1be03869328 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/intenset.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/intflag.rs b/pac/atsamda1j/src/tcc0/intflag.rs new file mode 100644 index 00000000000..7106718fd29 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/intflag.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/patt.rs b/pac/atsamda1j/src/tcc0/patt.rs new file mode 100644 index 00000000000..ea458642b18 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/pattb.rs b/pac/atsamda1j/src/tcc0/pattb.rs new file mode 100644 index 00000000000..04190b1d35d --- /dev/null +++ b/pac/atsamda1j/src/tcc0/pattb.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattb](index.html) module"] +pub struct PATTB_SPEC; +impl crate::RegisterSpec for PATTB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattb::R](R) reader structure"] +impl crate::Readable for PATTB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattb::W](W) writer structure"] +impl crate::Writable for PATTB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTB to value 0"] +impl crate::Resettable for PATTB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/per.rs b/pac/atsamda1j/src/tcc0/per.rs new file mode 100644 index 00000000000..9d861863165 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/per_dith4_mode.rs b/pac/atsamda1j/src/tcc0/per_dith4_mode.rs new file mode 100644 index 00000000000..6e8d857e483 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/per_dith5_mode.rs b/pac/atsamda1j/src/tcc0/per_dith5_mode.rs new file mode 100644 index 00000000000..06337b7b91c --- /dev/null +++ b/pac/atsamda1j/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/per_dith6_mode.rs b/pac/atsamda1j/src/tcc0/per_dith6_mode.rs new file mode 100644 index 00000000000..fcbe0f6e31c --- /dev/null +++ b/pac/atsamda1j/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCY` reader - Dithering Cycle Number"] +pub struct DITHERCY_R(crate::FieldReader); +impl DITHERCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCY` writer - Dithering Cycle Number"] +pub struct DITHERCY_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&self) -> DITHERCY_R { + DITHERCY_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dithercy(&mut self) -> DITHERCY_W { + DITHERCY_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/perb.rs b/pac/atsamda1j/src/tcc0/perb.rs new file mode 100644 index 00000000000..6d3eb30c82d --- /dev/null +++ b/pac/atsamda1j/src/tcc0/perb.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb](index.html) module"] +pub struct PERB_SPEC; +impl crate::RegisterSpec for PERB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb::R](R) reader structure"] +impl crate::Readable for PERB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb::W](W) writer structure"] +impl crate::Writable for PERB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB to value 0xffff_ffff"] +impl crate::Resettable for PERB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/perb_dith4_mode.rs b/pac/atsamda1j/src/tcc0/perb_dith4_mode.rs new file mode 100644 index 00000000000..7781d12d911 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/perb_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith4_mode](index.html) module"] +pub struct PERB_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/perb_dith5_mode.rs b/pac/atsamda1j/src/tcc0/perb_dith5_mode.rs new file mode 100644 index 00000000000..e7364029ce2 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/perb_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith5_mode](index.html) module"] +pub struct PERB_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/perb_dith6_mode.rs b/pac/atsamda1j/src/tcc0/perb_dith6_mode.rs new file mode 100644 index 00000000000..0a780ae5f55 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/perb_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERB_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERB_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERCYB` reader - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_R(crate::FieldReader); +impl DITHERCYB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERCYB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERCYB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERCYB` writer - Dithering Buffer Cycle Number"] +pub struct DITHERCYB_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERCYB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERB` reader - Period Buffer Value"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` writer - Period Buffer Value"] +pub struct PERB_W<'a> { + w: &'a mut W, +} +impl<'a> PERB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&self) -> DITHERCYB_R { + DITHERCYB_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn dithercyb(&mut self) -> DITHERCYB_W { + DITHERCYB_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perb(&mut self) -> PERB_W { + PERB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perb_dith6_mode](index.html) module"] +pub struct PERB_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERB_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perb_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERB_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perb_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERB_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERB_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERB_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamda1j/src/tcc0/status.rs b/pac/atsamda1j/src/tcc0/status.rs new file mode 100644 index 00000000000..15ea2088d08 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBV` reader - Pattern Buffer Valid"] +pub struct PATTBV_R(crate::FieldReader); +impl PATTBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBV` writer - Pattern Buffer Valid"] +pub struct PATTBV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `WAVEBV` reader - Wave Buffer Valid"] +pub struct WAVEBV_R(crate::FieldReader); +impl WAVEBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVEBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVEBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEBV` writer - Wave Buffer Valid"] +pub struct WAVEBV_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PERBV` reader - Period Buffer Valid"] +pub struct PERBV_R(crate::FieldReader); +impl PERBV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBV` writer - Period Buffer Valid"] +pub struct PERBV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBV0_R(crate::FieldReader); +impl CCBV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBV1_R(crate::FieldReader); +impl CCBV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBV2_R(crate::FieldReader); +impl CCBV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBV3_R(crate::FieldReader); +impl CCBV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbv(&self) -> PATTBV_R { + PATTBV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Buffer Valid"] + #[inline(always)] + pub fn wavebv(&self) -> WAVEBV_R { + WAVEBV_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbv(&self) -> PERBV_R { + PERBV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbv0(&self) -> CCBV0_R { + CCBV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbv1(&self) -> CCBV1_R { + CCBV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbv2(&self) -> CCBV2_R { + CCBV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbv3(&self) -> CCBV3_R { + CCBV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbv(&mut self) -> PATTBV_W { + PATTBV_W { w: self } + } + #[doc = "Bit 6 - Wave Buffer Valid"] + #[inline(always)] + pub fn wavebv(&mut self) -> WAVEBV_W { + WAVEBV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbv(&mut self) -> PERBV_W { + PERBV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbv0(&mut self) -> CCBV0_W { + CCBV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbv1(&mut self) -> CCBV1_W { + CCBV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbv2(&mut self) -> CCBV2_W { + CCBV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbv3(&mut self) -> CCBV3_W { + CCBV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1j/src/tcc0/syncbusy.rs b/pac/atsamda1j/src/tcc0/syncbusy.rs new file mode 100644 index 00000000000..92f751789fd --- /dev/null +++ b/pac/atsamda1j/src/tcc0/syncbusy.rs @@ -0,0 +1,413 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTB` reader - Pattern Buffer Busy"] +pub struct PATTB_R(crate::FieldReader); +impl PATTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEB` reader - Wave Buffer Busy"] +pub struct WAVEB_R(crate::FieldReader); +impl WAVEB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVEB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVEB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERB` reader - Period Buffer Busy"] +pub struct PERB_R(crate::FieldReader); +impl PERB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB0` reader - Compare Channel Buffer 0 Busy"] +pub struct CCB0_R(crate::FieldReader); +impl CCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB1` reader - Compare Channel Buffer 1 Busy"] +pub struct CCB1_R(crate::FieldReader); +impl CCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB2` reader - Compare Channel Buffer 2 Busy"] +pub struct CCB2_R(crate::FieldReader); +impl CCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCB3` reader - Compare Channel Buffer 3 Busy"] +pub struct CCB3_R(crate::FieldReader); +impl CCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Pattern Buffer Busy"] + #[inline(always)] + pub fn pattb(&self) -> PATTB_R { + PATTB_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Wave Buffer Busy"] + #[inline(always)] + pub fn waveb(&self) -> WAVEB_R { + WAVEB_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Period Buffer Busy"] + #[inline(always)] + pub fn perb(&self) -> PERB_R { + PERB_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel Buffer 0 Busy"] + #[inline(always)] + pub fn ccb0(&self) -> CCB0_R { + CCB0_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Compare Channel Buffer 1 Busy"] + #[inline(always)] + pub fn ccb1(&self) -> CCB1_R { + CCB1_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Compare Channel Buffer 2 Busy"] + #[inline(always)] + pub fn ccb2(&self) -> CCB2_R { + CCB2_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Compare Channel Buffer 3 Busy"] + #[inline(always)] + pub fn ccb3(&self) -> CCB3_R { + CCB3_R::new(((self.bits >> 22) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/wave.rs b/pac/atsamda1j/src/tcc0/wave.rs new file mode 100644 index 00000000000..30602a3a4c6 --- /dev/null +++ b/pac/atsamda1j/src/tcc0/wave.rs @@ -0,0 +1,927 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RAMP_A::RAMP1), + 1 => Some(RAMP_A::RAMP2A), + 2 => Some(RAMP_A::RAMP2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/waveb.rs b/pac/atsamda1j/src/tcc0/waveb.rs new file mode 100644 index 00000000000..bfad858fc8f --- /dev/null +++ b/pac/atsamda1j/src/tcc0/waveb.rs @@ -0,0 +1,927 @@ +#[doc = "Register `WAVEB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVEB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGENB_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGENB_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGENB` reader - Waveform Generation Buffer"] +pub struct WAVEGENB_R(crate::FieldReader); +impl WAVEGENB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGENB_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGENB_A::NFRQ), + 1 => Some(WAVEGENB_A::MFRQ), + 2 => Some(WAVEGENB_A::NPWM), + 4 => Some(WAVEGENB_A::DSCRITICAL), + 5 => Some(WAVEGENB_A::DSBOTTOM), + 6 => Some(WAVEGENB_A::DSBOTH), + 7 => Some(WAVEGENB_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGENB_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGENB_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGENB_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGENB_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGENB_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGENB_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGENB_A::DSTOP + } +} +impl core::ops::Deref for WAVEGENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGENB` writer - Waveform Generation Buffer"] +pub struct WAVEGENB_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGENB_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGENB_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGENB_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGENB_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGENB_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGENB_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode Buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMPB_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMPB_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMPB` reader - Ramp Mode Buffer"] +pub struct RAMPB_R(crate::FieldReader); +impl RAMPB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMPB_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RAMPB_A::RAMP1), + 1 => Some(RAMPB_A::RAMP2A), + 2 => Some(RAMPB_A::RAMP2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMPB_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMPB_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMPB_A::RAMP2 + } +} +impl core::ops::Deref for RAMPB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPB` writer - Ramp Mode Buffer"] +pub struct RAMPB_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPB_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMPB_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMPB_A::RAMP2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPERENB` reader - Circular Period Enable Buffer"] +pub struct CIPERENB_R(crate::FieldReader); +impl CIPERENB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPERENB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPERENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPERENB` writer - Circular Period Enable Buffer"] +pub struct CIPERENB_W<'a> { + w: &'a mut W, +} +impl<'a> CIPERENB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCENB0` reader - Circular Channel 0 Enable Buffer"] +pub struct CICCENB0_R(crate::FieldReader); +impl CICCENB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB0` writer - Circular Channel 0 Enable Buffer"] +pub struct CICCENB0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCENB1` reader - Circular Channel 1 Enable Buffer"] +pub struct CICCENB1_R(crate::FieldReader); +impl CICCENB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB1` writer - Circular Channel 1 Enable Buffer"] +pub struct CICCENB1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCENB2` reader - Circular Channel 2 Enable Buffer"] +pub struct CICCENB2_R(crate::FieldReader); +impl CICCENB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB2` writer - Circular Channel 2 Enable Buffer"] +pub struct CICCENB2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCENB3` reader - Circular Channel 3 Enable Buffer"] +pub struct CICCENB3_R(crate::FieldReader); +impl CICCENB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCENB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCENB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCENB3` writer - Circular Channel 3 Enable Buffer"] +pub struct CICCENB3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCENB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POLB0` reader - Channel 0 Polarity Buffer"] +pub struct POLB0_R(crate::FieldReader); +impl POLB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB0` writer - Channel 0 Polarity Buffer"] +pub struct POLB0_W<'a> { + w: &'a mut W, +} +impl<'a> POLB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POLB1` reader - Channel 1 Polarity Buffer"] +pub struct POLB1_R(crate::FieldReader); +impl POLB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB1` writer - Channel 1 Polarity Buffer"] +pub struct POLB1_W<'a> { + w: &'a mut W, +} +impl<'a> POLB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POLB2` reader - Channel 2 Polarity Buffer"] +pub struct POLB2_R(crate::FieldReader); +impl POLB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB2` writer - Channel 2 Polarity Buffer"] +pub struct POLB2_W<'a> { + w: &'a mut W, +} +impl<'a> POLB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POLB3` reader - Channel 3 Polarity Buffer"] +pub struct POLB3_R(crate::FieldReader); +impl POLB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POLB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POLB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POLB3` writer - Channel 3 Polarity Buffer"] +pub struct POLB3_W<'a> { + w: &'a mut W, +} +impl<'a> POLB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAPB0` reader - Swap DTI Output Pair 0 Buffer"] +pub struct SWAPB0_R(crate::FieldReader); +impl SWAPB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB0` writer - Swap DTI Output Pair 0 Buffer"] +pub struct SWAPB0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAPB1` reader - Swap DTI Output Pair 1 Buffer"] +pub struct SWAPB1_R(crate::FieldReader); +impl SWAPB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB1` writer - Swap DTI Output Pair 1 Buffer"] +pub struct SWAPB1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAPB2` reader - Swap DTI Output Pair 2 Buffer"] +pub struct SWAPB2_R(crate::FieldReader); +impl SWAPB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB2` writer - Swap DTI Output Pair 2 Buffer"] +pub struct SWAPB2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAPB3` reader - Swap DTI Output Pair 3 Buffer"] +pub struct SWAPB3_R(crate::FieldReader); +impl SWAPB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAPB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAPB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAPB3` writer - Swap DTI Output Pair 3 Buffer"] +pub struct SWAPB3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAPB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation Buffer"] + #[inline(always)] + pub fn wavegenb(&self) -> WAVEGENB_R { + WAVEGENB_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode Buffer"] + #[inline(always)] + pub fn rampb(&self) -> RAMPB_R { + RAMPB_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular Period Enable Buffer"] + #[inline(always)] + pub fn ciperenb(&self) -> CIPERENB_R { + CIPERENB_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable Buffer"] + #[inline(always)] + pub fn ciccenb0(&self) -> CICCENB0_R { + CICCENB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable Buffer"] + #[inline(always)] + pub fn ciccenb1(&self) -> CICCENB1_R { + CICCENB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable Buffer"] + #[inline(always)] + pub fn ciccenb2(&self) -> CICCENB2_R { + CICCENB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable Buffer"] + #[inline(always)] + pub fn ciccenb3(&self) -> CICCENB3_R { + CICCENB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity Buffer"] + #[inline(always)] + pub fn polb0(&self) -> POLB0_R { + POLB0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity Buffer"] + #[inline(always)] + pub fn polb1(&self) -> POLB1_R { + POLB1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity Buffer"] + #[inline(always)] + pub fn polb2(&self) -> POLB2_R { + POLB2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity Buffer"] + #[inline(always)] + pub fn polb3(&self) -> POLB3_R { + POLB3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0 Buffer"] + #[inline(always)] + pub fn swapb0(&self) -> SWAPB0_R { + SWAPB0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1 Buffer"] + #[inline(always)] + pub fn swapb1(&self) -> SWAPB1_R { + SWAPB1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2 Buffer"] + #[inline(always)] + pub fn swapb2(&self) -> SWAPB2_R { + SWAPB2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3 Buffer"] + #[inline(always)] + pub fn swapb3(&self) -> SWAPB3_R { + SWAPB3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation Buffer"] + #[inline(always)] + pub fn wavegenb(&mut self) -> WAVEGENB_W { + WAVEGENB_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode Buffer"] + #[inline(always)] + pub fn rampb(&mut self) -> RAMPB_W { + RAMPB_W { w: self } + } + #[doc = "Bit 7 - Circular Period Enable Buffer"] + #[inline(always)] + pub fn ciperenb(&mut self) -> CIPERENB_W { + CIPERENB_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable Buffer"] + #[inline(always)] + pub fn ciccenb0(&mut self) -> CICCENB0_W { + CICCENB0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable Buffer"] + #[inline(always)] + pub fn ciccenb1(&mut self) -> CICCENB1_W { + CICCENB1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable Buffer"] + #[inline(always)] + pub fn ciccenb2(&mut self) -> CICCENB2_W { + CICCENB2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable Buffer"] + #[inline(always)] + pub fn ciccenb3(&mut self) -> CICCENB3_W { + CICCENB3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity Buffer"] + #[inline(always)] + pub fn polb0(&mut self) -> POLB0_W { + POLB0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity Buffer"] + #[inline(always)] + pub fn polb1(&mut self) -> POLB1_W { + POLB1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity Buffer"] + #[inline(always)] + pub fn polb2(&mut self) -> POLB2_W { + POLB2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity Buffer"] + #[inline(always)] + pub fn polb3(&mut self) -> POLB3_W { + POLB3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0 Buffer"] + #[inline(always)] + pub fn swapb0(&mut self) -> SWAPB0_W { + SWAPB0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1 Buffer"] + #[inline(always)] + pub fn swapb1(&mut self) -> SWAPB1_W { + SWAPB1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2 Buffer"] + #[inline(always)] + pub fn swapb2(&mut self) -> SWAPB2_W { + SWAPB2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3 Buffer"] + #[inline(always)] + pub fn swapb3(&mut self) -> SWAPB3_W { + SWAPB3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [waveb](index.html) module"] +pub struct WAVEB_SPEC; +impl crate::RegisterSpec for WAVEB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [waveb::R](R) reader structure"] +impl crate::Readable for WAVEB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [waveb::W](W) writer structure"] +impl crate::Writable for WAVEB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVEB to value 0"] +impl crate::Resettable for WAVEB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/tcc0/wexctrl.rs b/pac/atsamda1j/src/tcc0/wexctrl.rs new file mode 100644 index 00000000000..8eb0d29cbee --- /dev/null +++ b/pac/atsamda1j/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb.rs b/pac/atsamda1j/src/usb.rs new file mode 100644 index 00000000000..22f33e47394 --- /dev/null +++ b/pac/atsamda1j/src/usb.rs @@ -0,0 +1,155 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_host: [u8; 0x01ea], +} +impl RegisterBlock { + #[doc = "0x00..0x1ea - USB is Host"] + #[inline(always)] + pub fn host(&self) -> &HOST { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const HOST) } + } + #[doc = "0x00..0x1ea - USB is Device"] + #[inline(always)] + pub fn device(&self) -> &DEVICE { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const DEVICE) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct DEVICE { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x03 - USB Quality Of Service"] + pub qosctrl: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - DEVICE Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x0a - DEVICE Device Address"] + pub dadd: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x0c - DEVICE Status"] + pub status: crate::Reg, + #[doc = "0x0d - Finite State Machine Status"] + pub fsmstatus: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x10 - DEVICE Device Frame Number"] + pub fnum: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x14 - DEVICE Device Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x18 - DEVICE Device Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x1c - DEVICE Device Interrupt Flag"] + pub intflag: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x20 - DEVICE End Point Interrupt Summary"] + pub epintsmry: crate::Reg, + _reserved12: [u8; 0x02], + #[doc = "0x24 - Descriptor Address"] + pub descadd: crate::Reg, + #[doc = "0x28 - USB PAD Calibration"] + pub padcal: crate::Reg, + _reserved14: [u8; 0xd6], + #[doc = "0x100..0x10a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint0: self::device::DEVICE_ENDPOINT, + _reserved15: [u8; 0x16], + #[doc = "0x120..0x12a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint1: self::device::DEVICE_ENDPOINT, + _reserved16: [u8; 0x16], + #[doc = "0x140..0x14a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint2: self::device::DEVICE_ENDPOINT, + _reserved17: [u8; 0x16], + #[doc = "0x160..0x16a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint3: self::device::DEVICE_ENDPOINT, + _reserved18: [u8; 0x16], + #[doc = "0x180..0x18a - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint4: self::device::DEVICE_ENDPOINT, + _reserved19: [u8; 0x16], + #[doc = "0x1a0..0x1aa - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint5: self::device::DEVICE_ENDPOINT, + _reserved20: [u8; 0x16], + #[doc = "0x1c0..0x1ca - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint6: self::device::DEVICE_ENDPOINT, + _reserved21: [u8; 0x16], + #[doc = "0x1e0..0x1ea - DEVICE_ENDPOINT\\[%s\\]"] + pub device_endpoint7: self::device::DEVICE_ENDPOINT, +} +#[doc = r"Register block"] +#[doc = "USB is Device"] +pub mod device; +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x03 - USB Quality Of Service"] + pub qosctrl: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - HOST Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x0a - HOST Host Start Of Frame Control"] + pub hsofc: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x0c - HOST Status"] + pub status: crate::Reg, + #[doc = "0x0d - Finite State Machine Status"] + pub fsmstatus: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x10 - HOST Host Frame Number"] + pub fnum: crate::Reg, + #[doc = "0x12 - HOST Host Frame Length"] + pub flenhigh: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x14 - HOST Host Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x18 - HOST Host Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved11: [u8; 0x02], + #[doc = "0x1c - HOST Host Interrupt Flag"] + pub intflag: crate::Reg, + _reserved12: [u8; 0x02], + #[doc = "0x20 - HOST Pipe Interrupt Summary"] + pub pintsmry: crate::Reg, + _reserved13: [u8; 0x02], + #[doc = "0x24 - Descriptor Address"] + pub descadd: crate::Reg, + #[doc = "0x28 - USB PAD Calibration"] + pub padcal: crate::Reg, + _reserved15: [u8; 0xd6], + #[doc = "0x100..0x10a - HOST_PIPE\\[%s\\]"] + pub host_pipe0: self::host::HOST_PIPE, + _reserved16: [u8; 0x16], + #[doc = "0x120..0x12a - HOST_PIPE\\[%s\\]"] + pub host_pipe1: self::host::HOST_PIPE, + _reserved17: [u8; 0x16], + #[doc = "0x140..0x14a - HOST_PIPE\\[%s\\]"] + pub host_pipe2: self::host::HOST_PIPE, + _reserved18: [u8; 0x16], + #[doc = "0x160..0x16a - HOST_PIPE\\[%s\\]"] + pub host_pipe3: self::host::HOST_PIPE, + _reserved19: [u8; 0x16], + #[doc = "0x180..0x18a - HOST_PIPE\\[%s\\]"] + pub host_pipe4: self::host::HOST_PIPE, + _reserved20: [u8; 0x16], + #[doc = "0x1a0..0x1aa - HOST_PIPE\\[%s\\]"] + pub host_pipe5: self::host::HOST_PIPE, + _reserved21: [u8; 0x16], + #[doc = "0x1c0..0x1ca - HOST_PIPE\\[%s\\]"] + pub host_pipe6: self::host::HOST_PIPE, + _reserved22: [u8; 0x16], + #[doc = "0x1e0..0x1ea - HOST_PIPE\\[%s\\]"] + pub host_pipe7: self::host::HOST_PIPE, +} +#[doc = r"Register block"] +#[doc = "USB is Host"] +pub mod host; diff --git a/pac/atsamda1j/src/usb/device.rs b/pac/atsamda1j/src/usb/device.rs new file mode 100644 index 00000000000..e5bbbadc1ca --- /dev/null +++ b/pac/atsamda1j/src/usb/device.rs @@ -0,0 +1,78 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "USB Quality Of Service"] +pub mod qosctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "DEVICE Control B"] +pub mod ctrlb; +#[doc = "DADD register accessor: an alias for `Reg`"] +pub type DADD = crate::Reg; +#[doc = "DEVICE Device Address"] +pub mod dadd; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "DEVICE Status"] +pub mod status; +#[doc = "FSMSTATUS register accessor: an alias for `Reg`"] +pub type FSMSTATUS = crate::Reg; +#[doc = "Finite State Machine Status"] +pub mod fsmstatus; +#[doc = "FNUM register accessor: an alias for `Reg`"] +pub type FNUM = crate::Reg; +#[doc = "DEVICE Device Frame Number"] +pub mod fnum; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "DEVICE Device Interrupt Flag"] +pub mod intflag; +#[doc = "EPINTSMRY register accessor: an alias for `Reg`"] +pub type EPINTSMRY = crate::Reg; +#[doc = "DEVICE End Point Interrupt Summary"] +pub mod epintsmry; +#[doc = "DESCADD register accessor: an alias for `Reg`"] +pub type DESCADD = crate::Reg; +#[doc = "Descriptor Address"] +pub mod descadd; +#[doc = "PADCAL register accessor: an alias for `Reg`"] +pub type PADCAL = crate::Reg; +#[doc = "USB PAD Calibration"] +pub mod padcal; +#[doc = r"Register block"] +#[repr(C)] +pub struct DEVICE_ENDPOINT { + #[doc = "0x00 - DEVICE_ENDPOINT End Point Configuration"] + pub epcfg: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - DEVICE_ENDPOINT End Point Pipe Status Clear"] + pub epstatusclr: crate::Reg, + #[doc = "0x05 - DEVICE_ENDPOINT End Point Pipe Status Set"] + pub epstatusset: crate::Reg, + #[doc = "0x06 - DEVICE_ENDPOINT End Point Pipe Status"] + pub epstatus: crate::Reg, + #[doc = "0x07 - DEVICE_ENDPOINT End Point Interrupt Flag"] + pub epintflag: crate::Reg, + #[doc = "0x08 - DEVICE_ENDPOINT End Point Interrupt Clear Flag"] + pub epintenclr: crate::Reg, + #[doc = "0x09 - DEVICE_ENDPOINT End Point Interrupt Set Flag"] + pub epintenset: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "DEVICE_ENDPOINT\\[%s\\]"] +pub mod device_endpoint; diff --git a/pac/atsamda1j/src/usb/device/ctrla.rs b/pac/atsamda1j/src/usb/device/ctrla.rs new file mode 100644 index 00000000000..f29253092ce --- /dev/null +++ b/pac/atsamda1j/src/usb/device/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby Mode"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby Mode"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Device Mode"] + DEVICE = 0, + #[doc = "1: Host Mode"] + HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::DEVICE, + true => MODE_A::HOST, + } + } + #[doc = "Checks if the value of the field is `DEVICE`"] + #[inline(always)] + pub fn is_device(&self) -> bool { + **self == MODE_A::DEVICE + } + #[doc = "Checks if the value of the field is `HOST`"] + #[inline(always)] + pub fn is_host(&self) -> bool { + **self == MODE_A::HOST + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Device Mode"] + #[inline(always)] + pub fn device(self) -> &'a mut W { + self.variant(MODE_A::DEVICE) + } + #[doc = "Host Mode"] + #[inline(always)] + pub fn host(self) -> &'a mut W { + self.variant(MODE_A::HOST) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/ctrlb.rs b/pac/atsamda1j/src/usb/device/ctrlb.rs new file mode 100644 index 00000000000..8c076e89255 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/ctrlb.rs @@ -0,0 +1,666 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DETACH` reader - Detach"] +pub struct DETACH_R(crate::FieldReader); +impl DETACH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DETACH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DETACH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DETACH` writer - Detach"] +pub struct DETACH_W<'a> { + w: &'a mut W, +} +impl<'a> DETACH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPDCONF_A { + #[doc = "0: FS : Full Speed"] + FS = 0, + #[doc = "1: LS : Low Speed"] + LS = 1, + #[doc = "2: HS : High Speed capable"] + HS = 2, + #[doc = "3: HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + HSTM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPDCONF_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPDCONF` reader - Speed Configuration"] +pub struct SPDCONF_R(crate::FieldReader); +impl SPDCONF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPDCONF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SPDCONF_A { + match self.bits { + 0 => SPDCONF_A::FS, + 1 => SPDCONF_A::LS, + 2 => SPDCONF_A::HS, + 3 => SPDCONF_A::HSTM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPDCONF_A::FS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + **self == SPDCONF_A::LS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + **self == SPDCONF_A::HS + } + #[doc = "Checks if the value of the field is `HSTM`"] + #[inline(always)] + pub fn is_hstm(&self) -> bool { + **self == SPDCONF_A::HSTM + } +} +impl core::ops::Deref for SPDCONF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPDCONF` writer - Speed Configuration"] +pub struct SPDCONF_W<'a> { + w: &'a mut W, +} +impl<'a> SPDCONF_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPDCONF_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "FS : Full Speed"] + #[inline(always)] + pub fn fs(self) -> &'a mut W { + self.variant(SPDCONF_A::FS) + } + #[doc = "LS : Low Speed"] + #[inline(always)] + pub fn ls(self) -> &'a mut W { + self.variant(SPDCONF_A::LS) + } + #[doc = "HS : High Speed capable"] + #[inline(always)] + pub fn hs(self) -> &'a mut W { + self.variant(SPDCONF_A::HS) + } + #[doc = "HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + #[inline(always)] + pub fn hstm(self) -> &'a mut W { + self.variant(SPDCONF_A::HSTM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `NREPLY` reader - No Reply"] +pub struct NREPLY_R(crate::FieldReader); +impl NREPLY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NREPLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NREPLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NREPLY` writer - No Reply"] +pub struct NREPLY_W<'a> { + w: &'a mut W, +} +impl<'a> NREPLY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TSTJ` reader - Test mode J"] +pub struct TSTJ_R(crate::FieldReader); +impl TSTJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTJ` writer - Test mode J"] +pub struct TSTJ_W<'a> { + w: &'a mut W, +} +impl<'a> TSTJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTK` reader - Test mode K"] +pub struct TSTK_R(crate::FieldReader); +impl TSTK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTK` writer - Test mode K"] +pub struct TSTK_W<'a> { + w: &'a mut W, +} +impl<'a> TSTK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TSTPCKT` reader - Test packet mode"] +pub struct TSTPCKT_R(crate::FieldReader); +impl TSTPCKT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTPCKT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTPCKT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTPCKT` writer - Test packet mode"] +pub struct TSTPCKT_W<'a> { + w: &'a mut W, +} +impl<'a> TSTPCKT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPMODE2` reader - Specific Operational Mode"] +pub struct OPMODE2_R(crate::FieldReader); +impl OPMODE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPMODE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPMODE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPMODE2` writer - Specific Operational Mode"] +pub struct OPMODE2_W<'a> { + w: &'a mut W, +} +impl<'a> OPMODE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GNAK` reader - Global NAK"] +pub struct GNAK_R(crate::FieldReader); +impl GNAK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GNAK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GNAK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GNAK` writer - Global NAK"] +pub struct GNAK_W<'a> { + w: &'a mut W, +} +impl<'a> GNAK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Link Power Management Handshake\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LPMHDSK_A { + #[doc = "0: No handshake. LPM is not supported"] + NO = 0, + #[doc = "1: ACK"] + ACK = 1, + #[doc = "2: NYET"] + NYET = 2, + #[doc = "3: STALL"] + STALL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LPMHDSK_A) -> Self { + variant as _ + } +} +#[doc = "Field `LPMHDSK` reader - Link Power Management Handshake"] +pub struct LPMHDSK_R(crate::FieldReader); +impl LPMHDSK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LPMHDSK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LPMHDSK_A { + match self.bits { + 0 => LPMHDSK_A::NO, + 1 => LPMHDSK_A::ACK, + 2 => LPMHDSK_A::NYET, + 3 => LPMHDSK_A::STALL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO`"] + #[inline(always)] + pub fn is_no(&self) -> bool { + **self == LPMHDSK_A::NO + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == LPMHDSK_A::ACK + } + #[doc = "Checks if the value of the field is `NYET`"] + #[inline(always)] + pub fn is_nyet(&self) -> bool { + **self == LPMHDSK_A::NYET + } + #[doc = "Checks if the value of the field is `STALL`"] + #[inline(always)] + pub fn is_stall(&self) -> bool { + **self == LPMHDSK_A::STALL + } +} +impl core::ops::Deref for LPMHDSK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMHDSK` writer - Link Power Management Handshake"] +pub struct LPMHDSK_W<'a> { + w: &'a mut W, +} +impl<'a> LPMHDSK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LPMHDSK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No handshake. LPM is not supported"] + #[inline(always)] + pub fn no(self) -> &'a mut W { + self.variant(LPMHDSK_A::NO) + } + #[doc = "ACK"] + #[inline(always)] + pub fn ack(self) -> &'a mut W { + self.variant(LPMHDSK_A::ACK) + } + #[doc = "NYET"] + #[inline(always)] + pub fn nyet(self) -> &'a mut W { + self.variant(LPMHDSK_A::NYET) + } + #[doc = "STALL"] + #[inline(always)] + pub fn stall(self) -> &'a mut W { + self.variant(LPMHDSK_A::STALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u16 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + pub fn detach(&self) -> DETACH_R { + DETACH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + pub fn spdconf(&self) -> SPDCONF_R { + SPDCONF_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + pub fn nreply(&self) -> NREPLY_R { + NREPLY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&self) -> TSTJ_R { + TSTJ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&self) -> TSTK_R { + TSTK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + pub fn tstpckt(&self) -> TSTPCKT_R { + TSTPCKT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + pub fn opmode2(&self) -> OPMODE2_R { + OPMODE2_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + pub fn gnak(&self) -> GNAK_R { + GNAK_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + pub fn lpmhdsk(&self) -> LPMHDSK_R { + LPMHDSK_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + pub fn detach(&mut self) -> DETACH_W { + DETACH_W { w: self } + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + pub fn spdconf(&mut self) -> SPDCONF_W { + SPDCONF_W { w: self } + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + pub fn nreply(&mut self) -> NREPLY_W { + NREPLY_W { w: self } + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&mut self) -> TSTJ_W { + TSTJ_W { w: self } + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&mut self) -> TSTK_W { + TSTK_W { w: self } + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + pub fn tstpckt(&mut self) -> TSTPCKT_W { + TSTPCKT_W { w: self } + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + pub fn opmode2(&mut self) -> OPMODE2_W { + OPMODE2_W { w: self } + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + pub fn gnak(&mut self) -> GNAK_W { + GNAK_W { w: self } + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + pub fn lpmhdsk(&mut self) -> LPMHDSK_W { + LPMHDSK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x01"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1j/src/usb/device/dadd.rs b/pac/atsamda1j/src/usb/device/dadd.rs new file mode 100644 index 00000000000..36cc57b728b --- /dev/null +++ b/pac/atsamda1j/src/usb/device/dadd.rs @@ -0,0 +1,150 @@ +#[doc = "Register `DADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DADD` reader - Device Address"] +pub struct DADD_R(crate::FieldReader); +impl DADD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DADD` writer - Device Address"] +pub struct DADD_W<'a> { + w: &'a mut W, +} +impl<'a> DADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `ADDEN` reader - Device Address Enable"] +pub struct ADDEN_R(crate::FieldReader); +impl ADDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDEN` writer - Device Address Enable"] +pub struct ADDEN_W<'a> { + w: &'a mut W, +} +impl<'a> ADDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + pub fn dadd(&self) -> DADD_R { + DADD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + pub fn adden(&self) -> ADDEN_R { + ADDEN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + pub fn dadd(&mut self) -> DADD_W { + DADD_W { w: self } + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + pub fn adden(&mut self) -> ADDEN_W { + ADDEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dadd](index.html) module"] +pub struct DADD_SPEC; +impl crate::RegisterSpec for DADD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dadd::R](R) reader structure"] +impl crate::Readable for DADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dadd::W](W) writer structure"] +impl crate::Writable for DADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DADD to value 0"] +impl crate::Resettable for DADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/descadd.rs b/pac/atsamda1j/src/usb/device/descadd.rs new file mode 100644 index 00000000000..9fe18a8dcb2 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/descadd.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DESCADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DESCADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCADD` reader - Descriptor Address Value"] +pub struct DESCADD_R(crate::FieldReader); +impl DESCADD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCADD` writer - Descriptor Address Value"] +pub struct DESCADD_W<'a> { + w: &'a mut W, +} +impl<'a> DESCADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&self) -> DESCADD_R { + DESCADD_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&mut self) -> DESCADD_W { + DESCADD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [descadd](index.html) module"] +pub struct DESCADD_SPEC; +impl crate::RegisterSpec for DESCADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [descadd::R](R) reader structure"] +impl crate::Readable for DESCADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [descadd::W](W) writer structure"] +impl crate::Writable for DESCADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DESCADD to value 0"] +impl crate::Resettable for DESCADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/device_endpoint.rs b/pac/atsamda1j/src/usb/device/device_endpoint.rs new file mode 100644 index 00000000000..b0722149fb9 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint.rs @@ -0,0 +1,28 @@ +#[doc = "EPCFG register accessor: an alias for `Reg`"] +pub type EPCFG = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Configuration"] +pub mod epcfg; +#[doc = "EPSTATUSCLR register accessor: an alias for `Reg`"] +pub type EPSTATUSCLR = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Clear"] +pub mod epstatusclr; +#[doc = "EPSTATUSSET register accessor: an alias for `Reg`"] +pub type EPSTATUSSET = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Set"] +pub mod epstatusset; +#[doc = "EPSTATUS register accessor: an alias for `Reg`"] +pub type EPSTATUS = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Pipe Status"] +pub mod epstatus; +#[doc = "EPINTFLAG register accessor: an alias for `Reg`"] +pub type EPINTFLAG = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Flag"] +pub mod epintflag; +#[doc = "EPINTENCLR register accessor: an alias for `Reg`"] +pub type EPINTENCLR = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Clear Flag"] +pub mod epintenclr; +#[doc = "EPINTENSET register accessor: an alias for `Reg`"] +pub type EPINTENSET = crate::Reg; +#[doc = "DEVICE_ENDPOINT End Point Interrupt Set Flag"] +pub mod epintenset; diff --git a/pac/atsamda1j/src/usb/device/device_endpoint/epcfg.rs b/pac/atsamda1j/src/usb/device/device_endpoint/epcfg.rs new file mode 100644 index 00000000000..08d635693e7 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint/epcfg.rs @@ -0,0 +1,187 @@ +#[doc = "Register `EPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EPTYPE0` reader - End Point Type0"] +pub struct EPTYPE0_R(crate::FieldReader); +impl EPTYPE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EPTYPE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPTYPE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPTYPE0` writer - End Point Type0"] +pub struct EPTYPE0_W<'a> { + w: &'a mut W, +} +impl<'a> EPTYPE0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `EPTYPE1` reader - End Point Type1"] +pub struct EPTYPE1_R(crate::FieldReader); +impl EPTYPE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EPTYPE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPTYPE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPTYPE1` writer - End Point Type1"] +pub struct EPTYPE1_W<'a> { + w: &'a mut W, +} +impl<'a> EPTYPE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +#[doc = "Field `NYETDIS` reader - NYET Token Disable"] +pub struct NYETDIS_R(crate::FieldReader); +impl NYETDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NYETDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NYETDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NYETDIS` writer - NYET Token Disable"] +pub struct NYETDIS_W<'a> { + w: &'a mut W, +} +impl<'a> NYETDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + pub fn eptype0(&self) -> EPTYPE0_R { + EPTYPE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + pub fn eptype1(&self) -> EPTYPE1_R { + EPTYPE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + pub fn nyetdis(&self) -> NYETDIS_R { + NYETDIS_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + pub fn eptype0(&mut self) -> EPTYPE0_W { + EPTYPE0_W { w: self } + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + pub fn eptype1(&mut self) -> EPTYPE1_W { + EPTYPE1_W { w: self } + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + pub fn nyetdis(&mut self) -> NYETDIS_W { + NYETDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epcfg](index.html) module"] +pub struct EPCFG_SPEC; +impl crate::RegisterSpec for EPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epcfg::R](R) reader structure"] +impl crate::Readable for EPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epcfg::W](W) writer structure"] +impl crate::Writable for EPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPCFG to value 0"] +impl crate::Resettable for EPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/device_endpoint/epintenclr.rs b/pac/atsamda1j/src/usb/device/device_endpoint/epintenclr.rs new file mode 100644 index 00000000000..50e8a9188e4 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint/epintenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Disable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Disable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Disable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Disable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Disable"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Disable"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Disable"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Disable"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Disable"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Disable"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/Out Interrupt Disable"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/Out Interrupt Disable"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/Out Interrupt Disable"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/Out Interrupt Disable"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Clear Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenclr](index.html) module"] +pub struct EPINTENCLR_SPEC; +impl crate::RegisterSpec for EPINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenclr::R](R) reader structure"] +impl crate::Readable for EPINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenclr::W](W) writer structure"] +impl crate::Writable for EPINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTENCLR to value 0"] +impl crate::Resettable for EPINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/device_endpoint/epintenset.rs b/pac/atsamda1j/src/usb/device/device_endpoint/epintenset.rs new file mode 100644 index 00000000000..1df6b33a143 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint/epintenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Enable"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Enable"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Enable"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Enable"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Enable"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Enable"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/out Interrupt enable"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/out Interrupt enable"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/out Interrupt enable"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/out Interrupt enable"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Set Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenset](index.html) module"] +pub struct EPINTENSET_SPEC; +impl crate::RegisterSpec for EPINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenset::R](R) reader structure"] +impl crate::Readable for EPINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenset::W](W) writer structure"] +impl crate::Writable for EPINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTENSET to value 0"] +impl crate::Resettable for EPINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/device_endpoint/epintflag.rs b/pac/atsamda1j/src/usb/device/device_endpoint/epintflag.rs new file mode 100644 index 00000000000..8af2f8266fd --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint/epintflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EPINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL0` reader - Error Flow 0"] +pub struct TRFAIL0_R(crate::FieldReader); +impl TRFAIL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL0` writer - Error Flow 0"] +pub struct TRFAIL0_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TRFAIL1` reader - Error Flow 1"] +pub struct TRFAIL1_R(crate::FieldReader); +impl TRFAIL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL1` writer - Error Flow 1"] +pub struct TRFAIL1_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTP` reader - Received Setup"] +pub struct RXSTP_R(crate::FieldReader); +impl RXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTP` writer - Received Setup"] +pub struct RXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL0` reader - Stall 0 In/out"] +pub struct STALL0_R(crate::FieldReader); +impl STALL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL0` writer - Stall 0 In/out"] +pub struct STALL0_W<'a> { + w: &'a mut W, +} +impl<'a> STALL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `STALL1` reader - Stall 1 In/out"] +pub struct STALL1_R(crate::FieldReader); +impl STALL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL1` writer - Stall 1 In/out"] +pub struct STALL1_W<'a> { + w: &'a mut W, +} +impl<'a> STALL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + pub fn trfail0(&mut self) -> TRFAIL0_W { + TRFAIL0_W { w: self } + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + pub fn trfail1(&mut self) -> TRFAIL1_W { + TRFAIL1_W { w: self } + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + pub fn rxstp(&mut self) -> RXSTP_W { + RXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + pub fn stall0(&mut self) -> STALL0_W { + STALL0_W { w: self } + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + pub fn stall1(&mut self) -> STALL1_W { + STALL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintflag](index.html) module"] +pub struct EPINTFLAG_SPEC; +impl crate::RegisterSpec for EPINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintflag::R](R) reader structure"] +impl crate::Readable for EPINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintflag::W](W) writer structure"] +impl crate::Writable for EPINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPINTFLAG to value 0"] +impl crate::Resettable for EPINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/device_endpoint/epstatus.rs b/pac/atsamda1j/src/usb/device/device_endpoint/epstatus.rs new file mode 100644 index 00000000000..e5c544090f1 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint/epstatus.rs @@ -0,0 +1,173 @@ +#[doc = "Register `EPSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DTGLOUT` reader - Data Toggle Out"] +pub struct DTGLOUT_R(crate::FieldReader); +impl DTGLOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGLOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGLOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTGLIN` reader - Data Toggle In"] +pub struct DTGLIN_R(crate::FieldReader); +impl DTGLIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGLIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGLIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURBK` reader - Current Bank"] +pub struct CURBK_R(crate::FieldReader); +impl CURBK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CURBK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURBK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLRQ0` reader - Stall 0 Request"] +pub struct STALLRQ0_R(crate::FieldReader); +impl STALLRQ0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLRQ0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLRQ0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLRQ1` reader - Stall 1 Request"] +pub struct STALLRQ1_R(crate::FieldReader); +impl STALLRQ1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLRQ1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLRQ1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK0RDY` reader - Bank 0 ready"] +pub struct BK0RDY_R(crate::FieldReader); +impl BK0RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK0RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK0RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK1RDY` reader - Bank 1 ready"] +pub struct BK1RDY_R(crate::FieldReader); +impl BK1RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK1RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK1RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Data Toggle Out"] + #[inline(always)] + pub fn dtglout(&self) -> DTGLOUT_R { + DTGLOUT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Toggle In"] + #[inline(always)] + pub fn dtglin(&self) -> DTGLIN_R { + DTGLIN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Current Bank"] + #[inline(always)] + pub fn curbk(&self) -> CURBK_R { + CURBK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Stall 0 Request"] + #[inline(always)] + pub fn stallrq0(&self) -> STALLRQ0_R { + STALLRQ0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall 1 Request"] + #[inline(always)] + pub fn stallrq1(&self) -> STALLRQ1_R { + STALLRQ1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Bank 0 ready"] + #[inline(always)] + pub fn bk0rdy(&self) -> BK0RDY_R { + BK0RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bank 1 ready"] + #[inline(always)] + pub fn bk1rdy(&self) -> BK1RDY_R { + BK1RDY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatus](index.html) module"] +pub struct EPSTATUS_SPEC; +impl crate::RegisterSpec for EPSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epstatus::R](R) reader structure"] +impl crate::Readable for EPSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPSTATUS to value 0"] +impl crate::Resettable for EPSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/device_endpoint/epstatusclr.rs b/pac/atsamda1j/src/usb/device/device_endpoint/epstatusclr.rs new file mode 100644 index 00000000000..1c6a8b11556 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint/epstatusclr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `EPSTATUSCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Clear"] +pub struct DTGLOUT_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DTGLIN` writer - Data Toggle IN Clear"] +pub struct DTGLIN_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CURBK` writer - Curren Bank Clear"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Clear"] +pub struct STALLRQ0_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Clear"] +pub struct STALLRQ1_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Clear"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Clear"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle OUT Clear"] + #[inline(always)] + pub fn dtglout(&mut self) -> DTGLOUT_W { + DTGLOUT_W { w: self } + } + #[doc = "Bit 1 - Data Toggle IN Clear"] + #[inline(always)] + pub fn dtglin(&mut self) -> DTGLIN_W { + DTGLIN_W { w: self } + } + #[doc = "Bit 2 - Curren Bank Clear"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Stall 0 Request Clear"] + #[inline(always)] + pub fn stallrq0(&mut self) -> STALLRQ0_W { + STALLRQ0_W { w: self } + } + #[doc = "Bit 5 - Stall 1 Request Clear"] + #[inline(always)] + pub fn stallrq1(&mut self) -> STALLRQ1_W { + STALLRQ1_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Clear"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Clear"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusclr](index.html) module"] +pub struct EPSTATUSCLR_SPEC; +impl crate::RegisterSpec for EPSTATUSCLR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusclr::W](W) writer structure"] +impl crate::Writable for EPSTATUSCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPSTATUSCLR to value 0"] +impl crate::Resettable for EPSTATUSCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/device_endpoint/epstatusset.rs b/pac/atsamda1j/src/usb/device/device_endpoint/epstatusset.rs new file mode 100644 index 00000000000..a5bfce5a635 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/device_endpoint/epstatusset.rs @@ -0,0 +1,234 @@ +#[doc = "Register `EPSTATUSSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Set"] +pub struct DTGLOUT_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DTGLIN` writer - Data Toggle IN Set"] +pub struct DTGLIN_W<'a> { + w: &'a mut W, +} +impl<'a> DTGLIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CURBK` writer - Current Bank Set"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Set"] +pub struct STALLRQ0_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Set"] +pub struct STALLRQ1_W<'a> { + w: &'a mut W, +} +impl<'a> STALLRQ1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Set"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Set"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle OUT Set"] + #[inline(always)] + pub fn dtglout(&mut self) -> DTGLOUT_W { + DTGLOUT_W { w: self } + } + #[doc = "Bit 1 - Data Toggle IN Set"] + #[inline(always)] + pub fn dtglin(&mut self) -> DTGLIN_W { + DTGLIN_W { w: self } + } + #[doc = "Bit 2 - Current Bank Set"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Stall 0 Request Set"] + #[inline(always)] + pub fn stallrq0(&mut self) -> STALLRQ0_W { + STALLRQ0_W { w: self } + } + #[doc = "Bit 5 - Stall 1 Request Set"] + #[inline(always)] + pub fn stallrq1(&mut self) -> STALLRQ1_W { + STALLRQ1_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Set"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Set"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE_ENDPOINT End Point Pipe Status Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusset](index.html) module"] +pub struct EPSTATUSSET_SPEC; +impl crate::RegisterSpec for EPSTATUSSET_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusset::W](W) writer structure"] +impl crate::Writable for EPSTATUSSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EPSTATUSSET to value 0"] +impl crate::Resettable for EPSTATUSSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/epintsmry.rs b/pac/atsamda1j/src/usb/device/epintsmry.rs new file mode 100644 index 00000000000..9b62c194598 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/epintsmry.rs @@ -0,0 +1,193 @@ +#[doc = "Register `EPINTSMRY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPINT0` reader - End Point 0 Interrupt"] +pub struct EPINT0_R(crate::FieldReader); +impl EPINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT1` reader - End Point 1 Interrupt"] +pub struct EPINT1_R(crate::FieldReader); +impl EPINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT2` reader - End Point 2 Interrupt"] +pub struct EPINT2_R(crate::FieldReader); +impl EPINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT3` reader - End Point 3 Interrupt"] +pub struct EPINT3_R(crate::FieldReader); +impl EPINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT4` reader - End Point 4 Interrupt"] +pub struct EPINT4_R(crate::FieldReader); +impl EPINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT5` reader - End Point 5 Interrupt"] +pub struct EPINT5_R(crate::FieldReader); +impl EPINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT6` reader - End Point 6 Interrupt"] +pub struct EPINT6_R(crate::FieldReader); +impl EPINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT7` reader - End Point 7 Interrupt"] +pub struct EPINT7_R(crate::FieldReader); +impl EPINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - End Point 0 Interrupt"] + #[inline(always)] + pub fn epint0(&self) -> EPINT0_R { + EPINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - End Point 1 Interrupt"] + #[inline(always)] + pub fn epint1(&self) -> EPINT1_R { + EPINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - End Point 2 Interrupt"] + #[inline(always)] + pub fn epint2(&self) -> EPINT2_R { + EPINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End Point 3 Interrupt"] + #[inline(always)] + pub fn epint3(&self) -> EPINT3_R { + EPINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - End Point 4 Interrupt"] + #[inline(always)] + pub fn epint4(&self) -> EPINT4_R { + EPINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Point 5 Interrupt"] + #[inline(always)] + pub fn epint5(&self) -> EPINT5_R { + EPINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - End Point 6 Interrupt"] + #[inline(always)] + pub fn epint6(&self) -> EPINT6_R { + EPINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - End Point 7 Interrupt"] + #[inline(always)] + pub fn epint7(&self) -> EPINT7_R { + EPINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "DEVICE End Point Interrupt Summary\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintsmry](index.html) module"] +pub struct EPINTSMRY_SPEC; +impl crate::RegisterSpec for EPINTSMRY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [epintsmry::R](R) reader structure"] +impl crate::Readable for EPINTSMRY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPINTSMRY to value 0"] +impl crate::Resettable for EPINTSMRY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/fnum.rs b/pac/atsamda1j/src/usb/device/fnum.rs new file mode 100644 index 00000000000..761148868fc --- /dev/null +++ b/pac/atsamda1j/src/usb/device/fnum.rs @@ -0,0 +1,93 @@ +#[doc = "Register `FNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MFNUM` reader - Micro Frame Number"] +pub struct MFNUM_R(crate::FieldReader); +impl MFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNUM` reader - Frame Number"] +pub struct FNUM_R(crate::FieldReader); +impl FNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNCERR` reader - Frame Number CRC Error"] +pub struct FNCERR_R(crate::FieldReader); +impl FNCERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FNCERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNCERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&self) -> MFNUM_R { + MFNUM_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&self) -> FNUM_R { + FNUM_R::new(((self.bits >> 3) & 0x07ff) as u16) + } + #[doc = "Bit 15 - Frame Number CRC Error"] + #[inline(always)] + pub fn fncerr(&self) -> FNCERR_R { + FNCERR_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "DEVICE Device Frame Number\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fnum](index.html) module"] +pub struct FNUM_SPEC; +impl crate::RegisterSpec for FNUM_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [fnum::R](R) reader structure"] +impl crate::Readable for FNUM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FNUM to value 0"] +impl crate::Resettable for FNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/fsmstatus.rs b/pac/atsamda1j/src/usb/device/fsmstatus.rs new file mode 100644 index 00000000000..a89e8172c39 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/fsmstatus.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FSMSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Fine State Machine Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSMSTATE_A { + #[doc = "1: OFF (L3). It corresponds to the powered-off, disconnected, and disabled state"] + OFF = 1, + #[doc = "2: ON (L0). It corresponds to the Idle and Active states"] + ON = 2, + #[doc = "4: SUSPEND (L2)"] + SUSPEND = 4, + #[doc = "8: SLEEP (L1)"] + SLEEP = 8, + #[doc = "16: DNRESUME. Down Stream Resume."] + DNRESUME = 16, + #[doc = "32: UPRESUME. Up Stream Resume."] + UPRESUME = 32, + #[doc = "64: RESET. USB lines Reset."] + RESET = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSMSTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSMSTATE` reader - Fine State Machine Status"] +pub struct FSMSTATE_R(crate::FieldReader); +impl FSMSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSMSTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(FSMSTATE_A::OFF), + 2 => Some(FSMSTATE_A::ON), + 4 => Some(FSMSTATE_A::SUSPEND), + 8 => Some(FSMSTATE_A::SLEEP), + 16 => Some(FSMSTATE_A::DNRESUME), + 32 => Some(FSMSTATE_A::UPRESUME), + 64 => Some(FSMSTATE_A::RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FSMSTATE_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + **self == FSMSTATE_A::ON + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == FSMSTATE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `SLEEP`"] + #[inline(always)] + pub fn is_sleep(&self) -> bool { + **self == FSMSTATE_A::SLEEP + } + #[doc = "Checks if the value of the field is `DNRESUME`"] + #[inline(always)] + pub fn is_dnresume(&self) -> bool { + **self == FSMSTATE_A::DNRESUME + } + #[doc = "Checks if the value of the field is `UPRESUME`"] + #[inline(always)] + pub fn is_upresume(&self) -> bool { + **self == FSMSTATE_A::UPRESUME + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == FSMSTATE_A::RESET + } +} +impl core::ops::Deref for FSMSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Fine State Machine Status"] + #[inline(always)] + pub fn fsmstate(&self) -> FSMSTATE_R { + FSMSTATE_R::new((self.bits & 0x7f) as u8) + } +} +#[doc = "Finite State Machine Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmstatus](index.html) module"] +pub struct FSMSTATUS_SPEC; +impl crate::RegisterSpec for FSMSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fsmstatus::R](R) reader structure"] +impl crate::Readable for FSMSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FSMSTATUS to value 0x01"] +impl crate::Resettable for FSMSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1j/src/usb/device/intenclr.rs b/pac/atsamda1j/src/usb/device/intenclr.rs new file mode 100644 index 00000000000..feffea27e6f --- /dev/null +++ b/pac/atsamda1j/src/usb/device/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/intenset.rs b/pac/atsamda1j/src/usb/device/intenset.rs new file mode 100644 index 00000000000..3f525c20e6a --- /dev/null +++ b/pac/atsamda1j/src/usb/device/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/intflag.rs b/pac/atsamda1j/src/usb/device/intflag.rs new file mode 100644 index 00000000000..1b52bfae973 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend"] +pub struct SUSPEND_R(crate::FieldReader); +impl SUSPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSPEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSPEND` writer - Suspend"] +pub struct SUSPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SUSPEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `MSOF` reader - Micro Start of Frame in High Speed Mode"] +pub struct MSOF_R(crate::FieldReader); +impl MSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSOF` writer - Micro Start of Frame in High Speed Mode"] +pub struct MSOF_W<'a> { + w: &'a mut W, +} +impl<'a> MSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SOF` reader - Start Of Frame"] +pub struct SOF_R(crate::FieldReader); +impl SOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOF` writer - Start Of Frame"] +pub struct SOF_W<'a> { + w: &'a mut W, +} +impl<'a> SOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EORST` reader - End of Reset"] +pub struct EORST_R(crate::FieldReader); +impl EORST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORST` writer - End of Reset"] +pub struct EORST_W<'a> { + w: &'a mut W, +} +impl<'a> EORST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `EORSM` reader - End Of Resume"] +pub struct EORSM_R(crate::FieldReader); +impl EORSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EORSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EORSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EORSM` writer - End Of Resume"] +pub struct EORSM_W<'a> { + w: &'a mut W, +} +impl<'a> EORSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet"] +pub struct LPMNYET_R(crate::FieldReader); +impl LPMNYET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMNYET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMNYET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet"] +pub struct LPMNYET_W<'a> { + w: &'a mut W, +} +impl<'a> LPMNYET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend"] +pub struct LPMSUSP_R(crate::FieldReader); +impl LPMSUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPMSUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPMSUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend"] +pub struct LPMSUSP_W<'a> { + w: &'a mut W, +} +impl<'a> LPMSUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + pub fn suspend(&mut self) -> SUSPEND_W { + SUSPEND_W { w: self } + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + pub fn msof(&mut self) -> MSOF_W { + MSOF_W { w: self } + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + pub fn sof(&mut self) -> SOF_W { + SOF_W { w: self } + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + pub fn eorst(&mut self) -> EORST_W { + EORST_W { w: self } + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + pub fn eorsm(&mut self) -> EORSM_W { + EORSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + pub fn lpmnyet(&mut self) -> LPMNYET_W { + LPMNYET_W { w: self } + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + pub fn lpmsusp(&mut self) -> LPMSUSP_W { + LPMSUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/padcal.rs b/pac/atsamda1j/src/usb/device/padcal.rs new file mode 100644 index 00000000000..9b11d4fc687 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/padcal.rs @@ -0,0 +1,177 @@ +#[doc = "Register `PADCAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PADCAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRANSP` reader - USB Pad Transp calibration"] +pub struct TRANSP_R(crate::FieldReader); +impl TRANSP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSP` writer - USB Pad Transp calibration"] +pub struct TRANSP_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `TRANSN` reader - USB Pad Transn calibration"] +pub struct TRANSN_R(crate::FieldReader); +impl TRANSN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSN` writer - USB Pad Transn calibration"] +pub struct TRANSN_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 6)) | ((value as u16 & 0x1f) << 6); + self.w + } +} +#[doc = "Field `TRIM` reader - USB Pad Trim calibration"] +pub struct TRIM_R(crate::FieldReader); +impl TRIM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIM` writer - USB Pad Trim calibration"] +pub struct TRIM_W<'a> { + w: &'a mut W, +} +impl<'a> TRIM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u16 & 0x07) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&self) -> TRANSP_R { + TRANSP_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&self) -> TRANSN_R { + TRANSN_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 12) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&mut self) -> TRANSP_W { + TRANSP_W { w: self } + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&mut self) -> TRANSN_W { + TRANSN_W { w: self } + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&mut self) -> TRIM_W { + TRIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB PAD Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [padcal](index.html) module"] +pub struct PADCAL_SPEC; +impl crate::RegisterSpec for PADCAL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [padcal::R](R) reader structure"] +impl crate::Readable for PADCAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [padcal::W](W) writer structure"] +impl crate::Writable for PADCAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PADCAL to value 0"] +impl crate::Resettable for PADCAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/device/qosctrl.rs b/pac/atsamda1j/src/usb/device/qosctrl.rs new file mode 100644 index 00000000000..86b85a16067 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/qosctrl.rs @@ -0,0 +1,290 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Configuration Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `CQOS` reader - Configuration Quality of Service"] +pub struct CQOS_R(crate::FieldReader); +impl CQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CQOS_A { + match self.bits { + 0 => CQOS_A::DISABLE, + 1 => CQOS_A::LOW, + 2 => CQOS_A::MEDIUM, + 3 => CQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == CQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == CQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == CQOS_A::HIGH + } +} +impl core::ops::Deref for CQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CQOS` writer - Configuration Quality of Service"] +pub struct CQOS_W<'a> { + w: &'a mut W, +} +impl<'a> CQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(CQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(CQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(CQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Data Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&self) -> CQOS_R { + CQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&mut self) -> CQOS_W { + CQOS_W { w: self } + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB Quality Of Service\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x05"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1j/src/usb/device/status.rs b/pac/atsamda1j/src/usb/device/status.rs new file mode 100644 index 00000000000..ef62be58537 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/status.rs @@ -0,0 +1,157 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Speed Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Full-speed mode"] + FS = 0, + #[doc = "1: High-speed mode"] + HS = 1, + #[doc = "2: Low-speed mode"] + LS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Status"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::FS), + 1 => Some(SPEED_A::HS), + 2 => Some(SPEED_A::LS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPEED_A::FS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + **self == SPEED_A::HS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + **self == SPEED_A::LS + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "USB Line State Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LINESTATE_A { + #[doc = "0: SE0/RESET"] + _0 = 0, + #[doc = "1: FS-J or LS-K State"] + _1 = 1, + #[doc = "2: FS-K or LS-J State"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LINESTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `LINESTATE` reader - USB Line State Status"] +pub struct LINESTATE_R(crate::FieldReader); +impl LINESTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINESTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LINESTATE_A::_0), + 1 => Some(LINESTATE_A::_1), + 2 => Some(LINESTATE_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == LINESTATE_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == LINESTATE_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == LINESTATE_A::_2 + } +} +impl core::ops::Deref for LINESTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&self) -> LINESTATE_R { + LINESTATE_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "DEVICE Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x40"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x40 + } +} diff --git a/pac/atsamda1j/src/usb/device/syncbusy.rs b/pac/atsamda1j/src/usb/device/syncbusy.rs new file mode 100644 index 00000000000..5f22af98954 --- /dev/null +++ b/pac/atsamda1j/src/usb/device/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host.rs b/pac/atsamda1j/src/usb/host.rs new file mode 100644 index 00000000000..4f2a018f914 --- /dev/null +++ b/pac/atsamda1j/src/usb/host.rs @@ -0,0 +1,84 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "USB Quality Of Service"] +pub mod qosctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "HOST Control B"] +pub mod ctrlb; +#[doc = "HSOFC register accessor: an alias for `Reg`"] +pub type HSOFC = crate::Reg; +#[doc = "HOST Host Start Of Frame Control"] +pub mod hsofc; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "HOST Status"] +pub mod status; +#[doc = "FSMSTATUS register accessor: an alias for `Reg`"] +pub type FSMSTATUS = crate::Reg; +#[doc = "Finite State Machine Status"] +pub mod fsmstatus; +#[doc = "FNUM register accessor: an alias for `Reg`"] +pub type FNUM = crate::Reg; +#[doc = "HOST Host Frame Number"] +pub mod fnum; +#[doc = "FLENHIGH register accessor: an alias for `Reg`"] +pub type FLENHIGH = crate::Reg; +#[doc = "HOST Host Frame Length"] +pub mod flenhigh; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "HOST Host Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "HOST Host Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "HOST Host Interrupt Flag"] +pub mod intflag; +#[doc = "PINTSMRY register accessor: an alias for `Reg`"] +pub type PINTSMRY = crate::Reg; +#[doc = "HOST Pipe Interrupt Summary"] +pub mod pintsmry; +#[doc = "DESCADD register accessor: an alias for `Reg`"] +pub type DESCADD = crate::Reg; +#[doc = "Descriptor Address"] +pub mod descadd; +#[doc = "PADCAL register accessor: an alias for `Reg`"] +pub type PADCAL = crate::Reg; +#[doc = "USB PAD Calibration"] +pub mod padcal; +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST_PIPE { + #[doc = "0x00 - HOST_PIPE End Point Configuration"] + pub pcfg: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x03 - HOST_PIPE Bus Access Period of Pipe"] + pub binterval: crate::Reg, + #[doc = "0x04 - HOST_PIPE End Point Pipe Status Clear"] + pub pstatusclr: crate::Reg, + #[doc = "0x05 - HOST_PIPE End Point Pipe Status Set"] + pub pstatusset: crate::Reg, + #[doc = "0x06 - HOST_PIPE End Point Pipe Status"] + pub pstatus: crate::Reg, + #[doc = "0x07 - HOST_PIPE Pipe Interrupt Flag"] + pub pintflag: crate::Reg, + #[doc = "0x08 - HOST_PIPE Pipe Interrupt Flag Clear"] + pub pintenclr: crate::Reg, + #[doc = "0x09 - HOST_PIPE Pipe Interrupt Flag Set"] + pub pintenset: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "HOST_PIPE\\[%s\\]"] +pub mod host_pipe; diff --git a/pac/atsamda1j/src/usb/host/ctrla.rs b/pac/atsamda1j/src/usb/host/ctrla.rs new file mode 100644 index 00000000000..f29253092ce --- /dev/null +++ b/pac/atsamda1j/src/usb/host/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby Mode"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby Mode"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MODE_A { + #[doc = "0: Device Mode"] + DEVICE = 0, + #[doc = "1: Host Mode"] + HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::DEVICE, + true => MODE_A::HOST, + } + } + #[doc = "Checks if the value of the field is `DEVICE`"] + #[inline(always)] + pub fn is_device(&self) -> bool { + **self == MODE_A::DEVICE + } + #[doc = "Checks if the value of the field is `HOST`"] + #[inline(always)] + pub fn is_host(&self) -> bool { + **self == MODE_A::HOST + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Device Mode"] + #[inline(always)] + pub fn device(self) -> &'a mut W { + self.variant(MODE_A::DEVICE) + } + #[doc = "Host Mode"] + #[inline(always)] + pub fn host(self) -> &'a mut W { + self.variant(MODE_A::HOST) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/ctrlb.rs b/pac/atsamda1j/src/usb/host/ctrlb.rs new file mode 100644 index 00000000000..59536faa219 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/ctrlb.rs @@ -0,0 +1,481 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESUME` reader - Send USB Resume"] +pub struct RESUME_R(crate::FieldReader); +impl RESUME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESUME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESUME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESUME` writer - Send USB Resume"] +pub struct RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Speed Configuration for Host\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPDCONF_A { + #[doc = "0: Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable."] + NORMAL = 0, + #[doc = "3: Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only."] + FS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPDCONF_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPDCONF` reader - Speed Configuration for Host"] +pub struct SPDCONF_R(crate::FieldReader); +impl SPDCONF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPDCONF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPDCONF_A::NORMAL), + 3 => Some(SPDCONF_A::FS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NORMAL`"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + **self == SPDCONF_A::NORMAL + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + **self == SPDCONF_A::FS + } +} +impl core::ops::Deref for SPDCONF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPDCONF` writer - Speed Configuration for Host"] +pub struct SPDCONF_W<'a> { + w: &'a mut W, +} +impl<'a> SPDCONF_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPDCONF_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable."] + #[inline(always)] + pub fn normal(self) -> &'a mut W { + self.variant(SPDCONF_A::NORMAL) + } + #[doc = "Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only."] + #[inline(always)] + pub fn fs(self) -> &'a mut W { + self.variant(SPDCONF_A::FS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `TSTJ` reader - Test mode J"] +pub struct TSTJ_R(crate::FieldReader); +impl TSTJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTJ` writer - Test mode J"] +pub struct TSTJ_W<'a> { + w: &'a mut W, +} +impl<'a> TSTJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTK` reader - Test mode K"] +pub struct TSTK_R(crate::FieldReader); +impl TSTK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTK` writer - Test mode K"] +pub struct TSTK_W<'a> { + w: &'a mut W, +} +impl<'a> TSTK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SOFE` reader - Start of Frame Generation Enable"] +pub struct SOFE_R(crate::FieldReader); +impl SOFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOFE` writer - Start of Frame Generation Enable"] +pub struct SOFE_W<'a> { + w: &'a mut W, +} +impl<'a> SOFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BUSRESET` reader - Send USB Reset"] +pub struct BUSRESET_R(crate::FieldReader); +impl BUSRESET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSRESET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSRESET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSRESET` writer - Send USB Reset"] +pub struct BUSRESET_W<'a> { + w: &'a mut W, +} +impl<'a> BUSRESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `VBUSOK` reader - VBUS is OK"] +pub struct VBUSOK_R(crate::FieldReader); +impl VBUSOK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VBUSOK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VBUSOK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VBUSOK` writer - VBUS is OK"] +pub struct VBUSOK_W<'a> { + w: &'a mut W, +} +impl<'a> VBUSOK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `L1RESUME` reader - Send L1 Resume"] +pub struct L1RESUME_R(crate::FieldReader); +impl L1RESUME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + L1RESUME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for L1RESUME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `L1RESUME` writer - Send L1 Resume"] +pub struct L1RESUME_W<'a> { + w: &'a mut W, +} +impl<'a> L1RESUME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 1 - Send USB Resume"] + #[inline(always)] + pub fn resume(&self) -> RESUME_R { + RESUME_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Speed Configuration for Host"] + #[inline(always)] + pub fn spdconf(&self) -> SPDCONF_R { + SPDCONF_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&self) -> TSTJ_R { + TSTJ_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&self) -> TSTK_R { + TSTK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Start of Frame Generation Enable"] + #[inline(always)] + pub fn sofe(&self) -> SOFE_R { + SOFE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Send USB Reset"] + #[inline(always)] + pub fn busreset(&self) -> BUSRESET_R { + BUSRESET_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - VBUS is OK"] + #[inline(always)] + pub fn vbusok(&self) -> VBUSOK_R { + VBUSOK_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Send L1 Resume"] + #[inline(always)] + pub fn l1resume(&self) -> L1RESUME_R { + L1RESUME_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Send USB Resume"] + #[inline(always)] + pub fn resume(&mut self) -> RESUME_W { + RESUME_W { w: self } + } + #[doc = "Bits 2:3 - Speed Configuration for Host"] + #[inline(always)] + pub fn spdconf(&mut self) -> SPDCONF_W { + SPDCONF_W { w: self } + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&mut self) -> TSTJ_W { + TSTJ_W { w: self } + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&mut self) -> TSTK_W { + TSTK_W { w: self } + } + #[doc = "Bit 8 - Start of Frame Generation Enable"] + #[inline(always)] + pub fn sofe(&mut self) -> SOFE_W { + SOFE_W { w: self } + } + #[doc = "Bit 9 - Send USB Reset"] + #[inline(always)] + pub fn busreset(&mut self) -> BUSRESET_W { + BUSRESET_W { w: self } + } + #[doc = "Bit 10 - VBUS is OK"] + #[inline(always)] + pub fn vbusok(&mut self) -> VBUSOK_W { + VBUSOK_W { w: self } + } + #[doc = "Bit 11 - Send L1 Resume"] + #[inline(always)] + pub fn l1resume(&mut self) -> L1RESUME_W { + L1RESUME_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/descadd.rs b/pac/atsamda1j/src/usb/host/descadd.rs new file mode 100644 index 00000000000..9fe18a8dcb2 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/descadd.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DESCADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DESCADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCADD` reader - Descriptor Address Value"] +pub struct DESCADD_R(crate::FieldReader); +impl DESCADD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCADD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCADD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCADD` writer - Descriptor Address Value"] +pub struct DESCADD_W<'a> { + w: &'a mut W, +} +impl<'a> DESCADD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&self) -> DESCADD_R { + DESCADD_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&mut self) -> DESCADD_W { + DESCADD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [descadd](index.html) module"] +pub struct DESCADD_SPEC; +impl crate::RegisterSpec for DESCADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [descadd::R](R) reader structure"] +impl crate::Readable for DESCADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [descadd::W](W) writer structure"] +impl crate::Writable for DESCADD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DESCADD to value 0"] +impl crate::Resettable for DESCADD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/flenhigh.rs b/pac/atsamda1j/src/usb/host/flenhigh.rs new file mode 100644 index 00000000000..ab9d58be29b --- /dev/null +++ b/pac/atsamda1j/src/usb/host/flenhigh.rs @@ -0,0 +1,53 @@ +#[doc = "Register `FLENHIGH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FLENHIGH` reader - Frame Length"] +pub struct FLENHIGH_R(crate::FieldReader); +impl FLENHIGH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLENHIGH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENHIGH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Frame Length"] + #[inline(always)] + pub fn flenhigh(&self) -> FLENHIGH_R { + FLENHIGH_R::new(self.bits as u8) + } +} +#[doc = "HOST Host Frame Length\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flenhigh](index.html) module"] +pub struct FLENHIGH_SPEC; +impl crate::RegisterSpec for FLENHIGH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [flenhigh::R](R) reader structure"] +impl crate::Readable for FLENHIGH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FLENHIGH to value 0"] +impl crate::Resettable for FLENHIGH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/fnum.rs b/pac/atsamda1j/src/usb/host/fnum.rs new file mode 100644 index 00000000000..cc5f2b47dce --- /dev/null +++ b/pac/atsamda1j/src/usb/host/fnum.rs @@ -0,0 +1,140 @@ +#[doc = "Register `FNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MFNUM` reader - Micro Frame Number"] +pub struct MFNUM_R(crate::FieldReader); +impl MFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MFNUM` writer - Micro Frame Number"] +pub struct MFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> MFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `FNUM` reader - Frame Number"] +pub struct FNUM_R(crate::FieldReader); +impl FNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FNUM` writer - Frame Number"] +pub struct FNUM_W<'a> { + w: &'a mut W, +} +impl<'a> FNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 3)) | ((value as u16 & 0x07ff) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&self) -> MFNUM_R { + MFNUM_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&self) -> FNUM_R { + FNUM_R::new(((self.bits >> 3) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&mut self) -> MFNUM_W { + MFNUM_W { w: self } + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&mut self) -> FNUM_W { + FNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Frame Number\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fnum](index.html) module"] +pub struct FNUM_SPEC; +impl crate::RegisterSpec for FNUM_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [fnum::R](R) reader structure"] +impl crate::Readable for FNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fnum::W](W) writer structure"] +impl crate::Writable for FNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FNUM to value 0"] +impl crate::Resettable for FNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/fsmstatus.rs b/pac/atsamda1j/src/usb/host/fsmstatus.rs new file mode 100644 index 00000000000..a89e8172c39 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/fsmstatus.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FSMSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Fine State Machine Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FSMSTATE_A { + #[doc = "1: OFF (L3). It corresponds to the powered-off, disconnected, and disabled state"] + OFF = 1, + #[doc = "2: ON (L0). It corresponds to the Idle and Active states"] + ON = 2, + #[doc = "4: SUSPEND (L2)"] + SUSPEND = 4, + #[doc = "8: SLEEP (L1)"] + SLEEP = 8, + #[doc = "16: DNRESUME. Down Stream Resume."] + DNRESUME = 16, + #[doc = "32: UPRESUME. Up Stream Resume."] + UPRESUME = 32, + #[doc = "64: RESET. USB lines Reset."] + RESET = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSMSTATE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FSMSTATE` reader - Fine State Machine Status"] +pub struct FSMSTATE_R(crate::FieldReader); +impl FSMSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FSMSTATE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(FSMSTATE_A::OFF), + 2 => Some(FSMSTATE_A::ON), + 4 => Some(FSMSTATE_A::SUSPEND), + 8 => Some(FSMSTATE_A::SLEEP), + 16 => Some(FSMSTATE_A::DNRESUME), + 32 => Some(FSMSTATE_A::UPRESUME), + 64 => Some(FSMSTATE_A::RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FSMSTATE_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + **self == FSMSTATE_A::ON + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == FSMSTATE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `SLEEP`"] + #[inline(always)] + pub fn is_sleep(&self) -> bool { + **self == FSMSTATE_A::SLEEP + } + #[doc = "Checks if the value of the field is `DNRESUME`"] + #[inline(always)] + pub fn is_dnresume(&self) -> bool { + **self == FSMSTATE_A::DNRESUME + } + #[doc = "Checks if the value of the field is `UPRESUME`"] + #[inline(always)] + pub fn is_upresume(&self) -> bool { + **self == FSMSTATE_A::UPRESUME + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == FSMSTATE_A::RESET + } +} +impl core::ops::Deref for FSMSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Fine State Machine Status"] + #[inline(always)] + pub fn fsmstate(&self) -> FSMSTATE_R { + FSMSTATE_R::new((self.bits & 0x7f) as u8) + } +} +#[doc = "Finite State Machine Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmstatus](index.html) module"] +pub struct FSMSTATUS_SPEC; +impl crate::RegisterSpec for FSMSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fsmstatus::R](R) reader structure"] +impl crate::Readable for FSMSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FSMSTATUS to value 0x01"] +impl crate::Resettable for FSMSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe.rs b/pac/atsamda1j/src/usb/host/host_pipe.rs new file mode 100644 index 00000000000..e0a917f3a12 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe.rs @@ -0,0 +1,32 @@ +#[doc = "PCFG register accessor: an alias for `Reg`"] +pub type PCFG = crate::Reg; +#[doc = "HOST_PIPE End Point Configuration"] +pub mod pcfg; +#[doc = "BINTERVAL register accessor: an alias for `Reg`"] +pub type BINTERVAL = crate::Reg; +#[doc = "HOST_PIPE Bus Access Period of Pipe"] +pub mod binterval; +#[doc = "PSTATUSCLR register accessor: an alias for `Reg`"] +pub type PSTATUSCLR = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status Clear"] +pub mod pstatusclr; +#[doc = "PSTATUSSET register accessor: an alias for `Reg`"] +pub type PSTATUSSET = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status Set"] +pub mod pstatusset; +#[doc = "PSTATUS register accessor: an alias for `Reg`"] +pub type PSTATUS = crate::Reg; +#[doc = "HOST_PIPE End Point Pipe Status"] +pub mod pstatus; +#[doc = "PINTFLAG register accessor: an alias for `Reg`"] +pub type PINTFLAG = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag"] +pub mod pintflag; +#[doc = "PINTENCLR register accessor: an alias for `Reg`"] +pub type PINTENCLR = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag Clear"] +pub mod pintenclr; +#[doc = "PINTENSET register accessor: an alias for `Reg`"] +pub type PINTENSET = crate::Reg; +#[doc = "HOST_PIPE Pipe Interrupt Flag Set"] +pub mod pintenset; diff --git a/pac/atsamda1j/src/usb/host/host_pipe/binterval.rs b/pac/atsamda1j/src/usb/host/host_pipe/binterval.rs new file mode 100644 index 00000000000..7b29db1e3d6 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/binterval.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BINTERVAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BINTERVAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BITINTERVAL` reader - Bit Interval"] +pub struct BITINTERVAL_R(crate::FieldReader); +impl BITINTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BITINTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BITINTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BITINTERVAL` writer - Bit Interval"] +pub struct BITINTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BITINTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Bit Interval"] + #[inline(always)] + pub fn bitinterval(&self) -> BITINTERVAL_R { + BITINTERVAL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Bit Interval"] + #[inline(always)] + pub fn bitinterval(&mut self) -> BITINTERVAL_W { + BITINTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Bus Access Period of Pipe\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [binterval](index.html) module"] +pub struct BINTERVAL_SPEC; +impl crate::RegisterSpec for BINTERVAL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [binterval::R](R) reader structure"] +impl crate::Readable for BINTERVAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [binterval::W](W) writer structure"] +impl crate::Writable for BINTERVAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BINTERVAL to value 0"] +impl crate::Resettable for BINTERVAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe/pcfg.rs b/pac/atsamda1j/src/usb/host/host_pipe/pcfg.rs new file mode 100644 index 00000000000..c6677dce494 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/pcfg.rs @@ -0,0 +1,187 @@ +#[doc = "Register `PCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTOKEN` reader - Pipe Token"] +pub struct PTOKEN_R(crate::FieldReader); +impl PTOKEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PTOKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTOKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTOKEN` writer - Pipe Token"] +pub struct PTOKEN_W<'a> { + w: &'a mut W, +} +impl<'a> PTOKEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Field `BK` reader - Pipe Bank"] +pub struct BK_R(crate::FieldReader); +impl BK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK` writer - Pipe Bank"] +pub struct BK_W<'a> { + w: &'a mut W, +} +impl<'a> BK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PTYPE` reader - Pipe Type"] +pub struct PTYPE_R(crate::FieldReader); +impl PTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PTYPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTYPE` writer - Pipe Type"] +pub struct PTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> PTYPE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u8 & 0x07) << 3); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Pipe Token"] + #[inline(always)] + pub fn ptoken(&self) -> PTOKEN_R { + PTOKEN_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Pipe Bank"] + #[inline(always)] + pub fn bk(&self) -> BK_R { + BK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:5 - Pipe Type"] + #[inline(always)] + pub fn ptype(&self) -> PTYPE_R { + PTYPE_R::new(((self.bits >> 3) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Pipe Token"] + #[inline(always)] + pub fn ptoken(&mut self) -> PTOKEN_W { + PTOKEN_W { w: self } + } + #[doc = "Bit 2 - Pipe Bank"] + #[inline(always)] + pub fn bk(&mut self) -> BK_W { + BK_W { w: self } + } + #[doc = "Bits 3:5 - Pipe Type"] + #[inline(always)] + pub fn ptype(&mut self) -> PTYPE_W { + PTYPE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcfg](index.html) module"] +pub struct PCFG_SPEC; +impl crate::RegisterSpec for PCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pcfg::R](R) reader structure"] +impl crate::Readable for PCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pcfg::W](W) writer structure"] +impl crate::Writable for PCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCFG to value 0"] +impl crate::Resettable for PCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe/pintenclr.rs b/pac/atsamda1j/src/usb/host/host_pipe/pintenclr.rs new file mode 100644 index 00000000000..d994194d579 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/pintenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Disable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Disable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Disable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Disable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Disable"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Disable"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Disable"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Disable"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Disable"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Disable"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Disable"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Disable"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Disable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Disable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Disable"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Disable"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Disable"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Disable"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Disable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Disable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Disable"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Disable"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Disable"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Disable"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintenclr](index.html) module"] +pub struct PINTENCLR_SPEC; +impl crate::RegisterSpec for PINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintenclr::R](R) reader structure"] +impl crate::Readable for PINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintenclr::W](W) writer structure"] +impl crate::Writable for PINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTENCLR to value 0"] +impl crate::Resettable for PINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe/pintenset.rs b/pac/atsamda1j/src/usb/host/host_pipe/pintenset.rs new file mode 100644 index 00000000000..fc7368fe117 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/pintenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Enable"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Enable"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Enable"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Enable"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Enable"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Enable"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Enable"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Enable"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Enable"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Enable"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Enable"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Enable"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Enable"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Enable"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Enable"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Enable"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintenset](index.html) module"] +pub struct PINTENSET_SPEC; +impl crate::RegisterSpec for PINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintenset::R](R) reader structure"] +impl crate::Readable for PINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintenset::W](W) writer structure"] +impl crate::Writable for PINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTENSET to value 0"] +impl crate::Resettable for PINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe/pintflag.rs b/pac/atsamda1j/src/usb/host/host_pipe/pintflag.rs new file mode 100644 index 00000000000..9724af9984c --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/pintflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `PINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Flag"] +pub struct TRCPT0_R(crate::FieldReader); +impl TRCPT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Flag"] +pub struct TRCPT0_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Flag"] +pub struct TRCPT1_R(crate::FieldReader); +impl TRCPT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRCPT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCPT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Flag"] +pub struct TRCPT1_W<'a> { + w: &'a mut W, +} +impl<'a> TRCPT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TRFAIL` reader - Error Flow Interrupt Flag"] +pub struct TRFAIL_R(crate::FieldReader); +impl TRFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRFAIL` writer - Error Flow Interrupt Flag"] +pub struct TRFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> TRFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PERR` reader - Pipe Error Interrupt Flag"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Pipe Error Interrupt Flag"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXSTP` reader - Transmit Setup Interrupt Flag"] +pub struct TXSTP_R(crate::FieldReader); +impl TXSTP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTP` writer - Transmit Setup Interrupt Flag"] +pub struct TXSTP_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Flag"] +pub struct STALL_R(crate::FieldReader); +impl STALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Flag"] +pub struct STALL_W<'a> { + w: &'a mut W, +} +impl<'a> STALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Flag"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Flag"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Error Flow Interrupt Flag"] + #[inline(always)] + pub fn trfail(&self) -> TRFAIL_R { + TRFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe Error Interrupt Flag"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmit Setup Interrupt Flag"] + #[inline(always)] + pub fn txstp(&self) -> TXSTP_R { + TXSTP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Flag"] + #[inline(always)] + pub fn trcpt0(&mut self) -> TRCPT0_W { + TRCPT0_W { w: self } + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Flag"] + #[inline(always)] + pub fn trcpt1(&mut self) -> TRCPT1_W { + TRCPT1_W { w: self } + } + #[doc = "Bit 2 - Error Flow Interrupt Flag"] + #[inline(always)] + pub fn trfail(&mut self) -> TRFAIL_W { + TRFAIL_W { w: self } + } + #[doc = "Bit 3 - Pipe Error Interrupt Flag"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 4 - Transmit Setup Interrupt Flag"] + #[inline(always)] + pub fn txstp(&mut self) -> TXSTP_W { + TXSTP_W { w: self } + } + #[doc = "Bit 5 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&mut self) -> STALL_W { + STALL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE Pipe Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintflag](index.html) module"] +pub struct PINTFLAG_SPEC; +impl crate::RegisterSpec for PINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pintflag::R](R) reader structure"] +impl crate::Readable for PINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pintflag::W](W) writer structure"] +impl crate::Writable for PINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINTFLAG to value 0"] +impl crate::Resettable for PINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe/pstatus.rs b/pac/atsamda1j/src/usb/host/host_pipe/pstatus.rs new file mode 100644 index 00000000000..072b3621ff5 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/pstatus.rs @@ -0,0 +1,133 @@ +#[doc = "Register `PSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DTGL` reader - Data Toggle"] +pub struct DTGL_R(crate::FieldReader); +impl DTGL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTGL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTGL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURBK` reader - Current Bank"] +pub struct CURBK_R(crate::FieldReader); +impl CURBK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CURBK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURBK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PFREEZE` reader - Pipe Freeze"] +pub struct PFREEZE_R(crate::FieldReader); +impl PFREEZE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PFREEZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PFREEZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK0RDY` reader - Bank 0 ready"] +pub struct BK0RDY_R(crate::FieldReader); +impl BK0RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK0RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK0RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BK1RDY` reader - Bank 1 ready"] +pub struct BK1RDY_R(crate::FieldReader); +impl BK1RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BK1RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BK1RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Data Toggle"] + #[inline(always)] + pub fn dtgl(&self) -> DTGL_R { + DTGL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Current Bank"] + #[inline(always)] + pub fn curbk(&self) -> CURBK_R { + CURBK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Pipe Freeze"] + #[inline(always)] + pub fn pfreeze(&self) -> PFREEZE_R { + PFREEZE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Bank 0 ready"] + #[inline(always)] + pub fn bk0rdy(&self) -> BK0RDY_R { + BK0RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bank 1 ready"] + #[inline(always)] + pub fn bk1rdy(&self) -> BK1RDY_R { + BK1RDY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "HOST_PIPE End Point Pipe Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatus](index.html) module"] +pub struct PSTATUS_SPEC; +impl crate::RegisterSpec for PSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pstatus::R](R) reader structure"] +impl crate::Readable for PSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PSTATUS to value 0"] +impl crate::Resettable for PSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe/pstatusclr.rs b/pac/atsamda1j/src/usb/host/host_pipe/pstatusclr.rs new file mode 100644 index 00000000000..6fb40667a9d --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/pstatusclr.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PSTATUSCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGL` writer - Data Toggle clear"] +pub struct DTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DTGL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CURBK` writer - Curren Bank clear"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PFREEZE` writer - Pipe Freeze Clear"] +pub struct PFREEZE_W<'a> { + w: &'a mut W, +} +impl<'a> PFREEZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Clear"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Clear"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle clear"] + #[inline(always)] + pub fn dtgl(&mut self) -> DTGL_W { + DTGL_W { w: self } + } + #[doc = "Bit 2 - Curren Bank clear"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Pipe Freeze Clear"] + #[inline(always)] + pub fn pfreeze(&mut self) -> PFREEZE_W { + PFREEZE_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Clear"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Clear"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Pipe Status Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatusclr](index.html) module"] +pub struct PSTATUSCLR_SPEC; +impl crate::RegisterSpec for PSTATUSCLR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [pstatusclr::W](W) writer structure"] +impl crate::Writable for PSTATUSCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSTATUSCLR to value 0"] +impl crate::Resettable for PSTATUSCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/host_pipe/pstatusset.rs b/pac/atsamda1j/src/usb/host/host_pipe/pstatusset.rs new file mode 100644 index 00000000000..2d3e855e41f --- /dev/null +++ b/pac/atsamda1j/src/usb/host/host_pipe/pstatusset.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PSTATUSSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGL` writer - Data Toggle Set"] +pub struct DTGL_W<'a> { + w: &'a mut W, +} +impl<'a> DTGL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CURBK` writer - Current Bank Set"] +pub struct CURBK_W<'a> { + w: &'a mut W, +} +impl<'a> CURBK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PFREEZE` writer - Pipe Freeze Set"] +pub struct PFREEZE_W<'a> { + w: &'a mut W, +} +impl<'a> PFREEZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Set"] +pub struct BK0RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK0RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Set"] +pub struct BK1RDY_W<'a> { + w: &'a mut W, +} +impl<'a> BK1RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Data Toggle Set"] + #[inline(always)] + pub fn dtgl(&mut self) -> DTGL_W { + DTGL_W { w: self } + } + #[doc = "Bit 2 - Current Bank Set"] + #[inline(always)] + pub fn curbk(&mut self) -> CURBK_W { + CURBK_W { w: self } + } + #[doc = "Bit 4 - Pipe Freeze Set"] + #[inline(always)] + pub fn pfreeze(&mut self) -> PFREEZE_W { + PFREEZE_W { w: self } + } + #[doc = "Bit 6 - Bank 0 Ready Set"] + #[inline(always)] + pub fn bk0rdy(&mut self) -> BK0RDY_W { + BK0RDY_W { w: self } + } + #[doc = "Bit 7 - Bank 1 Ready Set"] + #[inline(always)] + pub fn bk1rdy(&mut self) -> BK1RDY_W { + BK1RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST_PIPE End Point Pipe Status Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pstatusset](index.html) module"] +pub struct PSTATUSSET_SPEC; +impl crate::RegisterSpec for PSTATUSSET_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [pstatusset::W](W) writer structure"] +impl crate::Writable for PSTATUSSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PSTATUSSET to value 0"] +impl crate::Resettable for PSTATUSSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/hsofc.rs b/pac/atsamda1j/src/usb/host/hsofc.rs new file mode 100644 index 00000000000..bc714a862ff --- /dev/null +++ b/pac/atsamda1j/src/usb/host/hsofc.rs @@ -0,0 +1,150 @@ +#[doc = "Register `HSOFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HSOFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLENC` reader - Frame Length Control"] +pub struct FLENC_R(crate::FieldReader); +impl FLENC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLENC` writer - Frame Length Control"] +pub struct FLENC_W<'a> { + w: &'a mut W, +} +impl<'a> FLENC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `FLENCE` reader - Frame Length Control Enable"] +pub struct FLENCE_R(crate::FieldReader); +impl FLENCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLENCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLENCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLENCE` writer - Frame Length Control Enable"] +pub struct FLENCE_W<'a> { + w: &'a mut W, +} +impl<'a> FLENCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Frame Length Control"] + #[inline(always)] + pub fn flenc(&self) -> FLENC_R { + FLENC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Frame Length Control Enable"] + #[inline(always)] + pub fn flence(&self) -> FLENCE_R { + FLENCE_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Frame Length Control"] + #[inline(always)] + pub fn flenc(&mut self) -> FLENC_W { + FLENC_W { w: self } + } + #[doc = "Bit 7 - Frame Length Control Enable"] + #[inline(always)] + pub fn flence(&mut self) -> FLENCE_W { + FLENCE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Start Of Frame Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hsofc](index.html) module"] +pub struct HSOFC_SPEC; +impl crate::RegisterSpec for HSOFC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [hsofc::R](R) reader structure"] +impl crate::Readable for HSOFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hsofc::W](W) writer structure"] +impl crate::Writable for HSOFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets HSOFC to value 0"] +impl crate::Resettable for HSOFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/intenclr.rs b/pac/atsamda1j/src/usb/host/intenclr.rs new file mode 100644 index 00000000000..df6a7c7b78e --- /dev/null +++ b/pac/atsamda1j/src/usb/host/intenclr.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Disable"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Disable"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - BUS Reset Interrupt Disable"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - BUS Reset Interrupt Disable"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Disable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Disable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - DownStream to Device Interrupt Disable"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - DownStream to Device Interrupt Disable"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume from Device Interrupt Disable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume from Device Interrupt Disable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Disable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Disable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Device Connection Interrupt Disable"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Device Connection Interrupt Disable"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Disable"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Disable"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BUS Reset Interrupt Disable"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Disable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Disable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Device Connection Interrupt Disable"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - BUS Reset Interrupt Disable"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Disable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - DownStream to Device Interrupt Disable"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Disable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Device Connection Interrupt Disable"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection Interrupt Disable"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/intenset.rs b/pac/atsamda1j/src/usb/host/intenset.rs new file mode 100644 index 00000000000..dce5e3a61f7 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/intenset.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Enable"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Enable"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - Bus Reset Interrupt Enable"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - Bus Reset Interrupt Enable"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - DownStream to the Device Interrupt Enable"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - DownStream to the Device Interrupt Enable"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume fromthe device Interrupt Enable"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume fromthe device Interrupt Enable"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Link Power Management Interrupt Enable"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Link Power Management Interrupt Enable"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Enable"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Enable"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Bus Reset Interrupt Enable"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - DownStream to the Device Interrupt Enable"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume fromthe device Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Link Power Management Interrupt Enable"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection Interrupt Enable"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - Bus Reset Interrupt Enable"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - DownStream to the Device Interrupt Enable"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume fromthe device Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Link Power Management Interrupt Enable"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection Interrupt Enable"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/intflag.rs b/pac/atsamda1j/src/usb/host/intflag.rs new file mode 100644 index 00000000000..14fbcfb2d1a --- /dev/null +++ b/pac/atsamda1j/src/usb/host/intflag.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HSOF` reader - Host Start Of Frame"] +pub struct HSOF_R(crate::FieldReader); +impl HSOF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSOF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSOF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSOF` writer - Host Start Of Frame"] +pub struct HSOF_W<'a> { + w: &'a mut W, +} +impl<'a> HSOF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RST` reader - Bus Reset"] +pub struct RST_R(crate::FieldReader); +impl RST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST` writer - Bus Reset"] +pub struct RST_W<'a> { + w: &'a mut W, +} +impl<'a> RST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WAKEUP` reader - Wake Up"] +pub struct WAKEUP_R(crate::FieldReader); +impl WAKEUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAKEUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAKEUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAKEUP` writer - Wake Up"] +pub struct WAKEUP_W<'a> { + w: &'a mut W, +} +impl<'a> WAKEUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DNRSM` reader - Downstream"] +pub struct DNRSM_R(crate::FieldReader); +impl DNRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNRSM` writer - Downstream"] +pub struct DNRSM_W<'a> { + w: &'a mut W, +} +impl<'a> DNRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UPRSM` reader - Upstream Resume from the Device"] +pub struct UPRSM_R(crate::FieldReader); +impl UPRSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UPRSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UPRSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UPRSM` writer - Upstream Resume from the Device"] +pub struct UPRSM_W<'a> { + w: &'a mut W, +} +impl<'a> UPRSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RAMACER` reader - Ram Access"] +pub struct RAMACER_R(crate::FieldReader); +impl RAMACER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMACER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMACER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMACER` writer - Ram Access"] +pub struct RAMACER_W<'a> { + w: &'a mut W, +} +impl<'a> RAMACER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `DCONN` reader - Device Connection"] +pub struct DCONN_R(crate::FieldReader); +impl DCONN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCONN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCONN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCONN` writer - Device Connection"] +pub struct DCONN_W<'a> { + w: &'a mut W, +} +impl<'a> DCONN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DDISC` reader - Device Disconnection"] +pub struct DDISC_R(crate::FieldReader); +impl DDISC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDISC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDISC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDISC` writer - Device Disconnection"] +pub struct DDISC_W<'a> { + w: &'a mut W, +} +impl<'a> DDISC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 2 - Host Start Of Frame"] + #[inline(always)] + pub fn hsof(&self) -> HSOF_R { + HSOF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Bus Reset"] + #[inline(always)] + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Downstream"] + #[inline(always)] + pub fn dnrsm(&self) -> DNRSM_R { + DNRSM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Upstream Resume from the Device"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Device Connection"] + #[inline(always)] + pub fn dconn(&self) -> DCONN_R { + DCONN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Device Disconnection"] + #[inline(always)] + pub fn ddisc(&self) -> DDISC_R { + DDISC_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Host Start Of Frame"] + #[inline(always)] + pub fn hsof(&mut self) -> HSOF_W { + HSOF_W { w: self } + } + #[doc = "Bit 3 - Bus Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RST_W { + RST_W { w: self } + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W { w: self } + } + #[doc = "Bit 5 - Downstream"] + #[inline(always)] + pub fn dnrsm(&mut self) -> DNRSM_W { + DNRSM_W { w: self } + } + #[doc = "Bit 6 - Upstream Resume from the Device"] + #[inline(always)] + pub fn uprsm(&mut self) -> UPRSM_W { + UPRSM_W { w: self } + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&mut self) -> RAMACER_W { + RAMACER_W { w: self } + } + #[doc = "Bit 8 - Device Connection"] + #[inline(always)] + pub fn dconn(&mut self) -> DCONN_W { + DCONN_W { w: self } + } + #[doc = "Bit 9 - Device Disconnection"] + #[inline(always)] + pub fn ddisc(&mut self) -> DDISC_W { + DDISC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Host Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/padcal.rs b/pac/atsamda1j/src/usb/host/padcal.rs new file mode 100644 index 00000000000..9b11d4fc687 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/padcal.rs @@ -0,0 +1,177 @@ +#[doc = "Register `PADCAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PADCAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRANSP` reader - USB Pad Transp calibration"] +pub struct TRANSP_R(crate::FieldReader); +impl TRANSP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSP` writer - USB Pad Transp calibration"] +pub struct TRANSP_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Field `TRANSN` reader - USB Pad Transn calibration"] +pub struct TRANSN_R(crate::FieldReader); +impl TRANSN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRANSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRANSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRANSN` writer - USB Pad Transn calibration"] +pub struct TRANSN_W<'a> { + w: &'a mut W, +} +impl<'a> TRANSN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 6)) | ((value as u16 & 0x1f) << 6); + self.w + } +} +#[doc = "Field `TRIM` reader - USB Pad Trim calibration"] +pub struct TRIM_R(crate::FieldReader); +impl TRIM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIM` writer - USB Pad Trim calibration"] +pub struct TRIM_W<'a> { + w: &'a mut W, +} +impl<'a> TRIM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u16 & 0x07) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&self) -> TRANSP_R { + TRANSP_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&self) -> TRANSN_R { + TRANSN_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 12) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&mut self) -> TRANSP_W { + TRANSP_W { w: self } + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&mut self) -> TRANSN_W { + TRANSN_W { w: self } + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&mut self) -> TRIM_W { + TRIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB PAD Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [padcal](index.html) module"] +pub struct PADCAL_SPEC; +impl crate::RegisterSpec for PADCAL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [padcal::R](R) reader structure"] +impl crate::Readable for PADCAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [padcal::W](W) writer structure"] +impl crate::Writable for PADCAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PADCAL to value 0"] +impl crate::Resettable for PADCAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/pintsmry.rs b/pac/atsamda1j/src/usb/host/pintsmry.rs new file mode 100644 index 00000000000..bc0fba3f12e --- /dev/null +++ b/pac/atsamda1j/src/usb/host/pintsmry.rs @@ -0,0 +1,193 @@ +#[doc = "Register `PINTSMRY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPINT0` reader - Pipe 0 Interrupt"] +pub struct EPINT0_R(crate::FieldReader); +impl EPINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT1` reader - Pipe 1 Interrupt"] +pub struct EPINT1_R(crate::FieldReader); +impl EPINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT2` reader - Pipe 2 Interrupt"] +pub struct EPINT2_R(crate::FieldReader); +impl EPINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT3` reader - Pipe 3 Interrupt"] +pub struct EPINT3_R(crate::FieldReader); +impl EPINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT4` reader - Pipe 4 Interrupt"] +pub struct EPINT4_R(crate::FieldReader); +impl EPINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT5` reader - Pipe 5 Interrupt"] +pub struct EPINT5_R(crate::FieldReader); +impl EPINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT6` reader - Pipe 6 Interrupt"] +pub struct EPINT6_R(crate::FieldReader); +impl EPINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPINT7` reader - Pipe 7 Interrupt"] +pub struct EPINT7_R(crate::FieldReader); +impl EPINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pipe 0 Interrupt"] + #[inline(always)] + pub fn epint0(&self) -> EPINT0_R { + EPINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pipe 1 Interrupt"] + #[inline(always)] + pub fn epint1(&self) -> EPINT1_R { + EPINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pipe 2 Interrupt"] + #[inline(always)] + pub fn epint2(&self) -> EPINT2_R { + EPINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pipe 3 Interrupt"] + #[inline(always)] + pub fn epint3(&self) -> EPINT3_R { + EPINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pipe 4 Interrupt"] + #[inline(always)] + pub fn epint4(&self) -> EPINT4_R { + EPINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pipe 5 Interrupt"] + #[inline(always)] + pub fn epint5(&self) -> EPINT5_R { + EPINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pipe 6 Interrupt"] + #[inline(always)] + pub fn epint6(&self) -> EPINT6_R { + EPINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pipe 7 Interrupt"] + #[inline(always)] + pub fn epint7(&self) -> EPINT7_R { + EPINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "HOST Pipe Interrupt Summary\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pintsmry](index.html) module"] +pub struct PINTSMRY_SPEC; +impl crate::RegisterSpec for PINTSMRY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pintsmry::R](R) reader structure"] +impl crate::Readable for PINTSMRY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PINTSMRY to value 0"] +impl crate::Resettable for PINTSMRY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/qosctrl.rs b/pac/atsamda1j/src/usb/host/qosctrl.rs new file mode 100644 index 00000000000..86b85a16067 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/qosctrl.rs @@ -0,0 +1,290 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Configuration Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `CQOS` reader - Configuration Quality of Service"] +pub struct CQOS_R(crate::FieldReader); +impl CQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CQOS_A { + match self.bits { + 0 => CQOS_A::DISABLE, + 1 => CQOS_A::LOW, + 2 => CQOS_A::MEDIUM, + 3 => CQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == CQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == CQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == CQOS_A::HIGH + } +} +impl core::ops::Deref for CQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CQOS` writer - Configuration Quality of Service"] +pub struct CQOS_W<'a> { + w: &'a mut W, +} +impl<'a> CQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(CQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(CQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(CQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Data Quality of Service\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&self) -> CQOS_R { + CQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&mut self) -> CQOS_W { + CQOS_W { w: self } + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB Quality Of Service\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x05"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamda1j/src/usb/host/status.rs b/pac/atsamda1j/src/usb/host/status.rs new file mode 100644 index 00000000000..45cf612fdac --- /dev/null +++ b/pac/atsamda1j/src/usb/host/status.rs @@ -0,0 +1,140 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPEED` reader - Speed Status"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Status"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Field `LINESTATE` reader - USB Line State Status"] +pub struct LINESTATE_R(crate::FieldReader); +impl LINESTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINESTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINESTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINESTATE` writer - USB Line State Status"] +pub struct LINESTATE_W<'a> { + w: &'a mut W, +} +impl<'a> LINESTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&self) -> LINESTATE_R { + LINESTATE_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&mut self) -> LINESTATE_W { + LINESTATE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "HOST Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/usb/host/syncbusy.rs b/pac/atsamda1j/src/usb/host/syncbusy.rs new file mode 100644 index 00000000000..5f22af98954 --- /dev/null +++ b/pac/atsamda1j/src/usb/host/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/wdt.rs b/pac/atsamda1j/src/wdt.rs new file mode 100644 index 00000000000..0c5da61ba13 --- /dev/null +++ b/pac/atsamda1j/src/wdt.rs @@ -0,0 +1,53 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamda1j/src/wdt/clear.rs b/pac/atsamda1j/src/wdt/clear.rs new file mode 100644 index 00000000000..61ee21f3246 --- /dev/null +++ b/pac/atsamda1j/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/wdt/config.rs b/pac/atsamda1j/src/wdt/config.rs new file mode 100644 index 00000000000..b87e8a0a9bd --- /dev/null +++ b/pac/atsamda1j/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::_8), + 1 => Some(PER_A::_16), + 2 => Some(PER_A::_32), + 3 => Some(PER_A::_64), + 4 => Some(PER_A::_128), + 5 => Some(PER_A::_256), + 6 => Some(PER_A::_512), + 7 => Some(PER_A::_1K), + 8 => Some(PER_A::_2K), + 9 => Some(PER_A::_4K), + 10 => Some(PER_A::_8K), + 11 => Some(PER_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PER_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PER_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PER_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PER_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PER_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PER_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PER_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == PER_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == PER_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == PER_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == PER_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == PER_A::_16K + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PER_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PER_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PER_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PER_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PER_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PER_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PER_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(PER_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(PER_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(PER_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(PER_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(PER_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::_8), + 1 => Some(WINDOW_A::_16), + 2 => Some(WINDOW_A::_32), + 3 => Some(WINDOW_A::_64), + 4 => Some(WINDOW_A::_128), + 5 => Some(WINDOW_A::_256), + 6 => Some(WINDOW_A::_512), + 7 => Some(WINDOW_A::_1K), + 8 => Some(WINDOW_A::_2K), + 9 => Some(WINDOW_A::_4K), + 10 => Some(WINDOW_A::_8K), + 11 => Some(WINDOW_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == WINDOW_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == WINDOW_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == WINDOW_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == WINDOW_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == WINDOW_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == WINDOW_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == WINDOW_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == WINDOW_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == WINDOW_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == WINDOW_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == WINDOW_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == WINDOW_A::_16K + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(WINDOW_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(WINDOW_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(WINDOW_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(WINDOW_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(WINDOW_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(WINDOW_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(WINDOW_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(WINDOW_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(WINDOW_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(WINDOW_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(WINDOW_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(WINDOW_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamda1j/src/wdt/ctrl.rs b/pac/atsamda1j/src/wdt/ctrl.rs new file mode 100644 index 00000000000..d312316d919 --- /dev/null +++ b/pac/atsamda1j/src/wdt/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/wdt/ewctrl.rs b/pac/atsamda1j/src/wdt/ewctrl.rs new file mode 100644 index 00000000000..6c7e31273c3 --- /dev/null +++ b/pac/atsamda1j/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + _8 = 0, + #[doc = "1: 16 clock cycles"] + _16 = 1, + #[doc = "2: 32 clock cycles"] + _32 = 2, + #[doc = "3: 64 clock cycles"] + _64 = 3, + #[doc = "4: 128 clock cycles"] + _128 = 4, + #[doc = "5: 256 clock cycles"] + _256 = 5, + #[doc = "6: 512 clock cycles"] + _512 = 6, + #[doc = "7: 1024 clock cycles"] + _1K = 7, + #[doc = "8: 2048 clock cycles"] + _2K = 8, + #[doc = "9: 4096 clock cycles"] + _4K = 9, + #[doc = "10: 8192 clock cycles"] + _8K = 10, + #[doc = "11: 16384 clock cycles"] + _16K = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::_8), + 1 => Some(EWOFFSET_A::_16), + 2 => Some(EWOFFSET_A::_32), + 3 => Some(EWOFFSET_A::_64), + 4 => Some(EWOFFSET_A::_128), + 5 => Some(EWOFFSET_A::_256), + 6 => Some(EWOFFSET_A::_512), + 7 => Some(EWOFFSET_A::_1K), + 8 => Some(EWOFFSET_A::_2K), + 9 => Some(EWOFFSET_A::_4K), + 10 => Some(EWOFFSET_A::_8K), + 11 => Some(EWOFFSET_A::_16K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == EWOFFSET_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == EWOFFSET_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == EWOFFSET_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == EWOFFSET_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == EWOFFSET_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == EWOFFSET_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == EWOFFSET_A::_512 + } + #[doc = "Checks if the value of the field is `_1K`"] + #[inline(always)] + pub fn is_1k(&self) -> bool { + **self == EWOFFSET_A::_1K + } + #[doc = "Checks if the value of the field is `_2K`"] + #[inline(always)] + pub fn is_2k(&self) -> bool { + **self == EWOFFSET_A::_2K + } + #[doc = "Checks if the value of the field is `_4K`"] + #[inline(always)] + pub fn is_4k(&self) -> bool { + **self == EWOFFSET_A::_4K + } + #[doc = "Checks if the value of the field is `_8K`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + **self == EWOFFSET_A::_8K + } + #[doc = "Checks if the value of the field is `_16K`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + **self == EWOFFSET_A::_16K + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(EWOFFSET_A::_8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(EWOFFSET_A::_16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(EWOFFSET_A::_32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(EWOFFSET_A::_64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(EWOFFSET_A::_128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(EWOFFSET_A::_256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(EWOFFSET_A::_512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn _1k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_1K) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn _2k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_2K) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn _4k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_4K) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn _8k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_8K) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn _16k(self) -> &'a mut W { + self.variant(EWOFFSET_A::_16K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamda1j/src/wdt/intenclr.rs b/pac/atsamda1j/src/wdt/intenclr.rs new file mode 100644 index 00000000000..ed4021f96cc --- /dev/null +++ b/pac/atsamda1j/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/wdt/intenset.rs b/pac/atsamda1j/src/wdt/intenset.rs new file mode 100644 index 00000000000..5a0928ff053 --- /dev/null +++ b/pac/atsamda1j/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/wdt/intflag.rs b/pac/atsamda1j/src/wdt/intflag.rs new file mode 100644 index 00000000000..f2c9b858a19 --- /dev/null +++ b/pac/atsamda1j/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamda1j/src/wdt/status.rs b/pac/atsamda1j/src/wdt/status.rs new file mode 100644 index 00000000000..012fa348a50 --- /dev/null +++ b/pac/atsamda1j/src/wdt/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYNCBUSY` reader - Synchronization Busy"] +pub struct SYNCBUSY_R(crate::FieldReader); +impl SYNCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYNCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYNCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Synchronization Busy"] + #[inline(always)] + pub fn syncbusy(&self) -> SYNCBUSY_R { + SYNCBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/svd/ATSAMDA1E14B.svd b/svd/ATSAMDA1E14B.svd new file mode 100644 index 00000000000..c26749a38f1 --- /dev/null +++ b/svd/ATSAMDA1E14B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1E14B + SAMDA1 + 0 + Microchip ATSAMDA1E14B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x1001156C + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x80 + registers + + + + 1 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1E15B.svd b/svd/ATSAMDA1E15B.svd new file mode 100644 index 00000000000..381cdd2ef1c --- /dev/null +++ b/svd/ATSAMDA1E15B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1E15B + SAMDA1 + 0 + Microchip ATSAMDA1E15B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x1001156B + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x80 + registers + + + + 1 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1E16B.svd b/svd/ATSAMDA1E16B.svd new file mode 100644 index 00000000000..865c45755fb --- /dev/null +++ b/svd/ATSAMDA1E16B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1E16B + SAMDA1 + 0 + Microchip ATSAMDA1E16B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x1001156A + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x80 + registers + + + + 1 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1G14B.svd b/svd/ATSAMDA1G14B.svd new file mode 100644 index 00000000000..2c67af4679c --- /dev/null +++ b/svd/ATSAMDA1G14B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1G14B + SAMDA1 + 0 + Microchip ATSAMDA1G14B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x10011569 + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1G15B.svd b/svd/ATSAMDA1G15B.svd new file mode 100644 index 00000000000..9df32a05097 --- /dev/null +++ b/svd/ATSAMDA1G15B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1G15B + SAMDA1 + 0 + Microchip ATSAMDA1G15B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x10011568 + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1G16B.svd b/svd/ATSAMDA1G16B.svd new file mode 100644 index 00000000000..e051f267950 --- /dev/null +++ b/svd/ATSAMDA1G16B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1G16B + SAMDA1 + 0 + Microchip ATSAMDA1G16B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x10011567 + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1J14B.svd b/svd/ATSAMDA1J14B.svd new file mode 100644 index 00000000000..4b53323044f --- /dev/null +++ b/svd/ATSAMDA1J14B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1J14B + SAMDA1 + 0 + Microchip ATSAMDA1J14B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x10011566 + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1J15B.svd b/svd/ATSAMDA1J15B.svd new file mode 100644 index 00000000000..6fb7632afd2 --- /dev/null +++ b/svd/ATSAMDA1J15B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1J15B + SAMDA1 + 0 + Microchip ATSAMDA1J15B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x10011565 + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMDA1J16B.svd b/svd/ATSAMDA1J16B.svd new file mode 100644 index 00000000000..8bfb135f070 --- /dev/null +++ b/svd/ATSAMDA1J16B.svd @@ -0,0 +1,22165 @@ + + + + Microchip Technology + MCHP + ATSAMDA1J16B + SAMDA1 + 0 + Microchip ATSAMDA1J16B Microcontroller + + CM0+ + r0p0 + selectable + false + false + true + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22051.1.2 + Analog Comparators + AC + AC_ + 0x42004400 + + 0 + 0x22 + registers + + + AC + 24 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + LPMUX + Low-Power Mux + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input + 9 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x8 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x9 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + STATUSC + Status C + 0xA + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + WINCTRL + Window Control + 0xC + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 0 + 1 + + + SINGLE + Single-Shot Mode + 1 + 1 + + + SPEED + Speed Selection + 2 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 1 + + + + + INTSEL + Interrupt Selection + 5 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 2 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + OUT + Output + 16 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + HYST + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0x20 + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + + + ADC + U22041.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004000 + + 0 + 0x2B + registers + + + ADC + 23 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INT1V + 1.0V voltage reference + 0x0 + + + INTVCC0 + 1/1.48 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA (only for VDDANA > 2.0V) + 0x2 + + + AREFA + External reference A + 0x3 + + + AREFB + External reference B + 0x4 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x2 + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sampling Time Control + 0x3 + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + + + CTRLB + Control B + 0x4 + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enabled + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV4 + Peripheral clock divided by 4 + 0x0 + + + DIV8 + Peripheral clock divided by 8 + 0x1 + + + DIV16 + Peripheral clock divided by 16 + 0x2 + + + DIV32 + Peripheral clock divided by 32 + 0x3 + + + DIV64 + Peripheral clock divided by 64 + 0x4 + + + DIV128 + Peripheral clock divided by 128 + 0x5 + + + DIV256 + Peripheral clock divided by 256 + 0x6 + + + DIV512 + Peripheral clock divided by 512 + 0x7 + + + + + + + WINCTRL + Window Monitor Control + 0x8 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + Mode 1: RESULT > WINLT + 0x1 + + + MODE2 + Mode 2: RESULT < WINUT + 0x2 + + + MODE3 + Mode 3: WINLT < RESULT < WINUT + 0x3 + + + MODE4 + Mode 4: !(WINLT < RESULT < WINUT) + 0x4 + + + + + + + SWTRIG + Software Trigger + 0xC + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + ADC Start Conversion + 1 + 1 + + + + + INPUTCTRL + Input Control + 0x10 + 32 + 0x00000000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + PIN8 + ADC AIN8 Pin + 0x8 + + + PIN9 + ADC AIN9 Pin + 0x9 + + + PIN10 + ADC AIN10 Pin + 0xA + + + PIN11 + ADC AIN11 Pin + 0xB + + + PIN12 + ADC AIN12 Pin + 0xC + + + PIN13 + ADC AIN13 Pin + 0xD + + + PIN14 + ADC AIN14 Pin + 0xE + + + PIN15 + ADC AIN15 Pin + 0xF + + + PIN16 + ADC AIN16 Pin + 0x10 + + + PIN17 + ADC AIN17 Pin + 0x11 + + + PIN18 + ADC AIN18 Pin + 0x12 + + + PIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Reference + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + PIN0 + ADC AIN0 Pin + 0x0 + + + PIN1 + ADC AIN1 Pin + 0x1 + + + PIN2 + ADC AIN2 Pin + 0x2 + + + PIN3 + ADC AIN3 Pin + 0x3 + + + PIN4 + ADC AIN4 Pin + 0x4 + + + PIN5 + ADC AIN5 Pin + 0x5 + + + PIN6 + ADC AIN6 Pin + 0x6 + + + PIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + IOGND + I/O Ground + 0x19 + + + + + INPUTSCAN + Number of Input Channels Included in Scan + 16 + 4 + + + INPUTOFFSET + Positive Mux Setting Offset + 20 + 4 + + + GAIN + Gain Factor Selection + 24 + 4 + + GAINSelect + + 1X + 1x + 0x0 + + + 2X + 2x + 0x1 + + + 4X + 4x + 0x2 + + + 8X + 8x + 0x3 + + + 16X + 16x + 0x4 + + + DIV2 + 1/2x + 0xF + + + + + + + EVCTRL + Event Control + 0x14 + 8 + 0x00 + + + STARTEI + Start Conversion Event In + 0 + 1 + + + SYNCEI + Synchronization Event In + 1 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x16 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x17 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + + + STATUS + Status + 0x19 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + RESULT + Result + 0x1A + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + WINLT + Window Monitor Lower Threshold + 0x1C + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x20 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x24 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x26 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + CALIB + Calibration + 0x28 + 16 + 0x0000 + + + LINEARITY_CAL + Linearity Calibration Value + 0 + 8 + + + BIAS_CAL + Bias Calibration Value + 8 + 3 + + + + + DBGCTRL + Debug Control + 0x2A + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + DAC + U22141.1.0 + Digital Analog Converter + DAC + DAC_ + 0x42004800 + + 0 + 0xE + registers + + + DAC + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 2 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + EOEN + External Output Enable + 0 + 1 + + + IOEN + Internal Output Enable + 1 + 1 + + + LEFTADJ + Left Adjusted Data + 2 + 1 + + + VPD + Voltage Pump Disable + 3 + 1 + + + BDWP + Bypass DATABUF Write Protection + 4 + 1 + + + REFSEL + Reference Selection + 6 + 2 + + REFSELSelect + + INT1V + Internal 1.0V reference + 0 + + + AVCC + AVCC + 1 + + + VREFP + External reference + 2 + + + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input + 0 + 1 + + + EMPTYEO + Data Buffer Empty Event Output + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + UNDERRUN + Underrun Interrupt Enable + 0 + 1 + + + EMPTY + Data Buffer Empty Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + UNDERRUN + Underrun + 0 + 1 + + + EMPTY + Data Buffer Empty + 1 + 1 + + + SYNCRDY + Synchronization Ready + 2 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + DATA + Data + 0x8 + 16 + 0x0000 + + + DATA + Data value to be converted + 0 + 16 + + + + + DATABUF + Data Buffer + 0xC + 16 + 0x0000 + + + DATABUF + Data Buffer + 0 + 16 + + + + + + + DMAC + U22231.1.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41004800 + + 0 + 0x50 + registers + + + DMAC + 6 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + Byte bus access + 0x0 + + + HWORD + Half-word bus access + 0x1 + + + WORD + Word bus access + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x15 + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + 0x00000000 + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + 0x00000000 + + + PENDCH0 + Pending Channel 0 + 0 + 1 + + + PENDCH1 + Pending Channel 1 + 1 + 1 + + + PENDCH2 + Pending Channel 2 + 2 + 1 + + + PENDCH3 + Pending Channel 3 + 3 + 1 + + + PENDCH4 + Pending Channel 4 + 4 + 1 + + + PENDCH5 + Pending Channel 5 + 5 + 1 + + + PENDCH6 + Pending Channel 6 + 6 + 1 + + + PENDCH7 + Pending Channel 7 + 7 + 1 + + + PENDCH8 + Pending Channel 8 + 8 + 1 + + + PENDCH9 + Pending Channel 9 + 9 + 1 + + + PENDCH10 + Pending Channel 10 + 10 + 1 + + + PENDCH11 + Pending Channel 11 + 11 + 1 + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + 0x00000000 + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + + + ID + Active Channel ID + 8 + 5 + + + ABUSY + Active Channel Busy + 15 + 1 + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + 0x00000000 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + 0x00000000 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + 0x00 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + 0x00 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + 0x00000000 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + LVLSelect + + LVL0 + Channel Priority Level 0 + 0x00 + + + LVL1 + Channel Priority Level 1 + 0x01 + + + LVL2 + Channel Priority Level 2 + 0x02 + + + LVL3 + Channel Priority Level 3 + 0x03 + + + + + TRIGSRC + Peripheral Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x00 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + 0x00 + + + TERR + Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + 0x00 + + + TERR + Transfer Error + 0 + 1 + + + TCMPL + Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + 0x00 + + + PEND + Channel Pending + 0 + 1 + + + BUSY + Channel Busy + 1 + 1 + + + FERR + Fetch Error + 2 + 1 + + + + + + + DSU + U22092.0.3 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + CRC + 32-bit Cyclic Redundancy Check + 2 + 1 + + + MBIST + Memory Built-In Self-Test + 3 + 1 + + + CE + Chip Erase + 4 + 1 + + + + + STATUSA + Status A + 0x1 + 8 + 0x00 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x2 + 8 + read-only + 0x10 + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x4 + 32 + 0x00000000 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x8 + 32 + 0x00000000 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0xC + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + 2 + 4 + DCC[%s] + Debug Communication Channel n + 0x10 + 32 + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x18 + 32 + read-only + 0x10011564 + + + DEVSEL + Device Select + 0 + 8 + + + REVISION + Revision + 8 + 4 + + + DIE + Die Identification + 12 + 4 + + + SERIES + Product Series + 16 + 6 + + + FAMILY + Product Family + 23 + 5 + + + PROCESSOR + Processor + 28 + 4 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + + + ADDOFF + Address Offset + 12 + 20 + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00003002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + 0x00000000 + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + 0x00000000 + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + 0x00000000 + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB Count + 4 + 4 + + + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22171.0.1 + External Interrupt Controller + EIC + EIC_ + 0x40001800 + + 0 + 0x20 + registers + + + EIC + 4 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x2 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x3 + 8 + 0x00 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + EVCTRL + Event Control + 0x4 + 32 + 0x00000000 + + + EXTINTEO0 + External Interrupt 0 Event Output Enable + 0 + 1 + + + EXTINTEO1 + External Interrupt 1 Event Output Enable + 1 + 1 + + + EXTINTEO2 + External Interrupt 2 Event Output Enable + 2 + 1 + + + EXTINTEO3 + External Interrupt 3 Event Output Enable + 3 + 1 + + + EXTINTEO4 + External Interrupt 4 Event Output Enable + 4 + 1 + + + EXTINTEO5 + External Interrupt 5 Event Output Enable + 5 + 1 + + + EXTINTEO6 + External Interrupt 6 Event Output Enable + 6 + 1 + + + EXTINTEO7 + External Interrupt 7 Event Output Enable + 7 + 1 + + + EXTINTEO8 + External Interrupt 8 Event Output Enable + 8 + 1 + + + EXTINTEO9 + External Interrupt 9 Event Output Enable + 9 + 1 + + + EXTINTEO10 + External Interrupt 10 Event Output Enable + 10 + 1 + + + EXTINTEO11 + External Interrupt 11 Event Output Enable + 11 + 1 + + + EXTINTEO12 + External Interrupt 12 Event Output Enable + 12 + 1 + + + EXTINTEO13 + External Interrupt 13 Event Output Enable + 13 + 1 + + + EXTINTEO14 + External Interrupt 14 Event Output Enable + 14 + 1 + + + EXTINTEO15 + External Interrupt 15 Event Output Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xC + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 Enable + 0 + 1 + + + EXTINT1 + External Interrupt 1 Enable + 1 + 1 + + + EXTINT2 + External Interrupt 2 Enable + 2 + 1 + + + EXTINT3 + External Interrupt 3 Enable + 3 + 1 + + + EXTINT4 + External Interrupt 4 Enable + 4 + 1 + + + EXTINT5 + External Interrupt 5 Enable + 5 + 1 + + + EXTINT6 + External Interrupt 6 Enable + 6 + 1 + + + EXTINT7 + External Interrupt 7 Enable + 7 + 1 + + + EXTINT8 + External Interrupt 8 Enable + 8 + 1 + + + EXTINT9 + External Interrupt 9 Enable + 9 + 1 + + + EXTINT10 + External Interrupt 10 Enable + 10 + 1 + + + EXTINT11 + External Interrupt 11 Enable + 11 + 1 + + + EXTINT12 + External Interrupt 12 Enable + 12 + 1 + + + EXTINT13 + External Interrupt 13 Enable + 13 + 1 + + + EXTINT14 + External Interrupt 14 Enable + 14 + 1 + + + EXTINT15 + External Interrupt 15 Enable + 15 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 32 + 0x00000000 + + + EXTINT0 + External Interrupt 0 + 0 + 1 + + + EXTINT1 + External Interrupt 1 + 1 + 1 + + + EXTINT2 + External Interrupt 2 + 2 + 1 + + + EXTINT3 + External Interrupt 3 + 3 + 1 + + + EXTINT4 + External Interrupt 4 + 4 + 1 + + + EXTINT5 + External Interrupt 5 + 5 + 1 + + + EXTINT6 + External Interrupt 6 + 6 + 1 + + + EXTINT7 + External Interrupt 7 + 7 + 1 + + + EXTINT8 + External Interrupt 8 + 8 + 1 + + + EXTINT9 + External Interrupt 9 + 9 + 1 + + + EXTINT10 + External Interrupt 10 + 10 + 1 + + + EXTINT11 + External Interrupt 11 + 11 + 1 + + + EXTINT12 + External Interrupt 12 + 12 + 1 + + + EXTINT13 + External Interrupt 13 + 13 + 1 + + + EXTINT14 + External Interrupt 14 + 14 + 1 + + + EXTINT15 + External Interrupt 15 + 15 + 1 + + + + + WAKEUP + Wake-Up Enable + 0x14 + 32 + 0x00000000 + + + WAKEUPEN0 + External Interrupt 0 Wake-up Enable + 0 + 1 + + + WAKEUPEN1 + External Interrupt 1 Wake-up Enable + 1 + 1 + + + WAKEUPEN2 + External Interrupt 2 Wake-up Enable + 2 + 1 + + + WAKEUPEN3 + External Interrupt 3 Wake-up Enable + 3 + 1 + + + WAKEUPEN4 + External Interrupt 4 Wake-up Enable + 4 + 1 + + + WAKEUPEN5 + External Interrupt 5 Wake-up Enable + 5 + 1 + + + WAKEUPEN6 + External Interrupt 6 Wake-up Enable + 6 + 1 + + + WAKEUPEN7 + External Interrupt 7 Wake-up Enable + 7 + 1 + + + WAKEUPEN8 + External Interrupt 8 Wake-up Enable + 8 + 1 + + + WAKEUPEN9 + External Interrupt 9 Wake-up Enable + 9 + 1 + + + WAKEUPEN10 + External Interrupt 10 Wake-up Enable + 10 + 1 + + + WAKEUPEN11 + External Interrupt 11 Wake-up Enable + 11 + 1 + + + WAKEUPEN12 + External Interrupt 12 Wake-up Enable + 12 + 1 + + + WAKEUPEN13 + External Interrupt 13 Wake-up Enable + 13 + 1 + + + WAKEUPEN14 + External Interrupt 14 Wake-up Enable + 14 + 1 + + + WAKEUPEN15 + External Interrupt 15 Wake-up Enable + 15 + 1 + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x18 + 32 + 0x00000000 + + + SENSE0 + Input Sense 0 Configuration + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + FILTEN0 + Filter 0 Enable + 3 + 1 + + + SENSE1 + Input Sense 1 Configuration + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter 1 Enable + 7 + 1 + + + SENSE2 + Input Sense 2 Configuration + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN2 + Filter 2 Enable + 11 + 1 + + + SENSE3 + Input Sense 3 Configuration + 12 + 3 + + SENSE3Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN3 + Filter 3 Enable + 15 + 1 + + + SENSE4 + Input Sense 4 Configuration + 16 + 3 + + SENSE4Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter 4 Enable + 19 + 1 + + + SENSE5 + Input Sense 5 Configuration + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter 5 Enable + 23 + 1 + + + SENSE6 + Input Sense 6 Configuration + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter 6 Enable + 27 + 1 + + + SENSE7 + Input Sense 7 Configuration + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter 7 Enable + 31 + 1 + + + + + + + EVSYS + U22081.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000400 + + 0 + 0x1C + registers + + + EVSYS + 8 + + + + CTRL + Control + 0x0 + 8 + write-only + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + GCLKREQ + Generic Clock Requests + 4 + 1 + + + + + CHANNEL + Channel + 0x4 + 32 + 0x00000000 + + + CHANNEL + Channel Selection + 0 + 4 + + + SWEVT + Software Event + 8 + 1 + + + EVGEN + Event Generator Selection + 16 + 7 + + + PATH + Path Selection + 24 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 26 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + + + USER + User Multiplexer + 0x8 + 16 + 0x0000 + + + USER + User Multiplexer Selection + 0 + 5 + + + CHANNEL + Channel Event Selection + 8 + 5 + + CHANNELSelect + + 0 + No Channel Output Selected + 0 + + + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x000F00FF + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + CHBUSY0 + Channel 0 Busy + 8 + 1 + + + CHBUSY1 + Channel 1 Busy + 9 + 1 + + + CHBUSY2 + Channel 2 Busy + 10 + 1 + + + CHBUSY3 + Channel 3 Busy + 11 + 1 + + + CHBUSY4 + Channel 4 Busy + 12 + 1 + + + CHBUSY5 + Channel 5 Busy + 13 + 1 + + + CHBUSY6 + Channel 6 Busy + 14 + 1 + + + CHBUSY7 + Channel 7 Busy + 15 + 1 + + + USRRDY8 + Channel 8 User Ready + 16 + 1 + + + USRRDY9 + Channel 9 User Ready + 17 + 1 + + + USRRDY10 + Channel 10 User Ready + 18 + 1 + + + USRRDY11 + Channel 11 User Ready + 19 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 8 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 9 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 10 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 11 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 12 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 13 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 14 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 15 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 16 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 17 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 18 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 19 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 8 + 1 + + + EVD1 + Channel 1 Event Detection + 9 + 1 + + + EVD2 + Channel 2 Event Detection + 10 + 1 + + + EVD3 + Channel 3 Event Detection + 11 + 1 + + + EVD4 + Channel 4 Event Detection + 12 + 1 + + + EVD5 + Channel 5 Event Detection + 13 + 1 + + + EVD6 + Channel 6 Event Detection + 14 + 1 + + + EVD7 + Channel 7 Event Detection + 15 + 1 + + + OVR8 + Channel 8 Overrun + 16 + 1 + + + OVR9 + Channel 9 Overrun + 17 + 1 + + + OVR10 + Channel 10 Overrun + 18 + 1 + + + OVR11 + Channel 11 Overrun + 19 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + + + GCLK + U21022.1.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40000C00 + + 0 + 0xC + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + STATUS + Status + 0x1 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy Status + 7 + 1 + + + + + CLKCTRL + Generic Clock Control + 0x2 + 16 + 0x0000 + + + ID + Generic Clock Selection ID + 0 + 6 + + IDSelect + + DFLL48 + DFLL48 + 0x0 + + + FDPLL + FDPLL + 0x1 + + + FDPLL32K + FDPLL32K + 0x2 + + + WDT + WDT + 0x3 + + + RTC + RTC + 0x4 + + + EIC + EIC + 0x5 + + + USB + USB + 0x6 + + + EVSYS_0 + EVSYS_0 + 0x7 + + + EVSYS_1 + EVSYS_1 + 0x8 + + + EVSYS_2 + EVSYS_2 + 0x9 + + + EVSYS_3 + EVSYS_3 + 0xA + + + EVSYS_4 + EVSYS_4 + 0xB + + + EVSYS_5 + EVSYS_5 + 0xC + + + EVSYS_6 + EVSYS_6 + 0xD + + + EVSYS_7 + EVSYS_7 + 0xE + + + EVSYS_8 + EVSYS_8 + 0xF + + + EVSYS_9 + EVSYS_9 + 0x10 + + + EVSYS_10 + EVSYS_10 + 0x11 + + + EVSYS_11 + EVSYS_11 + 0x12 + + + SERCOMX_SLOW + SERCOMX_SLOW + 0x13 + + + SERCOM0_CORE + SERCOM0_CORE + 0x14 + + + SERCOM1_CORE + SERCOM1_CORE + 0x15 + + + SERCOM2_CORE + SERCOM2_CORE + 0x16 + + + SERCOM3_CORE + SERCOM3_CORE + 0x17 + + + SERCOM4_CORE + SERCOM4_CORE + 0x18 + + + SERCOM5_CORE + SERCOM5_CORE + 0x19 + + + TCC0_TCC1 + TCC0_TCC1 + 0x1A + + + TCC2_TC3 + TCC2_TC3 + 0x1B + + + TC4_TC5 + TC4_TC5 + 0x1C + + + TC6_TC7 + TC6_TC7 + 0x1D + + + ADC + ADC + 0x1E + + + AC_DIG + AC_DIG + 0x1F + + + AC_ANA + AC_ANA + 0x20 + + + DAC + DAC + 0x21 + + + I2S_0 + I2S_0 + 0x23 + + + I2S_1 + I2S_1 + 0x24 + + + + + GEN + Generic Clock Generator + 8 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CLKEN + Clock Enable + 14 + 1 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + GENCTRL + Generic Clock Generator Control + 0x4 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + SRC + Source Select + 8 + 5 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC8M + OSC8M oscillator output + 6 + + + DFLL48M + DFLL48M output + 7 + + + DPLL96M + DPLL96M output + 8 + + + + + GENEN + Generic Clock Generator Enable + 16 + 1 + + + IDC + Improve Duty Cycle + 17 + 1 + + + OOV + Output Off Value + 18 + 1 + + + OE + Output Enable + 19 + 1 + + + DIVSEL + Divide Selection + 20 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 21 + 1 + + + + + GENDIV + Generic Clock Generator Division + 0x8 + 32 + 0x00000000 + + + ID + Generic Clock Generator Selection + 0 + 4 + + + DIV + Division Factor + 8 + 16 + + + + + + + SBMATRIX + I76382.1.2 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x41007000 + + 0 + 0x168 + registers + + + + 16 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + I2S + U22241.1.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x42005000 + + 0 + 0x38 + registers + + + I2S + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + SEREN0 + Serializer 0 Enable + 4 + 1 + + + SEREN1 + Serializer 1 Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 11 + 1 + + + SCKSEL + Serial Clock Select + 12 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + MCKSEL + Master Clock Select + 16 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 18 + 1 + + + MCKDIV + Master Clock Division Factor + 19 + 5 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 5 + + + FSOUTINV + Frame Sync Output Invert + 29 + 1 + + + SCKOUTINV + Serial Clock Output Invert + 30 + 1 + + + MCKOUTINV + Master Clock Output Invert + 31 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + SEREN0 + Serializer 0 Enable Synchronization Status + 4 + 1 + + + SEREN1 + Serializer 1 Enable Synchronization Status + 5 + 1 + + + DATA0 + Data 0 Synchronization Status + 8 + 1 + + + DATA1 + Data 1 Synchronization Status + 9 + 1 + + + + + 2 + 4 + SERCTRL[%s] + Serializer n Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + 2 + 4 + DATA[%s] + Data n + 0x30 + 32 + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41006000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + CoreSight + 0xFD0 + 32 + read-only + + + PID5 + CoreSight + 0xFD4 + 32 + read-only + + + PID6 + CoreSight + 0xFD8 + 32 + read-only + + + PID7 + CoreSight + 0xFDC + 32 + read-only + + + PID0 + CoreSight + 0xFE0 + 32 + read-only + + + PID1 + CoreSight + 0xFE4 + 32 + read-only + + + PID2 + CoreSight + 0xFE8 + 32 + read-only + + + PID3 + CoreSight + 0xFEC + 32 + read-only + + + CID0 + CoreSight + 0xFF0 + 32 + read-only + + + CID1 + CoreSight + 0xFF4 + 32 + read-only + + + CID2 + CoreSight + 0xFF8 + 32 + read-only + + + CID3 + CoreSight + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22072.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x22 + registers + + + NVMCTRL + 5 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + + + PAC0 + U22111.0.1 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x8 + registers + + + + WPCLR + Write Protection Clear + 0x0 + 32 + 0x00000000 + + + WP + Write Protection Clear + 1 + 31 + + + + + WPSET + Write Protection Set + 0x4 + 32 + 0x00000000 + + + WP + Write Protection Set + 1 + 31 + + + + + + + PAC1 + 0x41000000 + + + PAC2 + 0x42000000 + + + PM + U22062.1.2 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x39 + registers + + + PM + 0 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SLEEP + Sleep Mode + 0x1 + 8 + 0x00 + + + IDLE + Idle Mode Configuration + 0 + 2 + + IDLESelect + + CPU + The CPU clock domain is stopped + 0 + + + AHB + The CPU and AHB clock domains are stopped + 1 + + + APB + The CPU, AHB and APB clock domains are stopped + 2 + + + + + + + EXTCTRL + External Reset Controller + 0x2 + 8 + 0x00 + + + SETDIS + External Reset Disable + 0 + 1 + + + + + CPUSEL + CPU Clock Select + 0x8 + 8 + 0x00 + + + CPUDIV + CPU Prescaler Selection + 0 + 3 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBASEL + APBA Clock Select + 0x9 + 8 + 0x00 + + + APBADIV + APBA Prescaler Selection + 0 + 3 + + APBADIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBBSEL + APBB Clock Select + 0xA + 8 + 0x00 + + + APBBDIV + APBB Prescaler Selection + 0 + 3 + + APBBDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + APBCSEL + APBC Clock Select + 0xB + 8 + 0x00 + + + APBCDIV + APBC Prescaler Selection + 0 + 3 + + APBCDIVSelect + + DIV1 + Divide by 1 + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + + + + + AHBMASK + AHB Mask + 0x14 + 32 + 0x0000007F + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 4 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 5 + 1 + + + USB_ + USB AHB Clock Mask + 6 + 1 + + + + + APBAMASK + APBA Mask + 0x18 + 32 + 0x0000007F + + + PAC0_ + PAC0 APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + SYSCTRL_ + SYSCTRL APB Clock Enable + 2 + 1 + + + GCLK_ + GCLK APB Clock Enable + 3 + 1 + + + WDT_ + WDT APB Clock Enable + 4 + 1 + + + RTC_ + RTC APB Clock Enable + 5 + 1 + + + EIC_ + EIC APB Clock Enable + 6 + 1 + + + + + APBBMASK + APBB Mask + 0x1C + 32 + 0x0000007F + + + PAC1_ + PAC1 APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + DMAC_ + DMAC APB Clock Enable + 4 + 1 + + + USB_ + USB APB Clock Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + + + APBCMASK + APBC Mask + 0x20 + 32 + 0x00010000 + + + PAC2_ + PAC2 APB Clock Enable + 0 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 1 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 2 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 3 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 4 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 5 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 6 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 7 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 8 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 9 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + TC4_ + TC4 APB Clock Enable + 12 + 1 + + + TC5_ + TC5 APB Clock Enable + 13 + 1 + + + TC6_ + TC6 APB Clock Enable + 14 + 1 + + + TC7_ + TC7 APB Clock Enable + 15 + 1 + + + ADC_ + ADC APB Clock Enable + 16 + 1 + + + AC_ + AC APB Clock Enable + 17 + 1 + + + DAC_ + DAC APB Clock Enable + 18 + 1 + + + PTC_ + PTC APB Clock Enable + 19 + 1 + + + I2S_ + I2S APB Clock Enable + 20 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x34 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x35 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x36 + 8 + 0x00 + + + CKRDY + Clock Ready + 0 + 1 + + + + + RCAUSE + Reset Cause + 0x38 + 8 + read-only + 0x01 + + + POR + Power On Reset + 0 + 1 + + + BOD12 + Brown Out 12 Detector Reset + 1 + 1 + + + BOD33 + Brown Out 33 Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + PORT + U22101.0.0 + Port Module + PORT + PORT_ + 0x41004400 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + Port Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + Port Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + Port Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + Port Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + Port Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing Even + 0 + 4 + + PMUXESelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + PMUXO + Peripheral Multiplexing Odd + 4 + 4 + + PMUXOSelect + + A + Peripheral function A selected + 0x0 + + + B + Peripheral function B selected + 0x1 + + + C + Peripheral function C selected + 0x2 + + + D + Peripheral function D selected + 0x3 + + + E + Peripheral function E selected + 0x4 + + + F + Peripheral function F selected + 0x5 + + + G + Peripheral function G selected + 0x6 + + + H + Peripheral function H selected + 0x7 + + + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22151.0.4 + Peripheral Touch Controller + PTC + PTC_ + 0x42004C00 + + 0 + 0x1 + reserved + + + PTC + 26 + + + + RTC + U22021.0.1 + Real-Time Counter + RTC + RTC_ + 0x40001400 + + 0 + 0x1D + registers + + + RTC + 3 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRL + MODE0 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x18 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRL + MODE1 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + CMP0 + Compare 0 Interrupt Enable + 0 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + CMP0 + Compare 0 + 0 + 1 + + + CMP1 + Compare 1 + 1 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x14 + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x18 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRL + MODE2 Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x1 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x2 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x3 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x4 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x5 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x6 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x7 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x8 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0x9 + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xA + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0010 + + + ADDR + Address + 0 + 6 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 16 + 0x0000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x6 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x7 + 8 + 0x00 + + + ALARM0 + Alarm 0 Interrupt Enable + 0 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 6 + 1 + + + OVF + Overflow Interrupt Enable + 7 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x8 + 8 + 0x00 + + + ALARM0 + Alarm 0 + 0 + 1 + + + SYNCRDY + Synchronization Ready + 6 + 1 + + + OVF + Overflow + 7 + 1 + + + + + STATUS + Status + 0xA + 8 + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + DBGCTRL + Debug Control + 0xB + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + FREQCORR + Frequency Correction + 0xC + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x10 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x1C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22012.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000800 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + PAD[0] = TxD; PAD[1] = XCK + 0x0 + + + PAD1 + PAD[2] = TxD; PAD[3] = XCK + 0x1 + + + PAD2 + PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS + 0x2 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + SAMPASelect + + ADJ0 + 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 + 0x0 + + + ADJ1 + 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 + 0x1 + + + ADJ2 + 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 + 0x2 + + + ADJ3 + 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000C00 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42001000 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001400 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001800 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001C00 + + SERCOM5 + 14 + + + + SYSCTRL + U21002.0.1 + System Control + SYSCTRL + SYSCTRL_ + 0x40000800 + + 0 + 0x51 + registers + + + SYSCTRL + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 1 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 2 + 1 + + + OSC8MRDY + OSC8M Ready Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 8 + 1 + + + BOD33RDY + BOD33 Ready Interrupt Enable + 9 + 1 + + + BOD33DET + BOD33 Detection Interrupt Enable + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready Interrupt Enable + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout Interrupt Enable + 17 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + PCLKSR + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSC32KRDY + XOSC32K Ready + 1 + 1 + + + OSC32KRDY + OSC32K Ready + 2 + 1 + + + OSC8MRDY + OSC8M Ready + 3 + 1 + + + DFLLRDY + DFLL Ready + 4 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 5 + 1 + + + DFLLLCKF + DFLL Lock Fine + 6 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 7 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 8 + 1 + + + BOD33RDY + BOD33 Ready + 9 + 1 + + + BOD33DET + BOD33 Detection + 10 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 11 + 1 + + + DPLLLCKR + DPLL Lock Rise + 15 + 1 + + + DPLLLCKF + DPLL Lock Fall + 16 + 1 + + + DPLLLTO + DPLL Lock Timeout + 17 + 1 + + + + + XOSC + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + 0 + 2MHz + 0x0 + + + 1 + 4MHz + 0x1 + + + 2 + 8MHz + 0x2 + + + 3 + 16MHz + 0x3 + + + 4 + 30MHz + 0x4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + AAMPEN + Automatic Amplitude Control Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.592 ms + 2 + + + CYCLE4096 + 125.092 ms + 3 + + + CYCLE16384 + 500.092 ms + 4 + + + CYCLE32768 + 1000.092 ms + 5 + + + CYCLE65536 + 2000.092 ms + 6 + + + CYCLE131072 + 4000.092 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 8 + 0x1F + + + CALIB + Oscillator Calibration + 0 + 5 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + OSC8M + 8MHz Internal Oscillator (OSC8M) Control + 0x20 + 32 + 0x87070382 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESC + Oscillator Prescaler + 8 + 2 + + PRESCSelect + + 0 + 0x0 + + + 1 + 0x1 + + + 2 + 0x2 + + + 3 + 0x3 + + + + + CALIB + Oscillator Calibration + 16 + 12 + + + FRANGE + Oscillator Frequency Range + 30 + 2 + + FRANGESelect + + 0 + 4 to 6MHz + 0x0 + + + 1 + 6 to 8MHz + 0x1 + + + 2 + 8 to 11MHz + 0x2 + + + 3 + 11 to 15MHz + 0x3 + + + + + + + DFLLCTRL + DFLL48M Control + 0x24 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x28 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x2C + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x30 + 8 + 0x00 + + + READREQ + Read Request + 7 + 1 + + + + + BOD33 + 3.3V Brown-Out Detector (BOD33) Control + 0x34 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis + 2 + 1 + + + ACTION + BOD33 Action + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INTERRUPT + The BOD33 generates an interrupt + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MODE + Operation Mode + 8 + 1 + + + CEN + Clock Enable + 9 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1K + Divide clock by 1024 + 0x9 + + + DIV2K + Divide clock by 2048 + 0xA + + + DIV4K + Divide clock by 4096 + 0xB + + + DIV8K + Divide clock by 8192 + 0xC + + + DIV16K + Divide clock by 16384 + 0xD + + + DIV32K + Divide clock by 32768 + 0xE + + + DIV64K + Divide clock by 65536 + 0xF + + + + + LEVEL + BOD33 Threshold Level + 16 + 6 + + + + + VREG + Voltage Regulator System (VREG) Control + 0x3C + 16 + 0x0000 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + FORCELDO + Force LDO Voltage Regulator + 13 + 1 + + + + + VREF + Voltage References System (VREF) Control + 0x40 + 32 + 0x00000000 + + + TSEN + Temperature Sensor Enable + 1 + 1 + + + BGOUTEN + Bandgap Output Enable + 2 + 1 + + + CALIB + Bandgap Voltage Generator Calibration + 16 + 11 + + + + + DPLLCTRLA + DPLL Control A + 0x44 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Clock Activation + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x48 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + DPLL Control B + 0x4C + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0x0 + + + LBFILT + Low bandwidth filter + 0x1 + + + HBFILT + High bandwidth filter + 0x2 + + + HDFILT + High damping filter + 0x3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + REF0 + CLK_DPLL_REF0 clock reference + 0x0 + + + REF1 + CLK_DPLL_REF1 clock reference + 0x1 + + + GCLK + GCLK_DPLL clock reference + 0x2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out + 0x0 + + + 8MS + Time-out if no lock within 8 ms + 0x4 + + + 9MS + Time-out if no lock within 9 ms + 0x5 + + + 10MS + Time-out if no lock within 10 ms + 0x6 + + + 11MS + Time-out if no lock within 11 ms + 0x7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSTATUS + DPLL Status + 0x50 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + Output Clock Ready + 1 + 1 + + + ENABLE + DPLL Enable + 2 + 1 + + + DIV + Divider Enable + 3 + 1 + + + + + + + TC3 + U22121.3.1 + Basic Timer Counter + TC + TC_ + 0x42002C00 + + 0 + 0x20 + registers + + + TC3 + 18 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT8 Counter Value + 0x10 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period Value + 0x14 + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare/Capture + 0x18 + 8 + 0x00 + + + CC + Compare/Capture Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT16 Counter Value + 0x10 + 16 + 0x0000 + + + COUNT + Count Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare/Capture + 0x18 + 16 + 0x0000 + + + CC + Compare/Capture Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + TC Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + WAVEGEN + Waveform Generation Operation + 5 + 2 + + WAVEGENSelect + + NFRQ + 0 + + + MFRQ + 1 + + + NPWM + 2 + + + MPWM + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock. Reset the prescaler counter + 2 + + + + + + + READREQ + Read Request + 0x2 + 16 + 0x0000 + + + ADDR + Address + 0 + 5 + + + RCONT + Read Continuously + 14 + 1 + + + RREQ + Read Request + 15 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x02 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + CMD + Command + 6 + 2 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + + + + + CTRLC + Control C + 0x6 + 8 + 0x00 + + + INVEN0 + Output Waveform 0 Invert Enable + 0 + 1 + + + INVEN1 + Output Waveform 1 Invert Enable + 1 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 4 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x8 + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + EVCTRL + Event Control + 0xA + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + PPW + Period captured in CC0, pulse width in CC1 + 5 + + + PWP + Period captured in CC1, pulse width in CC0 + 6 + + + + + TCINV + TC Inverted Event Input + 4 + 1 + + + TCEI + TC Event Input + 5 + 1 + + + OVFEO + Overflow/Underflow Event Output Enable + 8 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xD + 8 + 0x00 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + SYNCRDY + Synchronization Ready Interrupt Enable + 3 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 4 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xE + 8 + 0x00 + + + OVF + Overflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + SYNCRDY + Synchronization Ready + 3 + 1 + + + MC0 + Match or Capture Channel 0 + 4 + 1 + + + MC1 + Match or Capture Channel 1 + 5 + 1 + + + + + STATUS + Status + 0xF + 8 + read-only + 0x08 + + + STOP + Stop + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + COUNT + COUNT32 Counter Value + 0x10 + 32 + 0x00000000 + + + COUNT + Count Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare/Capture + 0x18 + 32 + 0x00000000 + + + CC + Compare/Capture Value + 0 + 32 + + + + + + + + TC4 + 0x42003000 + + TC4 + 19 + + + + TC5 + 0x42003400 + + TC5 + 20 + + + + TC6 + 0x42003800 + + TC6 + 21 + + + + TC7 + 0x42003C00 + + TC7 + 22 + + + + TCC0 + U22131.2.2 + Timer Counter Control + TCC + TCC_ + 0x42002000 + + 0 + 0x80 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update of double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + PATTB + Pattern Buffer Busy + 16 + 1 + + + WAVEB + Wave Buffer Busy + 17 + 1 + + + PERB + Period Buffer Busy + 18 + 1 + + + CCB0 + Compare Channel Buffer 0 Busy + 19 + 1 + + + CCB1 + Compare Channel Buffer 1 Busy + 20 + 1 + + + CCB2 + Compare Channel Buffer 2 Busy + 21 + 1 + + + CCB3 + Compare Channel Buffer 3 Busy + 22 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + NONE + No blanking applied + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBV + Pattern Buffer Valid + 5 + 1 + + + WAVEBV + Wave Buffer Valid + 6 + 1 + + + PERBV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHERCY + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTB + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + WAVEB + Waveform Control Buffer + 0x68 + 32 + 0x00000000 + + + WAVEGENB + Waveform Generation Buffer + 0 + 3 + + WAVEGENBSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMPB + Ramp Mode Buffer + 4 + 2 + + RAMPBSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + + + CIPERENB + Circular Period Enable Buffer + 7 + 1 + + + CICCENB0 + Circular Channel 0 Enable Buffer + 8 + 1 + + + CICCENB1 + Circular Channel 1 Enable Buffer + 9 + 1 + + + CICCENB2 + Circular Channel 2 Enable Buffer + 10 + 1 + + + CICCENB3 + Circular Channel 3 Enable Buffer + 11 + 1 + + + POLB0 + Channel 0 Polarity Buffer + 16 + 1 + + + POLB1 + Channel 1 Polarity Buffer + 17 + 1 + + + POLB2 + Channel 2 Polarity Buffer + 18 + 1 + + + POLB3 + Channel 3 Polarity Buffer + 19 + 1 + + + SWAPB0 + Swap DTI Output Pair 0 Buffer + 24 + 1 + + + SWAPB1 + Swap DTI Output Pair 1 Buffer + 25 + 1 + + + SWAPB2 + Swap DTI Output Pair 2 Buffer + 26 + 1 + + + SWAPB3 + Swap DTI Output Pair 3 Buffer + 27 + 1 + + + + + PERB + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERB + Period Buffer Value + 0 + 24 + + + + + PERB_DITH4_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + PERB + Period Buffer Value + 4 + 20 + + + + + PERB_DITH5_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + PERB + Period Buffer Value + 5 + 19 + + + + + PERB_DITH6_MODE + Period Buffer + PERB + 0x6C + 32 + 0xFFFFFFFF + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + PERB + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCB[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCB + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCB_DITH4_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 4 + + + CCB + Channel Compare/Capture Buffer Value + 4 + 20 + + + + + 4 + 4 + CCB_DITH5_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 5 + + + CCB + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCB_DITH6_MODE[%s] + Compare and Capture Buffer + CCB[%s] + 0x70 + 32 + 0x00000000 + + + DITHERCYB + Dithering Buffer Cycle Number + 0 + 6 + + + CCB + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002400 + + TCC1 + 16 + + + + TCC2 + 0x42002800 + + TCC2 + 17 + + + + USB + U22221.0.3 + Universal Serial Bus + USB + USB_ + 0x41005000 + + 0 + 0x200 + registers + + + USB + 7 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Curren Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x05 + + + CQOS + Configuration Quality of Service + 0 + 2 + + CQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Quality of Service + 2 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Interrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22032.0.0 + Watchdog Timer + WDT + WDT_ + 0x40001000 + + 0 + 0x9 + registers + + + WDT + 2 + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + 8 + 8 clock cycles + 0x0 + + + 16 + 16 clock cycles + 0x1 + + + 32 + 32 clock cycles + 0x2 + + + 64 + 64 clock cycles + 0x3 + + + 128 + 128 clock cycles + 0x4 + + + 256 + 256 clock cycles + 0x5 + + + 512 + 512 clock cycles + 0x6 + + + 1K + 1024 clock cycles + 0x7 + + + 2K + 2048 clock cycles + 0x8 + + + 4K + 4096 clock cycles + 0x9 + + + 8K + 8192 clock cycles + 0xA + + + 16K + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + STATUS + Status + 0x7 + 8 + read-only + 0x00 + + + SYNCBUSY + Synchronization Busy + 7 + 1 + + + + + CLEAR + Clear + 0x8 + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 29 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 29 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 29 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 29 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/devices/atsamda1e14b.xsl b/svd/devices/atsamda1e14b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1e14b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1e15b.xsl b/svd/devices/atsamda1e15b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1e15b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1e16b.xsl b/svd/devices/atsamda1e16b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1e16b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1g14b.xsl b/svd/devices/atsamda1g14b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1g14b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1g15b.xsl b/svd/devices/atsamda1g15b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1g15b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1g16b.xsl b/svd/devices/atsamda1g16b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1g16b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1j14b.xsl b/svd/devices/atsamda1j14b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1j14b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1j15b.xsl b/svd/devices/atsamda1j15b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1j15b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamda1j16b.xsl b/svd/devices/atsamda1j16b.xsl new file mode 100644 index 00000000000..3730d72c2e6 --- /dev/null +++ b/svd/devices/atsamda1j16b.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/include/atsamda1.xsl b/svd/devices/include/atsamda1.xsl new file mode 100644 index 00000000000..91fad5b6f84 --- /dev/null +++ b/svd/devices/include/atsamda1.xsl @@ -0,0 +1,256 @@ + + + + + + + + + SERCOM0_RX + SERCOM0 RX Trigger + 0x01 + + + SERCOM0_TX + SERCOM0 TX Trigger + 0x02 + + + SERCOM1_RX + SERCOM1 RX Trigger + 0x03 + + + SERCOM1_TX + SERCOM1 TX Trigger + 0x04 + + + SERCOM2_RX + SERCOM2 RX Trigger + 0x05 + + + SERCOM2_TX + SERCOM2 TX Trigger + 0x06 + + + SERCOM3_RX + SERCOM3 RX Trigger + 0x07 + + + SERCOM3_TX + SERCOM3 TX Trigger + 0x08 + + + SERCOM4_RX + SERCOM4 RX Trigger + 0x09 + + + SERCOM4_TX + SERCOM4 TX Trigger + 0x0A + + + SERCOM5_RX + SERCOM5 RX Trigger + 0x0B + + + SERCOM5_TX + SERCOM5 TX Trigger + 0x0C + + + TCC0_OVF + TCC0 Overflow Trigger + 0x0D + + + TCC0_MC0 + TCC0 Match/Compare 0 Trigger + 0x0E + + + TCC0_MC1 + TCC0 Match/Compare 1 Trigger + 0x0F + + + TCC0_MC2 + TCC0 Match/Compare 2 Trigger + 0x10 + + + TCC0_MC3 + TCC0 Match/Compare 3 Trigger + 0x11 + + + TCC1_OVF + TCC1 Overflow Trigger + 0x12 + + + TCC1_MC0 + TCC1 Match/Compare 0 Trigger + 0x13 + + + TCC1_MC1 + TCC1 Match/Compare 1 Trigger + 0x14 + + + TCC2_OVF + TCC2 Overflow Trigger + 0x15 + + + TCC2_MC0 + TCC2 Match/Compare 0 Trigger + 0x16 + + + TCC2_MC1 + TCC2 Match/Compare 1 Trigger + 0x17 + + + TC3_OVF + TC3 Overflow Trigger + 0x18 + + + TC3_MC0 + TC3 Match/Compare 0 Trigger + 0x19 + + + TC3_MC1 + TC3 Match/Compare 1 Trigger + 0x1A + + + TC4_OVF + TC4 Overflow Trigger + 0x1B + + + TC4_MC0 + TC4 Match/Compare 0 Trigger + 0x1C + + + TC4_MC1 + TC4 Match/Compare 1 Trigger + 0x1D + + + TC5_OVF + TC5 Overflow Trigger + 0x1E + + + TC5_MC0 + TC5 Match/Compare 0 Trigger + 0x1F + + + TC5_MC1 + TC5 Match/Compare 1 Trigger + 0x20 + + + TC6_OVF + TC6 Overflow Trigger + 0x21 + + + TC6_MC0 + TC6 Match/Compare 0 Trigger + 0x22 + + + TC6_MC1 + TC6 Match/Compare 1 Trigger + 0x23 + + + TC7_OVF + TC7 Overflow Trigger + 0x24 + + + TC7_MC0 + TC7 Match/Compare 0 Trigger + 0x25 + + + TC7_MC1 + TC7 Match/Compare 1 Trigger + 0x26 + + + ADC_RESRDY + ADC Result Ready Trigger + 0x27 + + + DAC_EMPTY + DAC Empty Trigger + 0x28 + + + I2S_RX_0 + I2S RX 0 Trigger + 0x29 + + + I2S_RX_1 + I2S RX 1 Trigger + 0x2A + + + I2S_TX_0 + I2S TX 0 Trigger + 0x2B + + + I2S_TX_1 + I2S TX 1 Trigger + 0x2C + + + TCC3_OVF + TCC3 Overflow Trigger + 0x2D + + + TCC3_MC0 + TCC3 Match/Compare 0 Trigger + 0x2E + + + TCC3_MC1 + TCC3 Match/Compare 1 Trigger + 0x2F + + + TCC3_MC2 + Match/Compare 2 Trigger + 0x30 + + + TCC3_MC3 + Match/Compare 3 Trigger + 0x31 + + + +